SEC2410I-JZX-TR

SEC2410I-JZX-TR Datasheet

SEC2410/SEC4410 HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage

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SEC2410I-JZX	SEC2410I-JZX
SEC2410-JZX	SEC2410-JZX
SEC2410-JZX-TR	SEC2410-JZX-TR

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SEC2410/SEC4410 HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage PRODUCT FEATURES The SMSC SEC2410/SEC4410 are USB compliant, hi-speed bulk-only mass storage class peripheral controllers. They are intended to be used to read and write to popular flash media, including Secure Digital SD , and MultiMediaCardTM MMC families. The SMSC SEC2410/SEC4410 are fully integrated, single-chip solutions capable of ultra-high performance operation. Average sustained transfer rates exceeding 35 MB/s are possible if the media and host can support those rates. The SMSC SEC2410/SEC4410 includes provisions to read/write to secure media formats, as well as support AES encryption, without performance impact. General Features The SEC2410/SEC4410 is available in two lead-free RoHS compliant packages: 64-pin QFN 9x9 mm package 72-pin QFN 10x10 mm package that includes debug pins to interface to standard ARM debug tools Hardware-controlled data flow architecture for all selfmapped media Pipelined hardware support for access to non-selfmapped media Order number see next page with i denote the products that support the industrial temperature range of -40ºC to 85ºC Support included for secure media format on a licensed, customized basis SD Secure Hardware Features Single-chip flash media controller containing: A multiplexed interface for use with combo card sockets SD/MMC flash media reader/writer SDIO and MMC streaming mode support Extended configuration options Media Activity LED GPIO configuration and polarity Up to 32 GPIOs for special function use One GPIO with up to 200 mA drive On board 24 MHz crystal driver circuit Optional external 24 MHz clock input Datasheet Internal card power FET 200 mA "Fold-back" short circuit protection ARM M3 32-bit microprocessor 60 MHz execution speed at 1 cycle per instruction minimum 32 KBytes of internal SRAM for a general purpose scratchpad 96 KByte SRAM available for code execution 32 KByte internal code ROM JTAG interface Supports a single external V supply source internal regulators provide V internal core voltage for additional bill of materials and power savings Optimized pinout improves signal routing, easing implementation for improved signal integrity V reference voltage for HSIC SEC4410 only Flash Media Specification Compliance Secure Digital HS-SD, SDHC, SDXC TransFlashTM and reduced form factor media MultiMediaCard MMC version 1/4/8-bit eMMC version Software Features Customizable vendor-specific data Reduced memory footprint Applications Secure dongles and storage Flash media card reader/writers Desktop and mobile PCs Consumer A/V and media players/viewers Compatible with VistaTM and Vista ReadyBoostTM 7, XP, ME, 2K SP4 Apple Mac Linux Mass Storage Class Drivers SMSC SEC2410/SEC4410 DATASHEET HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage Datasheet Order Numbers: ORDER NUMBERS SEC2410/SEC2410-JZX SEC4410/SEC4410i-JZX SEC2410/SEC2410-AKZE SEC4410/SEC4410i-AKZE LEAD-FREE ROHS COMPLIANT PACKAGE 64QFN 72QFN Refer to Byte/Bit Ordering for the byte and bit ordering of data transmission and reception. DATASHEET SMSC SEC2410/SEC4410 HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage Datasheet start bit first nibble second Nibble always '0' Total 4096 bits or 512-byte last nibble 16-bit CRC end bit always '1' DAT3 block data length/4 4092 16-bit CRC DAT2 block data length/4 4093 16-bit CRC DAT1 block data length/4 4094 16-bit CRC DAT0 block data length/4 4095 16-bit CRC 4 bit Data Bus with DAT0-3 Figure Data Format with DAT3-0 SD Clock Modulation during Block Data Transfer SDC modulates the SD_CLK signal during the block data read/write transfer. In the block data write operation, SDC drives the SD_CLK and data, when it has data to transmit to the SD/MMC device. Otherwise, SDC stops the SD_CLK and not drive the data line when it is not ready to transmit the data to the SD/MMC device. In the block data read operation, SDC drives the SD_CLK and sample the data lines, when it is ready to receive the data from SD/MMC device. Otherwise, SDC stops the SD_CLK and does not sample the data line, when it is not ready to receive the data from SD/MMC device. SD_CLK stay high when SDC stop driving SD_CLK signal. SDC CRC Generator and Checker CRC16 Generator/Checker is implemented to support the CRC generation and checking on the DAT lines. The 16-bit CRC is appended to the last bit of data to be transmitted from the SDC_DATA_XSR register. The CRC16 Generator/Checker checks the incoming 16-bit CRC after the last byte of data is received from the SDC device. The CRC_ERR bit in SDC_STAT register is set, if there is a CRC error detected. CRC7 Generator/Checker is implemented to support the CRC generation and checking for the COMMAND and RESPONSE data transfer. A 7-bit CRC is generated for any COMMAND packet to the SD device. As to the CRC7 Checker, it is implemented to check the incoming RESPONSE packet, if the CRC check is needed. Refer to the mode setting table in the section of SDC_MODE_CTL register for the CRC of each type of command and response. SMSC SEC2410/SEC4410 DATASHEET HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage Datasheet Byte/Bit Ordering The byte order of data block transmitted or received to or from SD/MMC card is in little-endian order. The byte order of data block transmitted or received to or from FMDU is in little-endian order as well. Therefore, the least significant byte LSB of data block is the first byte to be transmitted or received by SDC, and the most significant byte MSB of data block is the last byte to be transmitted or received by SDC. The most significant bit MSb of each byte is the first bit to be transmitted or received by SDC. The least significant bit LSb of each byte is the last bit to be transmitted or received by SDC. SDC SDIO Support: SEC2410/SEC4410 Supports the following enhanced SDIO Features SDIO Interrupt 1-bit and 4-bit modes SDIO Read Wait SDIO Suspend Resume SDIO Interrupt Support: The capability to support SDIO Interrupts is card dependent, firmware must verify that an SDIO card has the capability to support Interrupts prior to enabling interrupt support in the SDC. For Interrupt support: Firmware Responsibility i. Verify that the SDIO card supports Interrupts j. Enable Interrupt support by asserting the SDIOINT_EN bit k. When an interrupt occurs signified by SDIO_INTR = ‘1’ i. Access SDIO card and determine the source of the interrupt ii. Clear the SDIO card interrupt if necessary iii. Clear the SDIO_INTR Hardware Responsibility l. When SDIOINT_EN = ‘1’, monitor DAT[3] & DAT[1] for an interrupt condition on DAT1 when a data transfer is not in progress m. If an interrupt condition is detected, assert the SDIO_INTR bit Note For Interrupt support when the card is placed in a low-power state i.e. SD Card clock is stopped , the SDC and the card must both be configured for 1-bit operation. Note The SDC hardware does not support wakeup from a low power mode. To support wakeup from SDIO, the DAT1 line must be connected to a GPIO configured as an input. That GPIO must have the interrupts enabled. That interrupt must be routed to the WAKE_SRC register. Note During a Multi-Block read operation, An SD Card will continue to transfer data until a Stop Command is issued. The SDC will have been programmed for a particular data transfer size, and after the proper amount of data is transferred, the SDC will begin to monitor for SDIO Interrupts. Since the SD Card is still transferring data, the SDC will see the data transfer as an SDIO Interrupt. Firmware must do one of the following: Mask interrupts during the interval that the SDC will mistakenly misinterpret a transfer as an SDIO Interrupt. Temporarily disable SDIO Interrupt support until a stop command is received by the SD Card. SMSC SEC2410/SEC4410 DATASHEET HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage Datasheet SDIO Read Wait Support The capability to support SDIO Read Wait is card dependent firmware must verify that an SDIO card has the capability to support Read Wait prior to enabling interrupt support in the SDC. For Read Wait support: Firmware Responsibility: n. Set the SDIO_WAIT bit when a READ WAIT operation is required o. Send command s to the SDIO card p. When operation is complete, clear the SDIO_WAIT bit Hardware Responsibility q. When SDIO_WAIT = ‘1’ i. Retain all current read state and data information for the read operation that is being stalled. ii. Assert the READ WAIT condition on DAT2 according to SDIO spec timing restrictions, and delay sending any SD commands until DAT2 is asserted . iii. When DAT2 is asserted, send commands as directed by firmware. r. When SDIO_WAIT = ‘0’ i. Negate DAT2 ii. Resume the stalled read operation if applicable iii. Return to normal operation. SDIO Suspend/Resume Support: The SEC2410/SEC4410 hardware has had no specific enhancements to support SDIO Suspend/Resume. Suspend/Resume support is dependent upon firmware. DATASHEET SMSC SEC2410/SEC4410 HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage Chapter 20 Second Secured Digital SD/MMC Controller Datasheet SEC2410/SEC4410 has a second SD controller SD2 . The control registers are located on the CR_X32 bus. Table below shows the register addresses of the SD2. ADDRESS In CR_X32 Space 0x2800 0x2801 0x280D 0x2802 0x2803 0x2804 0x2806 0x2808 0x280A 0x280C 0x280E~ 0x280F 0x2810~ 0x281F 0x2844 0x2848~ 0x2849 0x284A 0x284B 0x284C 0x284D 0x2880 Table SD2/MMC2 Controller SDC2 Interface Registers NAME Once the EP_CNT has gone to zero, and the CBWP has received an acknowledge from the card controller, the CBWP writes the CSW buffer and posts a CN for the CSW. In this examble, it does this by writing a 0x87 to the SIE EP2_READ work queue. The CBWP does not have to wait for the data to be sent to the host before sending the CSW because the CSW is enqueued behind the data because of the enforced ordering. After the USB host reads the CSW, the SIE sends a CN to the FMDU. In this example, it does this by writing a 0x4 to FMDU EP1 endpoint. The CN for the CSW is the last act of the transfer. The cycle is repeated by the CBWP posting a buffer for the CBW at the SIE EP2_WRITE queue. SMSC SEC2410/SEC4410 DATASHEET HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage Datasheet Chapter 22 Bootloader The secure bootloader in the SEC2410/SEC4410 provides the ability to boot and execute a firmware image from multiple media sources in both secure and non-secure modes. The secure and non-secure boot modes search for a firmware boot image on the available boot sources SPI Flash or Flash Media SD1/MMC1 and SD2/MMC2 . If a valid image is found, the bootloader will execute the image. The secure bootloader also provides the functionality to download a firmware image over USB into internal memory for execution. The firmware boot image details are outlined in the Secure Bootloader Reference Guide The secure boot mode requires that a firmware boot image is stored on a boot source in an encrypted state that is authenticated and decrypted for execution in the device. The encryption and authentication keys for the secure boot will be stored in a lockable store in OTP. The keys in the OTP are provisioned by the manufacturer prior to the initial boot image being stored on the boot source. The secure boot mode does not allow code to execute in place on the external SPI Flash, rather the image is loaded into the instruction SRAM from the external source. The secure bootloader also provides the functionality to update the firmware boot image on the media source by a USB host. Through various procedures, the bootloader can enter firmware upgrade mode, which provides the capability for an application on the USB host to store a valid boot image on the source media. The bootloader detects that it should not attempt to load the image in the media source, but instead enter firmware upgrade mode. The non-secure boot mode does not require authentication of the boot image and can be executed from the external SPI Flash. The firmware image can either be solely copied to instruction SRAM and only execute from instruction SRAM or it can be partially located and executed in the external SPI Flash and instruction SRAM. Boot Process Booting from Multiple Devices The bootloader supports booting from multiple sources. The bootloader will attempt to boot from the acceptable devices in the following order SPI Flash SD1/MMC1 SD2/MMC2 Locating the Firmware Image After power on reset, the SEC2410/SEC4410 initially boots to internal ROM. Code execution begins by searching for a valid firmware image on one of the acceptable boot devices. The presence of a valid boot image is searched in the following order: The bootloader checks to see whether firmware update mode has been enabled. When enabled, firmware update is forced and the bootloader will not attempt to boot a firmware image. In this case, the bootloader ends the boot process and switches to the firmware update mode. If this mode has not been enabled, the bootloader will continue with the boot process. The OTP security configuration is the next item checked by the bootloader. If a valid signature is detected, the bootloader continues to step Otherwise, non-secure mode is selected and the bootloader continues to step In secure mode, the bootloader firmware checks an additional bit to determine whether secure mode was selected. If set, the bootloader with continue in secure mode if not set, the bootloader with proceed in non-secure mode. DATASHEET SMSC SEC2410/SEC4410 HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage Datasheet Starting with the SPI Flash device the bootloader checks whether the device is present if present it initializes the SPI Flash interface and continues to step If the SPI Flash device does not initialize successfully or is not present, the bootloader repeats step 4 with the next device the order is provided in Section If the bootloader is unable to detect and initialize a device, the bootloader ends the boot process and switches to the firmware update mode. The bootloader firmware checks whether the media device contains a valid firmware image using the method outlined in Section Validate Firmware Image Existence. If a valid firmware image exists, the bootloader continues to the next step. If a valid image is not found, step 3 is repeated with the next device. If there are no remaining devices to check, the bootloader ends the boot process and switches to the firmware update mode. Detect and Initialize Devices The bootloader will attempt to detect and initialize the available devices. The boot devices will be initialized based on the method specific to the boot device type. These methods are outlined in the Secure Bootloader Reference Guide SPI Flash: The SPI Flash device will be detected and initialized using the String ID in the Media Layout Descriptor MLD . The existence of the String ID will verify that an external SPI Flash device exists and that the SPI has been initialized for read/write access to the device. Since the SPI controller supports SPI interface modes 0 and 3 and supports dual read mode, four attempts to read the String ID are made. Mode 0, dual output mode opcode 0x3b Mode 3, dual output mode opcode 0x3b Mode 0, single output mode opcode 0x0b Mode 3, single output mode opcode 0x0b If the String ID is not read correctly after the 4th configuration then it is assumed a valid SPI Flash device is not available. This can occur if either a SPI Flash device is not connected or the MLD has not been programmed in the SPI Flash memory. SD/MMC Media: The SD/MMC media devices will be initialized per the SD/MMC specification. The media devices will be detected as present based on the state of the card detect GPIO. Validate Firmware Image Existence

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SEC2410/SEC4410 HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage

PRODUCT FEATURES

The SMSC SEC2410/SEC4410 are USB compliant, hi-speed bulk-only mass storage class peripheral controllers. They are intended to be used to read and write to popular flash media, including Secure Digital SD , and MultiMediaCardTM MMC families.

The SMSC SEC2410/SEC4410 are fully integrated, single-chip solutions capable of ultra-high performance operation. Average sustained transfer rates exceeding 35 MB/s are possible if the media and host can support those rates. The SMSC SEC2410/SEC4410 includes provisions to read/write to secure media formats, as well as support AES encryption, without performance impact.

General Features The SEC2410/SEC4410 is available in two lead-free

RoHS compliant packages:
64-pin QFN 9x9 mm package 72-pin QFN 10x10 mm package that includes debug
pins to interface to standard ARM debug tools

Hardware-controlled data flow architecture for all selfmapped media

Pipelined hardware support for access to non-selfmapped media

Order number see next page with i denote the products that support the industrial temperature range of -40ºC to 85ºC

Support included for secure media format on a licensed, customized basis

SD Secure

Hardware Features Single-chip flash media controller containing:

A multiplexed interface for use with combo card sockets SD/MMC flash media reader/writer

SDIO and MMC streaming mode support Extended configuration options Media Activity LED GPIO configuration and polarity

Up to 32 GPIOs for special function use One GPIO with up to 200 mA drive

On board 24 MHz crystal driver circuit Optional external 24 MHz clock input

Datasheet

Internal card power FET 200 mA "Fold-back" short circuit protection

ARM M3 32-bit microprocessor
60 MHz execution speed at 1 cycle per instruction minimum
32 KBytes of internal SRAM for a general purpose scratchpad
96 KByte SRAM available for code execution 32 KByte internal code ROM JTAG interface

Supports a single external V supply source internal regulators provide V internal core voltage for additional bill of materials and power savings

Optimized pinout improves signal routing, easing implementation for improved signal integrity

V reference voltage for HSIC SEC4410 only

Flash Media Specification Compliance Secure Digital

HS-SD, SDHC, SDXC TransFlashTM and reduced form factor media

MultiMediaCard

MMC version 1/4/8-bit eMMC version

Software Features Customizable vendor-specific data Reduced memory footprint

Applications Secure dongles and storage Flash media card reader/writers Desktop and mobile PCs Consumer A/V and media players/viewers Compatible with

VistaTM and Vista ReadyBoostTM 7, XP, ME, 2K SP4 Apple Mac Linux Mass Storage Class Drivers

SMSC SEC2410/SEC4410

DATASHEET

HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage Datasheet

Order Numbers:

ORDER NUMBERS SEC2410/SEC2410-JZX SEC4410/SEC4410i-JZX SEC2410/SEC2410-AKZE SEC4410/SEC4410i-AKZE

LEAD-FREE ROHS COMPLIANT

PACKAGE 64QFN 72QFN
Refer to Byte/Bit Ordering for the byte and bit ordering of data transmission and reception.

DATASHEET

SMSC SEC2410/SEC4410

HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage Datasheet
start bit first nibble second Nibble always '0'

Total 4096 bits or 512-byte
last nibble 16-bit CRC
end bit always '1'

DAT3
block data length/4
4092
16-bit CRC

DAT2
block data length/4
4093
16-bit CRC

DAT1
block data length/4
4094
16-bit CRC

DAT0
block data length/4
4095
16-bit CRC
4 bit Data Bus with DAT0-3

Figure Data Format with DAT3-0

SD Clock Modulation during Block Data Transfer

SDC modulates the SD_CLK signal during the block data read/write transfer.

In the block data write operation, SDC drives the SD_CLK and data, when it has data to transmit to the SD/MMC device. Otherwise, SDC stops the SD_CLK and not drive the data line when it is not ready to transmit the data to the SD/MMC device.

In the block data read operation, SDC drives the SD_CLK and sample the data lines, when it is ready to receive the data from SD/MMC device. Otherwise, SDC stops the SD_CLK and does not sample the data line, when it is not ready to receive the data from SD/MMC device.

SD_CLK stay high when SDC stop driving SD_CLK signal.

SDC CRC Generator and Checker

CRC16 Generator/Checker is implemented to support the CRC generation and checking on the DAT lines. The 16-bit CRC is appended to the last bit of data to be transmitted from the SDC_DATA_XSR register.

The CRC16 Generator/Checker checks the incoming 16-bit CRC after the last byte of data is received from the SDC device. The CRC_ERR bit in SDC_STAT register is set, if there is a CRC error detected.

CRC7 Generator/Checker is implemented to support the CRC generation and checking for the COMMAND and RESPONSE data transfer. A 7-bit CRC is generated for any COMMAND packet to the SD device.

As to the CRC7 Checker, it is implemented to check the incoming RESPONSE packet, if the CRC check is needed.

Refer to the mode setting table in the section of SDC_MODE_CTL register for the CRC of each type of command and response.

SMSC SEC2410/SEC4410

DATASHEET

HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage

Datasheet
Byte/Bit Ordering

The byte order of data block transmitted or received to or from SD/MMC card is in little-endian order. The byte order of data block transmitted or received to or from FMDU is in little-endian order as well. Therefore, the least significant byte LSB of data block is the first byte to be transmitted or received by SDC, and the most significant byte MSB of data block is the last byte to be transmitted or received by SDC.

The most significant bit MSb of each byte is the first bit to be transmitted or received by SDC. The least significant bit LSb of each byte is the last bit to be transmitted or received by SDC.

SDC SDIO Support:

SEC2410/SEC4410 Supports the following enhanced SDIO Features SDIO Interrupt 1-bit and 4-bit modes SDIO Read Wait SDIO Suspend Resume

SDIO Interrupt Support:

The capability to support SDIO Interrupts is card dependent, firmware must verify that an SDIO card has the capability to support Interrupts prior to enabling interrupt support in the SDC.

For Interrupt support:

Firmware Responsibility
i. Verify that the SDIO card supports Interrupts j. Enable Interrupt support by asserting the SDIOINT_EN bit k. When an interrupt occurs signified by SDIO_INTR = ‘1’
i. Access SDIO card and determine the source of the interrupt ii. Clear the SDIO card interrupt if necessary iii. Clear the SDIO_INTR

Hardware Responsibility l. When SDIOINT_EN = ‘1’, monitor DAT[3] & DAT[1] for an interrupt condition on DAT1 when a data
transfer is not in progress m. If an interrupt condition is detected, assert the SDIO_INTR bit

Note For Interrupt support when the card is placed in a low-power state i.e. SD Card clock is stopped , the SDC and the card must both be configured for 1-bit operation.

Note The SDC hardware does not support wakeup from a low power mode. To support wakeup from SDIO, the DAT1 line must be connected to a GPIO configured as an input. That GPIO must have the interrupts enabled. That interrupt must be routed to the WAKE_SRC register.

Note During a Multi-Block read operation, An SD Card will continue to transfer data until a Stop Command is issued. The SDC will have been programmed for a particular data transfer size, and after the proper amount of data is transferred, the SDC will begin to monitor for SDIO Interrupts. Since the SD Card is still transferring data, the SDC will see the data transfer as an SDIO Interrupt. Firmware must do one of the following:

Mask interrupts during the interval that the SDC will mistakenly misinterpret a transfer as an SDIO Interrupt.

Temporarily disable SDIO Interrupt support until a stop command is received by the SD Card.

SMSC SEC2410/SEC4410

DATASHEET

HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage

Datasheet

SDIO Read Wait Support

The capability to support SDIO Read Wait is card dependent firmware must verify that an SDIO card has the capability to support Read Wait prior to enabling interrupt support in the SDC.

For Read Wait support:

Firmware Responsibility:
n. Set the SDIO_WAIT bit when a READ WAIT operation is required o. Send command s to the SDIO card p. When operation is complete, clear the SDIO_WAIT bit Hardware Responsibility q. When SDIO_WAIT = ‘1’
i. Retain all current read state and data information for the read operation that is being stalled. ii. Assert the READ WAIT condition on DAT2 according to SDIO spec timing restrictions, and delay sending any SD commands until DAT2 is asserted . iii. When DAT2 is asserted, send commands as directed by firmware. r. When SDIO_WAIT = ‘0’ i. Negate DAT2 ii. Resume the stalled read operation if applicable iii. Return to normal operation.

SDIO Suspend/Resume Support:

The SEC2410/SEC4410 hardware has had no specific enhancements to support SDIO Suspend/Resume. Suspend/Resume support is dependent upon firmware.

DATASHEET

SMSC SEC2410/SEC4410

HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage

Chapter 20 Second Secured Digital SD/MMC Controller

Datasheet

SEC2410/SEC4410 has a second SD controller SD2 . The control registers are located on the CR_X32 bus. Table below shows the register addresses of the SD2.

ADDRESS In CR_X32 Space 0x2800 0x2801 0x280D 0x2802 0x2803 0x2804 0x2806 0x2808 0x280A 0x280C 0x280E~ 0x280F 0x2810~ 0x281F 0x2844 0x2848~ 0x2849 0x284A 0x284B
0x284C
0x284D 0x2880

Table SD2/MMC2 Controller SDC2 Interface Registers

NAME
Once the EP_CNT has gone to zero, and the CBWP has received an acknowledge from the card controller, the CBWP writes the CSW buffer and posts a CN for the CSW. In this examble, it does this by writing a 0x87 to the SIE EP2_READ work queue. The CBWP does not have to wait for the data to be sent to the host before sending the CSW because the CSW is enqueued behind the data because of the enforced ordering.

After the USB host reads the CSW, the SIE sends a CN to the FMDU. In this example, it does this by writing a 0x4 to FMDU EP1 endpoint. The CN for the CSW is the last act of the transfer.

The cycle is repeated by the CBWP posting a buffer for the CBW at the SIE EP2_WRITE queue.

SMSC SEC2410/SEC4410

DATASHEET

HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage Datasheet

Chapter 22 Bootloader

The secure bootloader in the SEC2410/SEC4410 provides the ability to boot and execute a firmware image from multiple media sources in both secure and non-secure modes. The secure and non-secure boot modes search for a firmware boot image on the available boot sources SPI Flash or Flash Media SD1/MMC1 and SD2/MMC2 . If a valid image is found, the bootloader will execute the image. The secure bootloader also provides the functionality to download a firmware image over USB into internal memory for execution. The firmware boot image details are outlined in the Secure Bootloader Reference Guide

The secure boot mode requires that a firmware boot image is stored on a boot source in an encrypted state that is authenticated and decrypted for execution in the device. The encryption and authentication keys for the secure boot will be stored in a lockable store in OTP. The keys in the OTP are provisioned by the manufacturer prior to the initial boot image being stored on the boot source. The secure boot mode does not allow code to execute in place on the external SPI Flash, rather the image is loaded into the instruction SRAM from the external source.

The secure bootloader also provides the functionality to update the firmware boot image on the media source by a USB host. Through various procedures, the bootloader can enter firmware upgrade mode, which provides the capability for an application on the USB host to store a valid boot image on the source media. The bootloader detects that it should not attempt to load the image in the media source, but instead enter firmware upgrade mode.

The non-secure boot mode does not require authentication of the boot image and can be executed from the external SPI Flash. The firmware image can either be solely copied to instruction SRAM and only execute from instruction SRAM or it can be partially located and executed in the external SPI Flash and instruction SRAM.

Boot Process

Booting from Multiple Devices

The bootloader supports booting from multiple sources. The bootloader will attempt to boot from the acceptable devices in the following order SPI Flash

SD1/MMC1

SD2/MMC2

Locating the Firmware Image

After power on reset, the SEC2410/SEC4410 initially boots to internal ROM. Code execution begins by searching for a valid firmware image on one of the acceptable boot devices. The presence of a valid boot image is searched in the following order:

The bootloader checks to see whether firmware update mode has been enabled. When enabled, firmware update is forced and the bootloader will not attempt to boot a firmware image. In this case, the bootloader ends the boot process and switches to the firmware update mode. If this mode has not been enabled, the bootloader will continue with the boot process.

The OTP security configuration is the next item checked by the bootloader. If a valid signature is detected, the bootloader continues to step Otherwise, non-secure mode is selected and the bootloader continues to step

In secure mode, the bootloader firmware checks an additional bit to determine whether secure mode was selected. If set, the bootloader with continue in secure mode if not set, the bootloader with proceed in non-secure mode.

DATASHEET

SMSC SEC2410/SEC4410

HS Endpoint Processor with USB Smart Card, & FMC for Secure Token & Storage

Datasheet

Starting with the SPI Flash device the bootloader checks whether the device is present if present it initializes the SPI Flash interface and continues to step

If the SPI Flash device does not initialize successfully or is not present, the bootloader repeats step 4 with the next device the order is provided in Section

If the bootloader is unable to detect and initialize a device, the bootloader ends the boot process and switches to the firmware update mode.

The bootloader firmware checks whether the media device contains a valid firmware image using the method outlined in Section Validate Firmware Image Existence. If a valid firmware image exists, the bootloader continues to the next step. If a valid image is not found, step 3 is repeated with the next device. If there are no remaining devices to check, the bootloader ends the boot process and switches to the firmware update mode.

Detect and Initialize Devices

The bootloader will attempt to detect and initialize the available devices. The boot devices will be initialized based on the method specific to the boot device type. These methods are outlined in the Secure Bootloader Reference Guide

SPI Flash:

The SPI Flash device will be detected and initialized using the String ID in the Media Layout Descriptor MLD . The existence of the String ID will verify that an external SPI Flash device exists and that the SPI has been initialized for read/write access to the device. Since the SPI controller supports SPI interface modes 0 and 3 and supports dual read mode, four attempts to read the String ID are made.

Mode 0, dual output mode opcode 0x3b

Mode 3, dual output mode opcode 0x3b

Mode 0, single output mode opcode 0x0b

Mode 3, single output mode opcode 0x0b

If the String ID is not read correctly after the 4th configuration then it is assumed a valid SPI Flash device is not available. This can occur if either a SPI Flash device is not connected or the MLD has not been programmed in the SPI Flash memory.

SD/MMC Media:

The SD/MMC media devices will be initialized per the SD/MMC specification. The media devices will be detected as present based on the state of the card detect GPIO.

Validate Firmware Image Existence

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Datasheet ID: SEC2410I-JZX-TR 648197