LPC47N227-MV

LPC47N227-MV Datasheet

LPC47N227

Part	Datasheet
LPC47N227-MV	LPC47N227-MV (pdf)

PDF Datasheet Preview
LPC47N227 100 Pin Super I/O with LPC Interface for Notebook Applications Volt Operation 5V Tolerant PC99 and ACPI 1.0b Compliant Programmable Wakeup Event Interface nIO_PME Pin SMI Support nIO_SMI Pin GPIOs 29 Two IRQ Input Pins XNOR Chain Intelligent Auto Power Management 2.88MB Super I/O Floppy Disk Controller - Licensed CMOS 765B Floppy Disk Controller - Software and Register Compatible with SMSC's Proprietary 82077AA Compatible Core - Supports One Floppy Drive Directly - Configurable Open Drain/Push-Pull Output Drivers - Supports Vertical Recording Format - 16-Byte Data FIFO - 100% IBM Compatibility - Detects All Overrun and Underrun Conditions - Sophisticated Power Control Circuitry PCC Including Multiple Powerdown Modes for Reduced Power Consumption - DMA Enable Logic - Data Rate and Drive Control Registers - Swap Drives A and B - Non-Burst Mode DMA Option - 48 Base I/O Address, 15 IRQ and 3 DMA Options - Forceable Write Protect and Disk Change Controls Floppy Disk Available on Parallel Port Pins ACPI Compliant Enhanced Digital Data Separator - 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates - Programmable Precompensation Modes Serial Ports - Two Full Function Serial Ports - High Speed NS16C550 Compatible UARTs with Send/Receive 16-Byte FIFOs - Supports 230k and 460k Baud - Programmable Baud Rate Generator - Modem Control Circuitry Infrared Communications Controller - IrDA v1.2 4Mbps , HPSIR, ASKIR, Consumer IR Support - 2 IR Ports - 96 Base I/O Address, 15 IRQ Options and 3 DMA Options Multi-Mode Parallel Port with ChiProtect - Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional Parallel Port - Enhanced Parallel Port EPP Compatible EPP and EPP IEEE 1284 Compliant - IEEE 1284 Compliant Enhanced Capabilities Port ECP - ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On - 192 Base I/O Address, 15 IRQ and 3 DMA Options LPC Bus Host Interface - Multiplexed Command, Address and Data Bus - 8-Bit I/O Transfers - 8-Bit DMA Transfers - 16-Bit Address Qualification - Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems - PCI nCLKRUN Support - Power Management Event nIO_PME Interface Pin 100 Pin TQN, lead-free RoHS compliant package and 100 Pin STQN, lead-free RoHS compliant package The SMSC LPC47N227 is a 3.3V PC 99 and ACPI 1.0b compliant Super I/O Controller. The LPC47N227 implements the LPC interface, a pin reduced ISA interface which provides the same or better performance as the ISA/X-bus with a substantial savings in pins used. The part also includes 29 GPIO pins. The LPC47N227 incorporates SMSC’s true CMOS 765B floppy disk controller, advanced digital data separator, 16byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support and one floppy direct drive support. The LPC47N227 does not require any external filter components, is easy to use and offers lower system cost and reduced board area. The LPC47N227 is software and register compatible with SMSC’s proprietary 82077AA core. The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and provides data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC’s patented data SMSC DB LPC47N227 PRODUCT PREVIEW 100 Pin Super I/O with LPC Interface for Notebook Applications separator technology allowing for ease of testing and use. The LPC47N227 supports both 1Mbps and 2Mbps data rates and vertical recording operation at 1Mbps Data Rate. The LPC47N227 also features a full 16-bit internally decoded address bus, a Serial IRQ interface with PCI nCLKRUN support, relocatable configuration ports and three DMA channel options. Both on-chip UARTs are compatible with the NS16C550. One UART includes additional support for a Serial Infrared Interface that complies with IrDA v1.2 Fast IR , HPSIR, and ASKIR formats used by Sharp and other PDAs , as well as Consumer IR. The parallel port is compatible with IBM PC/AT architectures, as well as IEEE 1284 EPP and ECP. The parallel port ChiProtect circuitry prevents damage caused by an attached powered printer when the LPC47N227 is not powered. The LPC47N227 incorporates sophisticated power control circuitry PCC . The PCC supports multiple low power down modes. The LPC47N227 also features Software Configurable Logic SCL for ease of use. SCL allows programmable system configuration of key functions such as the FDC, parallel port, and UARTs. The LPC47N227 supports the ISA Plug-and-Play Standard Version 1.0a and provides the recommended functionaity to support Windows ‘95/’98 and PC99. The I/O Address, DMA Channel and Hardware IRQ of each device in the LPC47N227 may be reprogrammed through the internal configuration registers. There are 192 I/O address location options, a Serialized IRQ interface, and three DMA channels. ORDERING INFORMATION Order Numbers: LPC47N227-MT for 100 Pin TQN, Lead-free RoHS Compliant Package LPC47N227-MV for 100 Pin STQN, Lead-free RoHS Compliant Package 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 631 435-6000, FAX 631 273-3123 Copyright 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order the "Terms of Sale Agreement" . The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at SMSC is a registered trademark of Standard Microsystems Corporation “SMSC” . Product names and company names are the trademarks of their respective holders. PRODUCT PREVIEW SMSC DB LPC47N227 100 Pin Super I/O with LPC Interface for Notebook Applications BLOCK DIAGRAM nIO_SMI* nIO_PME SMI PME WDT CONTROL, ADDRESS, DATA SER_IRQ PCI_CLK LAD0 LAD1 LAD2 LAD3 nLFRAME nLDRQ nPCI_RESET nLPCPD nCLKRUN SERIAL IRQ LPC BUS INTERFACE VTR Vcc Vss CLOCK GEN CLOCKI CONFIGURATION REGISTERS ACPI BLOCK SMSC WDATA PROPRIETARY WCLOCK DIGITAL 82077 DATA COMPATIBLE SEPERATOR VERTICAL PRE- FLOPPY DISK COMPENSATION CONTROLLER RCLOCK CORE RDATA nMTR0, nDS0, nDIR, nTRK0, nSTEP, DRVDEN0, nDSKCHG, nWGATE, HDSEL, nINDEX, DRVDEN1, nWDATA nWRTPRT, nRDATA nWDATA nRDATA

PDF Datasheet Preview

LPC47N227
100 Pin Super I/O with LPC Interface for Notebook Applications

Volt Operation 5V Tolerant PC99 and ACPI 1.0b Compliant Programmable Wakeup Event Interface nIO_PME

Pin SMI Support nIO_SMI Pin GPIOs 29 Two IRQ Input Pins XNOR Chain Intelligent Auto Power Management 2.88MB Super I/O Floppy Disk Controller
- Licensed CMOS 765B Floppy Disk Controller
- Software and Register Compatible with SMSC's Proprietary 82077AA Compatible

Core
- Supports One Floppy Drive Directly - Configurable Open Drain/Push-Pull Output

Drivers
- Supports Vertical Recording Format - 16-Byte Data FIFO
- 100% IBM Compatibility
- Detects All Overrun and Underrun Conditions - Sophisticated Power Control Circuitry PCC

Including Multiple Powerdown Modes for

Reduced Power Consumption
- DMA Enable Logic
- Data Rate and Drive Control Registers
- Swap Drives A and B - Non-Burst Mode DMA Option
- 48 Base I/O Address, 15 IRQ and 3 DMA

Options
- Forceable Write Protect and Disk Change

Controls Floppy Disk Available on Parallel Port Pins ACPI

Compliant Enhanced Digital Data Separator
- 2 Mbps, 1 Mbps, 500 Kbps, 300 Kbps, 250 Kbps Data Rates
- Programmable Precompensation Modes

Serial Ports - Two Full Function Serial Ports - High Speed NS16C550 Compatible UARTs with Send/Receive 16-Byte FIFOs - Supports 230k and 460k Baud - Programmable Baud Rate Generator - Modem Control Circuitry

Infrared Communications Controller - IrDA v1.2 4Mbps , HPSIR, ASKIR, Consumer IR Support - 2 IR Ports - 96 Base I/O Address, 15 IRQ Options and 3 DMA Options

Multi-Mode Parallel Port with ChiProtect - Standard Mode IBM PC/XT, PC/AT, and PS/2 Compatible Bidirectional Parallel Port - Enhanced Parallel Port EPP Compatible EPP and EPP IEEE 1284 Compliant - IEEE 1284 Compliant Enhanced Capabilities Port ECP - ChiProtect Circuitry for Protection Against Damage Due to Printer Power-On - 192 Base I/O Address, 15 IRQ and 3 DMA Options

LPC Bus Host Interface - Multiplexed Command, Address and Data Bus - 8-Bit I/O Transfers - 8-Bit DMA Transfers - 16-Bit Address Qualification - Serial IRQ Interface Compatible with Serialized IRQ Support for PCI Systems - PCI nCLKRUN Support - Power Management Event nIO_PME Interface Pin
100 Pin TQN, lead-free RoHS compliant package and 100 Pin STQN, lead-free RoHS compliant package

The SMSC LPC47N227 is a 3.3V PC 99 and ACPI 1.0b compliant Super I/O Controller. The LPC47N227 implements the LPC interface, a pin reduced ISA interface which provides the same or better performance as the ISA/X-bus with a substantial savings in pins used. The part also includes 29 GPIO pins.

The LPC47N227 incorporates SMSC’s true CMOS 765B floppy disk controller, advanced digital data separator, 16byte data FIFO, two 16C550 compatible UARTs, one Multi-Mode parallel port with ChiProtect circuitry plus EPP and ECP support and one floppy direct drive support. The LPC47N227 does not require any external filter components, is easy to use and offers lower system cost and reduced board area. The LPC47N227 is software and register compatible with SMSC’s proprietary 82077AA core.

The true CMOS 765B core provides 100% compatibility with IBM PC/XT and PC/AT architectures and provides data overflow and underflow protection. The SMSC advanced digital data separator incorporates SMSC’s patented data

SMSC DB LPC47N227

PRODUCT PREVIEW
100 Pin Super I/O with LPC Interface for Notebook Applications
separator technology allowing for ease of testing and use. The LPC47N227 supports both 1Mbps and 2Mbps data rates and vertical recording operation at 1Mbps Data Rate.

The LPC47N227 also features a full 16-bit internally decoded address bus, a Serial IRQ interface with PCI nCLKRUN support, relocatable configuration ports and three DMA channel options. Both on-chip UARTs are compatible with the NS16C550. One UART includes additional support for a Serial Infrared Interface that complies with IrDA v1.2 Fast IR , HPSIR, and ASKIR formats used by Sharp and other PDAs , as well as Consumer IR.

The parallel port is compatible with IBM PC/AT architectures, as well as IEEE 1284 EPP and ECP. The parallel port ChiProtect circuitry prevents damage caused by an attached powered printer when the LPC47N227 is not powered.

The LPC47N227 incorporates sophisticated power control circuitry PCC . The PCC supports multiple low power down modes. The LPC47N227 also features Software Configurable Logic SCL for ease of use. SCL allows programmable system configuration of key functions such as the FDC, parallel port, and UARTs.

The LPC47N227 supports the ISA Plug-and-Play Standard Version 1.0a and provides the recommended functionaity to support Windows ‘95/’98 and PC99. The I/O Address, DMA Channel and Hardware IRQ of each device in the LPC47N227 may be reprogrammed through the internal configuration registers. There are 192 I/O address location options, a Serialized IRQ interface, and three DMA channels.
ORDERING INFORMATION

Order Numbers:

LPC47N227-MT for 100 Pin TQN, Lead-free RoHS Compliant Package LPC47N227-MV for 100 Pin STQN, Lead-free RoHS Compliant Package
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 631 435-6000, FAX 631 273-3123

Copyright 2007 SMSC or its subsidiaries. All rights reserved.

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order the "Terms of Sale Agreement" . The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at SMSC is a registered trademark of Standard Microsystems Corporation “SMSC” . Product names and company names are the trademarks of their respective holders.

PRODUCT PREVIEW

SMSC DB LPC47N227
100 Pin Super I/O with LPC Interface for Notebook Applications

BLOCK DIAGRAM
nIO_SMI* nIO_PME SMI PME WDT

CONTROL, ADDRESS, DATA

SER_IRQ

PCI_CLK

LAD0 LAD1 LAD2 LAD3 nLFRAME nLDRQ nPCI_RESET
nLPCPD
nCLKRUN

SERIAL IRQ

LPC BUS INTERFACE

VTR Vcc Vss

CLOCK GEN

CLOCKI

CONFIGURATION REGISTERS

ACPI BLOCK

SMSC

WDATA

PROPRIETARY WCLOCK DIGITAL
82077

DATA

COMPATIBLE

SEPERATOR

VERTICAL

PRE-

FLOPPY DISK

COMPENSATION

CONTROLLER RCLOCK

CORE

RDATA
nMTR0, nDS0, nDIR, nTRK0, nSTEP, DRVDEN0*, nDSKCHG, nWGATE, HDSEL, nINDEX, DRVDEN1*, nWDATA nWRTPRT,
nRDATA
nWDATA nRDATA

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived LPC47N227-MV Datasheet file may be downloaded here without warranties.

Datasheet ID: LPC47N227-MV 648128