MT18HTF25672FY-53EA5D3

MT18HTF25672FY-53EA5D3 Datasheet

MT18HTF12872F 1GB MT18HTF25672F 2GB

Part	Datasheet
MT18HTF25672FY-53EA5D3	MT18HTF25672FY-53EA5D3 (pdf)

Related Parts	Information
MT18HTF12872FY-53ED5E3	MT18HTF12872FY-53ED5E3
MT18HTF12872FY-53EB5E3	MT18HTF12872FY-53EB5E3
MT18HTF25672FY-667A5E3	MT18HTF25672FY-667A5E3
MT18HTF25672FY-53EA5E3	MT18HTF25672FY-53EA5E3
MT18HTF12872FY-667B5E3	MT18HTF12872FY-667B5E3
MT18HTF12872FY-667B5D3	MT18HTF12872FY-667B5D3
MT18HTF25672FY-667A5D3	MT18HTF25672FY-667A5D3
MT18HTF12872FY-667D5E3	MT18HTF12872FY-667D5E3
MT18HTF12872FY-53EB5D3	MT18HTF12872FY-53EB5D3

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1GB, 2GB x72, SR 240-Pin DDR2 SDRAM FBDIMM Features DDR2 SDRAM FBDIMM MT18HTF12872F 1GB MT18HTF25672F 2GB For the latest data sheets and technical notes, refer to Micron’s Web site: • 240-pin, DDR2 fully buffered dual in-line memory module FBDIMM • Fast data transfer rates PC2-4200, PC2-5300, and PC2-6400 • 1GB 128 Meg x 72 , 2GB 256 Meg x 72 • Gb/s, Gb/s, and Gb/s link transfer rates • High-speed, differential, point-to-point link between host controller and advanced memory buffer AMB • Fault-tolerant can work around a bad bit lane in each direction • High-density scaling with up to eight FBDIMMs per channel • SMBus interface to AMB for configuration register access • In-band and out-of-band command access • Deterministic protocol Enables memory controller optimization of DRAM accesses for maximum performance Delivers precise control and repeatable memory behavior • Automatic DDR2 SDRAM bus and channel calibration • Transmitter de-emphasis to reduce ISI • MBIST and IBIST test functions • Transparent mode for DRAM test support • VDD = VDDQ = +1.8V for DDR2 SDRAM • VREF = 0.9V SDRAM command and address termination • VCC = 1.5V for AMB • VDDSPD = +3.0V to +3.6V for AMB and EEPROM • Serial presence-detect SPD with EEPROM • Gold edge contacts • Single rank Figure 1 240-Pin FBDIMM MO-256 R/C PCB height 30.35mm 1.19in Options • Package 240-pin DIMM Pb-free • Frequency/CAS latency 2.5ns CL = 5 DDR2-800 3.0ns CL = 5 DDR2-667 3.75ns CL = 4 DDR2-533 1 Marking -80E -667 -53E Notes Not recommended for new designs. Table 1 Key Timing Parameters Speed Grade -80E -667 -53E Industry Nomenclature PC2-6400 PC2-5300 PC2-4200 Data Rate MT/s CL = 5 CL = 4 CL = 3 tRCD ns tRP ns tRC ns Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved. Products and specifications discussed herein are subject to change by Micron without notice. 1GB, 2GB x72, SR 240-Pin DDR2 SDRAM FBDIMM Features Table 2 Addressing Parameter Refresh count Device bank address Device page size per bank Device configuration Row address Column address Module rank address 8K 4 BA0, BA1 1KB 512Mb 128 Meg x 4 16K 2K A11 1 S0# 1KB 1Gb 256 Meg x 4

PDF Datasheet Preview

1GB, 2GB x72, SR 240-Pin DDR2 SDRAM FBDIMM Features

DDR2 SDRAM FBDIMM

MT18HTF12872F 1GB MT18HTF25672F 2GB

For the latest data sheets and technical notes, refer to Micron’s Web site:
• 240-pin, DDR2 fully buffered dual in-line memory module FBDIMM
• Fast data transfer rates PC2-4200, PC2-5300, and PC2-6400
• 1GB 128 Meg x 72 , 2GB 256 Meg x 72
• Gb/s, Gb/s, and Gb/s link transfer rates
• High-speed, differential, point-to-point link
between host controller and advanced memory buffer AMB
• Fault-tolerant can work around a bad bit lane in each direction
• High-density scaling with up to eight FBDIMMs per channel
• SMBus interface to AMB for configuration register access
• In-band and out-of-band command access
• Deterministic protocol Enables memory controller optimization of DRAM
accesses for maximum performance Delivers precise control and repeatable memory
behavior
• Automatic DDR2 SDRAM bus and channel
calibration
• Transmitter de-emphasis to reduce ISI
• MBIST and IBIST test functions
• Transparent mode for DRAM test support
• VDD = VDDQ = +1.8V for DDR2 SDRAM
• VREF = 0.9V SDRAM command and address
termination
• VCC = 1.5V for AMB
• VDDSPD = +3.0V to +3.6V for AMB and EEPROM
• Serial presence-detect SPD with EEPROM
• Gold edge contacts
• Single rank

Figure 1 240-Pin FBDIMM MO-256 R/C

PCB height 30.35mm 1.19in

Options
• Package 240-pin DIMM Pb-free
• Frequency/CAS latency 2.5ns CL = 5 DDR2-800 3.0ns CL = 5 DDR2-667 3.75ns CL = 4 DDR2-533 1

Marking
-80E -667 -53E

Notes Not recommended for new designs.

Table 1 Key Timing Parameters

Speed Grade
-80E -667 -53E

Industry Nomenclature PC2-6400 PC2-5300 PC2-4200

Data Rate MT/s

CL = 5

CL = 4

CL = 3
tRCD ns
tRP ns
tRC ns

Micron Technology, Inc., reserves the right to change products or specifications without notice. 2005 Micron Technology, Inc. All rights reserved.

Products and specifications discussed herein are subject to change by Micron without notice.
1GB, 2GB x72, SR 240-Pin DDR2 SDRAM FBDIMM Features

Table 2 Addressing

Parameter Refresh count Device bank address Device page size per bank Device configuration Row address Column address Module rank address
8K 4 BA0, BA1
1KB 512Mb 128 Meg x 4
16K 2K A11
1 S0#
1KB 1Gb 256 Meg x 4

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Datasheet ID: MT18HTF25672FY-53EA5D3 648327