LAN91C100FD-SS

LAN91C100FD-SS Datasheet

LAN91C100FD REV. D

Part	Datasheet
LAN91C100FD-SS	LAN91C100FD-SS (pdf)

PDF Datasheet Preview
Product Features Dual Speed CSMA/CD Engine 10 Mbps and 100 Mbps Compliant with IEEE 100BASE-T Specification Supports 100BASE-TX, 100BASE-T4, and 10BASE-T Physical Interfaces 32 Bit Wide Data Path into Packet Buffer Memory Support for 32 and 16 Bit Buses Support for 32, 16 and 8 Bit CPU Accesses Synchronous, Asynchronous and Burst DMA Interface Mode Options 128 Kbyte External Memory FEAST Fast Ethernet Controller with Full Duplex Capability Datasheet Built-In Transparent Arbitration for Slave Sequential Access Architecture Flat MMU Architecture with Symmetric Transmit and Receive Structures and Queues MII Media Independent Interface Compliant MAC-PHY Interface Running at Nibble Rate MII Management Serial Interface Seven Wire Interface to 10 Mbps ENDEC EEPROM-Based Setup Full Duplex Capability ORDER NUMBER S : LAN91C100-FD for 208-pin QFP package LAN91C100-FD-SS for 208-pin QFP lead-free RoHS compliant package LAN91C100-FD for 208-pin TQFP package LAN91C100-FD-ST for 208-pin TQFP lead-free RoHS compliant package DATASHEET FEAST Fast Ethernet Controller with Full Duplex Capability 80 ARKAY DRIVE, HAUPPAUGE, NY 11788 631 435-6000, FAX 631 273-3123 Copyright 2008 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order the "Terms of Sale Agreement" . The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at SMSC is a registered trademark of Standard Microsystems Corporation “SMSC” . Product names and company names are the trademarks of their respective holders. DATASHEET FEAST Fast Ethernet Controller with Full Duplex Capability Table Of Contents Chapter 1 General Description 5 Chapter 2 Pin 6 Chapter 3 Description of Pin Functions 7 Chapter 4 Functional 15 Description of 15 Clock Generator CSMA/CD 15 DMA Block Arbiter Block MMU Block BIU MAC-PHY Interface Block MII Management Interface Block Serial EEPROM Interface Chapter 5 Data Structures and Registers 19 Packet Format in Buffer Memory 19 Typical Flow of Events for Transmit Auto Release = 41 Typical Flow of Events for Transmit Auto Release = 42 Typical Flow of Events for Receive 43 Memory Partitioning 48 Interrupt Generation 49 Chapter 6 Board Setup Information 52 Chapter 7 Application Considerations 55 Fast Ethernet Slave Adapter 55 VL Local Bus 32 Bit Systems 55 High End ISA or Non-Burst EISA 58 EISA 32 Bit SLAVEEISA 32 Bit 60 Chapter 8 Operational Description 63 Maximum Guaranteed Ratings* 63 DC Electrical 63 Chapter 9 Timing 66 Chapter 10 Package 76 List of Figures Figure - LAN91C100FD Block Diagram Figure - LAN91C100FD System Diagram Figure - LAN91C100FD Internal Bock diagram with Data Figure - Data Packet Format Figure - Interrupt Structure Figure - Interrupt Service Routine Figure - RX INTR Figure - TX Figure - TXEMPTY INTR Assumes Auto release Option Selected Figure - Drive Send and Allocate Routines Figure - Interrupt Generation for Transmit, Receive, MMU Figure - 64 X 16 Serial EEPROM DATASHEET FEAST Fast Ethernet Controller with Full Duplex Capability 111 7 RESET TX FIFOs - This command will reset both TX FIFOs The TX FIFO holding the packet numbers awaiting transmission and the TX Completion FIFO. This command provides a mechanism for canceling packet transmissions, and reordering or bypassing the transmit queue. The RESET TX FIFOs command should only be used when the transmitter is disabled. Unlike the RESET MMU command, the RESET TX FIFOs does not release any memory. Page 31 DATASHEET FEAST Fast Ethernet Controller with Full Duplex Capability Bits N2,N1,N0 bits are ignored by the LAN91C100FD but should be used for command 0 to preserve software compatibility with the LAN91C92 and future devices. They should be zero for all other commands. When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO ports register before issuing the command. MMU commands releasing memory commands 4 and 5 should only be issued if the corresponding packet number has memory allocated to it. COMMAND SEQUENCING A second allocate command 1 should not be issued until the present one has completed. Completion is determined by reading the FAILED bit of the allocation result register or through the allocation interrupt. A second release command commands 4, 5 should not be issued if the previous one is still being processed. The BUSY bit indicates that a release command is in progress. After issuing command 5, the contents of the PNR should not be changed until BUSY goes low. After issuing command 4, command 3 should not be issued until BUSY goes low. BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU is still processing a release command. When clear, MMU has already completed last release command. BUSY and FAILED bits are set upon the trailing edge of command. BANK 2 OFFSET 2 NAME PACKET NUMBER REGISTER TYPE READ/WRITE SYMBOL PNR PACKET NUMBER AT TX AREA PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number stored in this register as the packet number parameter. This register is cleared by a RESET or a RESET MMU Command. OFFSET 3 NAME ALLOCATION RESULT REGISTER TYPE READ ONLY This register is updated upon an ALLOCATE MEMORY MMU command. FAILED ALLOCATED PACKET NUMBER SYMBOL ARR FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only cleared when the pending allocation is satisfied. Defaults high upon reset and reset MMU command. For polling purposes, the ALLOC_INT in the Interrupt Status Register should be used because it is synchronized to the read operation. Sequence: Allocate Command Poll ALLOC_INT bit until set Read Allocation Result Register Page 32 DATASHEET FEAST Fast Ethernet Controller with Full Duplex Capability Note: ALLOCATED PACKET NUMBER - Packet number associated with the last memory allocation request. The value is only valid if the FAILED bit is clear. For software compatibility with future versions, the value read from the ARR after an allocation request is intended to be written into the PNR as is, without masking higher bits provided FAILED = BANK 2 OFFSET 4 NAME FIFO PORTS REGISTER TYPE READ ONLY SYMBOL FIFO This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet numbers to be processed by the interrupt service routines are read from this register. HIGH REMPTY

PDF Datasheet Preview

Product Features

Dual Speed CSMA/CD Engine 10 Mbps and 100 Mbps

Compliant with IEEE 100BASE-T Specification

Supports 100BASE-TX, 100BASE-T4, and 10BASE-T Physical Interfaces
32 Bit Wide Data Path into Packet Buffer Memory

Support for 32 and 16 Bit Buses Support for 32, 16 and 8 Bit CPU Accesses Synchronous, Asynchronous and Burst DMA

Interface Mode Options 128 Kbyte External Memory

FEAST Fast Ethernet Controller with Full Duplex Capability

Datasheet

Built-In Transparent Arbitration for Slave Sequential Access Architecture

Flat MMU Architecture with Symmetric Transmit and Receive Structures and Queues

MII Media Independent Interface Compliant MAC-PHY Interface Running at Nibble Rate

MII Management Serial Interface Seven Wire Interface to 10 Mbps ENDEC EEPROM-Based Setup Full Duplex Capability

ORDER NUMBER S :

LAN91C100-FD for 208-pin QFP package LAN91C100-FD-SS for 208-pin QFP lead-free RoHS compliant package

LAN91C100-FD for 208-pin TQFP package LAN91C100-FD-ST for 208-pin TQFP lead-free RoHS compliant package

DATASHEET

FEAST Fast Ethernet Controller with Full Duplex Capability
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 631 435-6000, FAX 631 273-3123

Copyright 2008 SMSC or its subsidiaries. All rights reserved.

Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order the "Terms of Sale Agreement" . The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC’s website at SMSC is a registered trademark of Standard Microsystems Corporation “SMSC” . Product names and company names are the trademarks of their respective holders.

DATASHEET

FEAST Fast Ethernet Controller with Full Duplex Capability

Table Of Contents

Chapter 1 General Description 5

Chapter 2 Pin 6

Chapter 3 Description of Pin Functions 7

Chapter 4 Functional 15 Description of 15

Clock Generator

CSMA/CD 15

DMA Block Arbiter Block MMU Block BIU MAC-PHY Interface Block MII Management Interface Block Serial EEPROM Interface

Chapter 5 Data Structures and Registers 19 Packet Format in Buffer Memory 19 Typical Flow of Events for Transmit Auto Release = 41 Typical Flow of Events for Transmit Auto Release = 42 Typical Flow of Events for Receive 43 Memory Partitioning 48 Interrupt Generation 49

Chapter 6 Board Setup Information 52

Chapter 7 Application Considerations 55 Fast Ethernet Slave Adapter 55 VL Local Bus 32 Bit Systems 55 High End ISA or Non-Burst EISA 58 EISA 32 Bit SLAVEEISA 32 Bit 60

Chapter 8 Operational Description 63 Maximum Guaranteed Ratings* 63 DC Electrical 63

Chapter 9 Timing 66

Chapter 10 Package 76

List of Figures

Figure - LAN91C100FD Block Diagram Figure - LAN91C100FD System Diagram Figure - LAN91C100FD Internal Bock diagram with Data Figure - Data Packet Format Figure - Interrupt Structure Figure - Interrupt Service Routine Figure - RX INTR Figure - TX Figure - TXEMPTY INTR Assumes Auto release Option Selected Figure - Drive Send and Allocate Routines Figure - Interrupt Generation for Transmit, Receive, MMU Figure - 64 X 16 Serial EEPROM

DATASHEET

FEAST Fast Ethernet Controller with Full Duplex Capability
111 7 RESET TX FIFOs - This command will reset both TX FIFOs The TX FIFO holding the packet numbers awaiting transmission and the TX Completion FIFO. This command provides a mechanism for canceling packet transmissions, and reordering or bypassing the transmit queue. The RESET TX FIFOs command should only be used when the transmitter is disabled. Unlike the RESET MMU command, the RESET TX FIFOs does not release any memory.

Page 31

DATASHEET

FEAST Fast Ethernet Controller with Full Duplex Capability

Bits N2,N1,N0 bits are ignored by the LAN91C100FD but should be used for command 0 to preserve software compatibility with the LAN91C92 and future devices. They should be zero for all other commands.

When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO ports register before issuing the command.

MMU commands releasing memory commands 4 and 5 should only be issued if the corresponding packet number has memory allocated to it.

COMMAND SEQUENCING

A second allocate command 1 should not be issued until the present one has completed. Completion is determined by reading the FAILED bit of the allocation result register or through the allocation interrupt.

A second release command commands 4, 5 should not be issued if the previous one is still being processed. The BUSY bit indicates that a release command is in progress. After issuing command 5, the contents of the PNR should not be changed until BUSY goes low. After issuing command 4, command 3 should not be issued until BUSY goes low.

BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU is still processing a release command. When clear, MMU has already completed last release command. BUSY and FAILED bits are set upon the trailing edge of command.

BANK 2

OFFSET 2

NAME PACKET NUMBER REGISTER

TYPE READ/WRITE

SYMBOL PNR

PACKET NUMBER AT TX AREA

PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible through the TX area. Some MMU commands use the number stored in this register as the packet number parameter. This register is cleared by a RESET or a RESET MMU Command.

OFFSET 3

NAME ALLOCATION RESULT REGISTER

TYPE READ ONLY

This register is updated upon an ALLOCATE MEMORY MMU command.

FAILED

ALLOCATED PACKET NUMBER

SYMBOL ARR

FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only cleared when the pending allocation is satisfied. Defaults high upon reset and reset MMU command. For polling purposes, the ALLOC_INT in the Interrupt Status Register should be used because it is synchronized to the read operation. Sequence:

Allocate Command

Poll ALLOC_INT bit until set

Read Allocation Result Register

Page 32

DATASHEET

FEAST Fast Ethernet Controller with Full Duplex Capability

Note:

ALLOCATED PACKET NUMBER - Packet number associated with the last memory allocation request. The value is only valid if the FAILED bit is clear.

For software compatibility with future versions, the value read from the ARR after an allocation request is intended to be written into the PNR as is, without masking higher bits provided FAILED =

BANK 2 OFFSET 4

NAME FIFO PORTS REGISTER

TYPE READ ONLY

SYMBOL FIFO

This register provides access to the read ports of the Receive FIFO and the Transmit completion FIFO. The packet numbers to be processed by the interrupt service routines are read from this register.

HIGH REMPTY

More datasheets: 61S64-1-060 | 61SS64-2 | 61S128-2-060 | 61S128-2 | 61S75-2-060 | 61S64-2 | 61S100-2-020 | 15801123 | 9107C-05CS08LF | 9107C-05CS08LFT

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived LAN91C100FD-SS Datasheet file may be downloaded here without warranties.

Datasheet ID: LAN91C100FD-SS 648120