LAN89730AMR-A

LAN89730AMR-A Datasheet

LAN89730

Part	Datasheet
LAN89730AMR-A	LAN89730AMR-A (pdf)

PDF Datasheet Preview
LAN89730 High-Speed Inter-Chip HSIC USB to 10/100 Ethernet Controller for Automotive Applications Highlights • Single Chip HSIC USB to 10/100 Ethernet Controller • Integrated 10/100 Ethernet MAC with Full-Duplex Support • Integrated 10/100 Ethernet PHY with HP AutoMDIX Support • Integrated USB Hi-Speed Device Controller • Integrated HSIC Interface1 • Implements Reduced Power Operating Modes Target Applications • Diagnostic Interface for Dealership Service Bay • Fast Software Download Interface e.g., OBD Connector • Gateway Service Interface Dealership, Aftermarket Repair Shop • In-vehicle Engineering Development Interface • Vehicle Manufacturing Test Interface Production Plant Assembly Line • Legislated Inspections Emissions Check, Safety Inspections Key Features • USB Device Controller - Supports HS 480 Mbps mode - Four Endpoints supported - Supports vendor specific commands - Integrated HSIC Interface - Remote wakeup supported • High-Performance 10/100 Ethernet Controller - Fully compliant with IEEE 802.3/802.3u - Integrated Ethernet MAC and PHY - 10BASE-T and 100BASE-TX support - Full- and half-duplex support - Full- and half-duplex flow control - Preamble generation and removal - Automatic 32-bit CRC generation and checking - Automatic payload padding and pad removal - Loop-back modes - TCP/UDP/IP/ICMP checksum offload support - Flexible address filtering modes - One 48-bit perfect address - 64 hash-filtered multicast addresses - Pass all multicast - Promiscuous mode - Inverse filtering - Pass all incoming with status report - Wakeup packet support - Integrated Ethernet PHY - Auto-negotiation - Automatic polarity detection and correction - HP Auto-MDIX support - Link status change wake-up detection - Support for three status LEDs • Power and I/Os - Various low power modes - Supports PCI-like PME wake when USB host dis- abled - 11 GPIOs - Supports bus-powered and self-powered opera- tion - Integrated power-on reset circuit - Single external V I/O supply - Optional internal core regulator • Miscellaneous Features - EEPROM controller - Supports custom operation without EEPROM - IEEE JTAG boundary scan - Requires single 25 MHz crystal • Software - 8/7/XP/Vista driver - driver - Win CE driver - OS driver - EEPROM utility • Packaging - 56-pin VQFN 8 x 8 mm , RoHS-compliant • Environmental - -40°C to +85°C temperature range Compliant to HSIC ECN as of May 2010 2013-2015 Microchip Technology Inc. DS60001348A-page 1 LAN89730 TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at We welcome your feedback. Most Current Data Sheet The EEPROM controller will then load the entire contents of the EEPROM into an internal 512 byte SRAM. The contents of the SRAM are accessed by the CTL USB Control Block as needed i.e., to fill Get Descriptor commands . A detailed explanation of the EEPROM byte ordering with respect to the MAC address is given in Section "MAC Address Low Register ADDRL ". If an 0xA5h is not read from the first address, the EEPROM controller will end initialization. The default values, as specified in Table 4-59, will then be assumed by the associated registers. It is then the responsibility of the host LAN driver software to set the IEEE address by writing to the MAC’s ADDRH and ADDRL registers. The device may not respond to the USB host until the EEPROM loading sequence has completed. Therefore, after reset, the USB PHY is kept in the disconnect state until the EEPROM load has completed. 2013-2015 Microchip Technology Inc. DS60001348A-page 89 LAN89730 EEPROM HOST OPERATIONS After the EEPROM controller has finished reading or attempting to read the EEPROM after a system-level reset, the host is free to perform other EEPROM operations. EEPROM operations are performed using the EEPROM Command E2P_CMD and EEPROM Data E2P_DATA registers. Section "EEPROM Command Register E2P_CMD " provides an explanation of the supported EEPROM operations. If the EEPROM operation is the “write location” WRITE or “write all” WRAL commands, the host must first write the desired data into the E2P_DATA register. The host must then issue the WRITE or WRAL command using the E2P_CMD register by setting the EPC_CMD field appropriately. If the operation is a WRITE, the EPC_ADDR field in E2P_CMD must also be set to the desired location. The command is executed when the host sets the EPC_BSY bit high. The completion of the operation is indicated when the EPC_BSY bit is cleared. If the EEPROM operation is the “read location” READ operation, the host must issue the READ command using the E2P_CMD register with the EPC_ADDR set to the desired location. The command is executed when the host sets the EPC_BSY bit high. The completion of the operation is indicated when the EPC_BSY bit is cleared, at which time the data from the EEPROM may be read from the E2P_DATA register. Other EEPROM operations are performed by writing the appropriate command to the E2P_CMD register. The command is executed when the host sets the EPC_BSY bit high. The completion of the operation is indicated when the EPC_BSY bit is cleared. In all cases, the host must wait for EPC_BSY to clear before modifying the E2P_CMD register. Note The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM, the host must first issue the EWEN command. If an operation is attempted, and an EEPROM device does not respond within 30 ms, the device will time-out, and the EPC time-out bit EPC_TO in the E2P_CMD register will be set. Figure 4-20 illustrates the host accesses required to perform an EEPROM Read or Write operation. FIGURE 4-20: EEPROM ACCESS FLOW DIAGRAM EEPROM Write EEPROM Read Idle Idle Write Data Register Write Command Register Busy Bit = 0 Read Command Register Write Command Register Read Command Register Busy Bit = 0 Read Data Register DS60001348A-page 90 2013-2015 Microchip Technology Inc. LAN89730 Supported EEPROM Operations The EEPROM controller supports the following EEPROM operations under host control via the E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A description and functional timing diagram is provided below for each operation. Refer to the E2P_CMD register description in Section "EEPROM Command Register E2P_CMD " for E2P_CMD field settings for each command. ERASE Location If erase/write operations are enabled in the EEPROM, this command will erase the location selected by the EPC Address field EPC_ADDR . The EPC_TO bit is set if the EEPROM does not respond within 30 ms. FIGURE 4-21: EEPROM ERASE CYCLE tCSL EECS EECLK EEDIO OUTPUT EEDIO INPUT ERASE CYCLE ERAL Erase All If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM. The EPC_TO bit is set if the EEPROM does not respond within 30 ms. Table 6-5 illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the Ethernet physical address. TABLE 6-5 ADDRL, ADDRH BYTE ORDERING ADDRL, ADDRH Order of Reception on Ethernet ADDRL[7:0] ADDRL[15:8] ADDRL[23:16] ADDRL[31:24] ADDRH[7:0] ADDRH[15:8] As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and ADDRH registers would be programmed as shown in Figure FIGURE 6-1: EXAMPLE ADDRL, ADDRH ADDRESS ORDERING 31 24 23 16 15 8 7 0 0xBC 0x9A ADDRH 31 24 23 16 15 8 7 0x78 0x56 0x34 0x12 ADDRL DS60001348A-page 166 2013-2015 Microchip Technology Inc. LAN89730 MULTICAST HASH TABLE HIGH REGISTER HASHH Address: 10Ch Size: 32 bits The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the hash table. The most significant bit determines the register to be used high/low , while the other five bits determine the bit within the register. A value of selects bit 0 of the Multicast Hash Table Low register and a value of selects the bit 31 of the Multicast Hash Table High register. If the corresponding bit is ‘1’, then the multicast frame is accepted. Otherwise, it is rejected. If the “Pass All Multicast” MCPAS bit is set ‘1’ , then all multicast frames are accepted regardless of the multicast hash values. The Multicast Hash Table High register contains the higher 32 bits of the hash table and the Multicast Hash Table Low register contains the lower 32 bits of the hash table. Bits 31:0 Upper 32 bits of the 64-bit hash table Type R/W Default 0000_0000h 2013-2015 Microchip Technology Inc. DS60001348A-page 167 LAN89730 MULTICAST HASH TABLE LOW REGISTER HASHL Address: 110h Size: 32 bits This register defines the lower 32-bits of the Multicast Hash Table. Refer to Section "Multicast Hash Table High Register HASHH " for further details. Bits 31:0 Lower 32 bits of the 64-bit hash table Type R/W Default 0000_0000h DS60001348A-page 168 2013-2015 Microchip Technology Inc. LAN89730 MII ACCESS REGISTER MII_ACCESS Address: 114h groups, Microchip consultant program member listing • Business of Microchip Product selector and ordering guides, latest Microchip press releases, listing of semi- nars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels • Distributor or Representative • Local Sales Office • Field Application Engineer FAE • Technical Support Customers should contact their distributor, representative or field application engineer FAE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: 2013-2015 Microchip Technology Inc. DS60001348A-page 215 LAN89730 PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. - - [X] 1 Device Temperature Package Tape and Pattern Automotive Range Reel Option Option Device: LAN89730 Temperature Range: = -40C to +85C automotive, industrial Package: = VQFN 56-pin Examples: a LAN89730AM-A -40C to +85C, 56-pin VQFN, Tray, A, V03 b LAN89730AMR-A -40C to +85C, 56-pin VQFN, Tape & Reel, A, V03 Tape and Reel Option: Pattern: Automotive Option: Blank = Standard packaging tray = Tape and Reel 1 = Product version Blank = Commercial V03 = Automotive Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Reel size is DS60001348A-page 216 2013-2015 Microchip Technology Inc. Note the following details of the code protection feature on Microchip devices • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. 2013-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN 978-1-63277-400-2 QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV == ISO/TS 16949 == 2013-2015 Microchip Technology Inc. Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its MCUs and DSCs, code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS60001348A-page 217 AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel 480-792-7200 Fax 480-792-7277 Technical Support Web Address: Atlanta Duluth, GA Tel 678-957-9614 Fax 678-957-1455 Austin, TX Tel 512-257-3370 Boston Westborough, MA Tel 774-760-0087 Fax 774-760-0088 Chicago Itasca, IL Tel 630-285-0071 Fax 630-285-0075 Cleveland Independence, OH Tel 216-447-0464 Fax 216-447-0643 Dallas Addison, TX Tel 972-818-7423 Fax 972-818-2924 Detroit Novi, MI Tel 248-848-4000 Houston, TX Tel 281-894-5983 Indianapolis Noblesville, IN Tel 317-773-8323 Fax 317-773-5453 Los Angeles Mission Viejo, CA Tel 949-462-9523 Fax 949-462-9608 New York, NY Tel 631-435-6000 San Jose, CA Tel 408-735-9110 Canada - Toronto Tel 905-673-0699 Fax 905-673-6509 Worldwide Sales and Service ASIA/PACIFIC Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel 852-2943-5100 Fax 852-2401-3431 Australia - Sydney Tel 61-2-9868-6733 Fax 61-2-9868-6755 China - Beijing Tel 86-10-8569-7000 Fax 86-10-8528-2104 China - Chengdu Tel 86-28-8665-5511 Fax 86-28-8665-7889 China - Chongqing Tel 86-23-8980-9588 Fax 86-23-8980-9500 China - Dongguan Tel 86-769-8702-9880 China - Hangzhou Tel 86-571-8792-8115 Fax 86-571-8792-8116

PDF Datasheet Preview

LAN89730

High-Speed Inter-Chip HSIC USB to 10/100 Ethernet Controller for Automotive Applications

Highlights
• Single Chip HSIC USB to 10/100 Ethernet Controller
• Integrated 10/100 Ethernet MAC with Full-Duplex Support
• Integrated 10/100 Ethernet PHY with HP AutoMDIX Support
• Integrated USB Hi-Speed Device Controller
• Integrated HSIC Interface1
• Implements Reduced Power Operating Modes

Target Applications
• Diagnostic Interface for Dealership Service Bay
• Fast Software Download Interface e.g., OBD Connector
• Gateway Service Interface Dealership, Aftermarket Repair Shop
• In-vehicle Engineering Development Interface
• Vehicle Manufacturing Test Interface Production Plant Assembly Line
• Legislated Inspections Emissions Check, Safety Inspections

Key Features
• USB Device Controller
- Supports HS 480 Mbps mode - Four Endpoints supported - Supports vendor specific commands - Integrated HSIC Interface - Remote wakeup supported
• High-Performance 10/100 Ethernet Controller
- Fully compliant with IEEE 802.3/802.3u - Integrated Ethernet MAC and PHY - 10BASE-T and 100BASE-TX support - Full- and half-duplex support - Full- and half-duplex flow control - Preamble generation and removal - Automatic 32-bit CRC generation and checking - Automatic payload padding and pad removal - Loop-back modes - TCP/UDP/IP/ICMP checksum offload support - Flexible address filtering modes
- One 48-bit perfect address
- 64 hash-filtered multicast addresses - Pass all multicast - Promiscuous mode - Inverse filtering - Pass all incoming with status report - Wakeup packet support - Integrated Ethernet PHY - Auto-negotiation - Automatic polarity detection and correction - HP Auto-MDIX support - Link status change wake-up detection - Support for three status LEDs
• Power and I/Os
- Various low power modes - Supports PCI-like PME wake when USB host dis-
abled - 11 GPIOs - Supports bus-powered and self-powered opera-
tion - Integrated power-on reset circuit - Single external V I/O supply
- Optional internal core regulator
• Miscellaneous Features
- EEPROM controller - Supports custom operation without EEPROM - IEEE JTAG boundary scan - Requires single 25 MHz crystal
• Software - 8/7/XP/Vista driver - driver - Win CE driver - OS driver - EEPROM utility
• Packaging
- 56-pin VQFN 8 x 8 mm , RoHS-compliant
• Environmental
- -40°C to +85°C temperature range

Compliant to HSIC ECN as of May 2010
2013-2015 Microchip Technology Inc.

DS60001348A-page 1

LAN89730

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at We welcome your feedback.

Most Current Data Sheet
The EEPROM controller will then load the entire contents of the EEPROM into an internal 512 byte SRAM. The contents of the SRAM are accessed by the CTL USB Control Block as needed i.e., to fill Get Descriptor commands . A detailed explanation of the EEPROM byte ordering with respect to the MAC address is given in Section "MAC Address Low Register ADDRL ". If an 0xA5h is not read from the first address, the EEPROM controller will end initialization. The default values, as specified in Table 4-59, will then be assumed by the associated registers. It is then the responsibility of the host LAN driver software to set the IEEE address by writing to the MAC’s ADDRH and ADDRL registers. The device may not respond to the USB host until the EEPROM loading sequence has completed. Therefore, after reset, the USB PHY is kept in the disconnect state until the EEPROM load has completed.
2013-2015 Microchip Technology Inc.

DS60001348A-page 89

LAN89730

EEPROM HOST OPERATIONS

After the EEPROM controller has finished reading or attempting to read the EEPROM after a system-level reset, the host is free to perform other EEPROM operations. EEPROM operations are performed using the EEPROM Command E2P_CMD and EEPROM Data E2P_DATA registers. Section "EEPROM Command Register E2P_CMD " provides an explanation of the supported EEPROM operations.

If the EEPROM operation is the “write location” WRITE or “write all” WRAL commands, the host must first write the desired data into the E2P_DATA register. The host must then issue the WRITE or WRAL command using the E2P_CMD register by setting the EPC_CMD field appropriately. If the operation is a WRITE, the EPC_ADDR field in E2P_CMD must also be set to the desired location. The command is executed when the host sets the EPC_BSY bit high. The completion of the operation is indicated when the EPC_BSY bit is cleared.

If the EEPROM operation is the “read location” READ operation, the host must issue the READ command using the E2P_CMD register with the EPC_ADDR set to the desired location. The command is executed when the host sets the EPC_BSY bit high. The completion of the operation is indicated when the EPC_BSY bit is cleared, at which time the data from the EEPROM may be read from the E2P_DATA register.

Other EEPROM operations are performed by writing the appropriate command to the E2P_CMD register. The command is executed when the host sets the EPC_BSY bit high. The completion of the operation is indicated when the EPC_BSY bit is cleared. In all cases, the host must wait for EPC_BSY to clear before modifying the E2P_CMD register.

Note The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM, the host must first issue the EWEN command.

If an operation is attempted, and an EEPROM device does not respond within 30 ms, the device will time-out, and the EPC time-out bit EPC_TO in the E2P_CMD register will be set.

Figure 4-20 illustrates the host accesses required to perform an EEPROM Read or Write operation.

FIGURE 4-20:

EEPROM ACCESS FLOW DIAGRAM

EEPROM Write

EEPROM Read

Idle

Idle

Write Data Register

Write Command Register

Busy Bit = 0

Read Command Register

Write Command Register

Read Command Register

Busy Bit = 0

Read Data Register

DS60001348A-page 90
2013-2015 Microchip Technology Inc.

LAN89730

Supported EEPROM Operations

The EEPROM controller supports the following EEPROM operations under host control via the E2P_CMD register. The operations are commonly supported by “93C46” EEPROM devices. A description and functional timing diagram is provided below for each operation. Refer to the E2P_CMD register description in Section "EEPROM Command Register E2P_CMD " for E2P_CMD field settings for each command.

ERASE Location If erase/write operations are enabled in the EEPROM, this command will erase the location selected by the EPC Address field EPC_ADDR . The EPC_TO bit is set if the EEPROM does not respond within 30 ms.

FIGURE 4-21:

EEPROM ERASE CYCLE
tCSL

EECS

EECLK

EEDIO OUTPUT

EEDIO INPUT

ERASE CYCLE

ERAL Erase All If erase/write operations are enabled in the EEPROM, this command will initiate a bulk erase of the entire EEPROM. The EPC_TO bit is set if the EEPROM does not respond within 30 ms.
Table 6-5 illustrates the byte ordering of the ADDRL and ADDRH registers with respect to the reception of the Ethernet physical address.
TABLE 6-5 ADDRL, ADDRH BYTE ORDERING

ADDRL, ADDRH

Order of Reception on Ethernet

ADDRL[7:0]

ADDRL[15:8]

ADDRL[23:16]

ADDRL[31:24]

ADDRH[7:0]

ADDRH[15:8]

As an example, if the desired Ethernet physical address is 12-34-56-78-9A-BC, the ADDRL and ADDRH registers would be programmed as shown in Figure

FIGURE 6-1:
EXAMPLE ADDRL, ADDRH ADDRESS ORDERING
31 24 23 16 15 8 7 0
0xBC 0x9A

ADDRH
31 24 23 16 15 8 7
0x78 0x56 0x34 0x12

ADDRL

DS60001348A-page 166
2013-2015 Microchip Technology Inc.

LAN89730

MULTICAST HASH TABLE HIGH REGISTER HASHH

Address:
10Ch

Size:
32 bits

The 64-bit Multicast table is used for group address filtering. For hash filtering, the contents of the destination address in the incoming frame is used to index the contents of the hash table. The most significant bit determines the register to be used high/low , while the other five bits determine the bit within the register. A value of selects bit 0 of the Multicast Hash Table Low register and a value of selects the bit 31 of the Multicast Hash Table High register.

If the corresponding bit is ‘1’, then the multicast frame is accepted. Otherwise, it is rejected. If the “Pass All Multicast” MCPAS bit is set ‘1’ , then all multicast frames are accepted regardless of the multicast hash values.

The Multicast Hash Table High register contains the higher 32 bits of the hash table and the Multicast Hash Table Low register contains the lower 32 bits of the hash table.

Bits
31:0 Upper 32 bits of the 64-bit hash table

Type R/W

Default 0000_0000h
2013-2015 Microchip Technology Inc.

DS60001348A-page 167

LAN89730

MULTICAST HASH TABLE LOW REGISTER HASHL

Address:
110h

Size:
32 bits

This register defines the lower 32-bits of the Multicast Hash Table. Refer to Section "Multicast Hash Table High Register HASHH " for further details.

Bits
31:0 Lower 32 bits of the 64-bit hash table

Type R/W

Default 0000_0000h

DS60001348A-page 168
2013-2015 Microchip Technology Inc.

LAN89730

MII ACCESS REGISTER MII_ACCESS

Address:
114h
groups, Microchip consultant program member listing
• Business of Microchip Product selector and ordering guides, latest Microchip press releases, listing of semi-
nars and events, listings of Microchip sales offices, distributors and factory representatives

CUSTOMER CHANGE NOTIFICATION SERVICE

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels
• Distributor or Representative
• Local Sales Office
• Field Application Engineer FAE
• Technical Support Customers should contact their distributor, representative or field application engineer FAE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at:
2013-2015 Microchip Technology Inc.

DS60001348A-page 215

LAN89730

PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
- - [X] 1

Device Temperature Package Tape and Pattern Automotive

Range

Reel Option

Option

Device:

LAN89730

Temperature Range:
= -40C to +85C automotive, industrial

Package:
= VQFN 56-pin

Examples:
a LAN89730AM-A -40C to +85C, 56-pin VQFN, Tray, A, V03
b LAN89730AMR-A -40C to +85C, 56-pin VQFN, Tape & Reel, A, V03

Tape and Reel Option:

Pattern:

Automotive Option:

Blank = Standard packaging tray
= Tape and Reel 1
= Product version

Blank = Commercial V03 = Automotive

Note 1:
Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. Reel size is

DS60001348A-page 216
2013-2015 Microchip Technology Inc.

Note the following details of the code protection feature on Microchip devices
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer’s risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated.

Trademarks The Microchip name and logo, the Microchip logo, dsPIC, FlashFlex, flexPWR, JukeBlox, KEELOQ, KEELOQ logo, Kleer, LANCheck, MediaLB, MOST, MOST logo, MPLAB, OptoLyzer, PIC, PICSTART, PIC32 logo, RightTouch, SpyNIC, SST, SST Logo, SuperFlash and UNI/O are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. The Embedded Control Solutions Company and mTouch are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, BodyCom, chipKIT, chipKIT logo, CodeGuard, dsPICDEM, dsPICDEM.net, ECAN, In-Circuit Serial Programming, ICSP, Inter-Chip Connectivity, KleerNet, KleerNet logo, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, RightTouch logo, REAL ICE, SQI, Serial Quad I/O, Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. Silicon Storage Technology is a registered trademark of Microchip Technology Inc. in other countries. GestIC is a registered trademarks of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. 2013-2015, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. ISBN 978-1-63277-400-2

QUALITY MANAGEMENT SYSTEM CERTIFIED BY DNV
== ISO/TS 16949 ==
2013-2015 Microchip Technology Inc.

Microchip received ISO/TS-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona Gresham, Oregon and design centers in California and India. The Company’s quality system processes and procedures are for its MCUs and DSCs, code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

DS60001348A-page 217

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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived LAN89730AMR-A Datasheet file may be downloaded here without warranties.

Datasheet ID: LAN89730AMR-A 648119