DSPIC30F6012AT-20I/PT

DSPIC30F6012AT-20I/PT Datasheet

dsPIC30F6011A/6012A/6013A/6014A Data Sheet

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DSPIC30F6012AT-20I/PT	DSPIC30F6012AT-20I/PT (pdf)

Related Parts	Information
DSPIC30F6012A-20I/PT	DSPIC30F6012A-20I/PT
DSPIC30F6012AT-20E/PT	DSPIC30F6012AT-20E/PT
DSPIC30F6013AT-30I/PF	DSPIC30F6013AT-30I/PF
DSPIC30F6012AT-20E/PF	DSPIC30F6012AT-20E/PF

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dsPIC30F6011A/6012A/6013A/6014A Data Sheet High-Performance Digital Signal Controllers 2005 Microchip Technology Inc. DS70143B Note the following details of the code protection feature on Microchip devices • Microchip products meet the specification contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. • There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. • Microchip is willing to work with the customer who is concerned about the integrity of their code. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.” Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. 2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October The Company’s quality system processes and procedures are for its 8-bit MCUs, code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS70143B-page ii 2005 Microchip Technology Inc. dsPIC30F6011A/6012A/6013A/6014A dsPIC30F6011A/6012A/6013A/6014A High-Performance Digital Signal Controllers Note This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual DS70046 . For more information on the device instruction set and programming, refer to the dsPIC30F Programmer’s Reference Manual DS70030 . High-Performance Modified RISC CPU: • Modified Harvard architecture • C compiler optimized instruction set architecture • Flexible addressing modes • 84 base instructions • 24-bit wide instructions, 16-bit wide data path • Up to 144 Kbytes on-chip Flash program space • Up to 48K instruction words • Up to 8 Kbytes of on-chip data RAM • Up to 4 Kbytes of nonvolatile data EEPROM • 16 x 16-bit working register array • Up to 30 MIPs operation: - DC to 40 MHz external clock input - 4 MHz-10 MHz oscillator input with PLL active 4x, 8x, 16x • Up to 41 interrupt sources: - 8 user selectable priority levels - 5 external interrupt sources - 4 processor traps DSP Features: • Dual data fetch • Modulo and Bit-Reversed modes • Two 40-bit wide accumulators with optional saturation logic • 17-bit x 17-bit single-cycle hardware fractional/ integer multiplier • All DSP instructions are single cycle - Multiply-Accumulate MAC operation • Single-cycle ±16 shift Peripheral Features: • High-current sink/source I/O pins 25 mA/25 mA • Five 16-bit timers/counters optionally pair up 16-bit timers into 32-bit timer modules • 16-bit Capture input functions • 16-bit Compare/PWM output functions • Data Converter Interface DCI supports common audio Codec protocols, including I2S and AC’97 • 3-wire SPI modules supports 4 Frame modes • I2C module supports Multi-Master/Slave mode and 7-bit/10-bit addressing • Two addressable UART modules with FIFO buffers • Two CAN bus modules compliant with CAN 2.0B The X AGU also supports bit-reversed addressing on destination effective addresses to greatly simplify input or output data reordering for radix-2 FFT algorithms. Refer to Section “Address Generator Units” for details on modulo and bit-reversed addressing. The core supports Inherent no operand , Relative, Literal, Memory Direct, Register Direct, Register Indirect, Register Offset and Literal Offset Addressing modes. Instructions are associated with predefined Addressing modes, depending upon their functional requirements. For most instructions, the core is capable of executing a data or program data memory read, a working register data read, a data memory write and a program instruction memory read per instruction cycle. As a result, 3-operand instructions are supported, allowing C = A+B operations to be executed in a single cycle. A DSP engine has been included to significantly enhance the core arithmetic capability and throughput. It features a high-speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. Data in the accumulator or any working register can be shifted up to 16 bits right, or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC class of instructions can concurrently fetch two data operands from memory while multiplying two W registers. To enable this concurrent fetching of data operands, the data space has been split for these instructions and linear for all others. This has been achieved in a transparent and flexible manner, by dedicating certain working registers to each address space for the MAC class of instructions. 2005 Microchip Technology Inc. DS70143B-page 15 dsPIC30F6011A/6012A/6013A/6014A The core does not support a multi-stage instruction pipeline. However, a single stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions. The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors. The exceptions consist of up to 8 traps of which 4 are reserved and 54 interrupts. Each interrupt is prioritized based on a user assigned priority between 1 and 7 1 being the lowest priority and 7 being the highest , in conjunction with a predetermined ‘natural order’. Traps have fixed priorities ranging from 8 to Programmer’s Model The programmer’s model is shown in Figure 2-1 and consists of 16 x 16-bit working registers W0 through W15 , 2 x 40-bit accumulators AccA and AccB , STATUS register SR , Data Table Page register TBLPAG , Program Space Visibility Page register PSVPAG , DO and REPEAT registers DOSTART, DOEND, DCOUNT and RCOUNT and Program Counter PC . The working registers can act as data, address or offset registers. All registers are memory mapped. W0 acts as the W register for file register addressing. Some of these registers have a shadow register associated with each of them, as shown in Figure The shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon the occurrence of an event. None of the shadow registers are accessible directly. The following rules apply for transfer of registers into and out of shadows. • PUSH.S and POP.S W0, W1, W2, W3, SR DC, N, OV, Z and C bits only are transferred. • DO instruction DOSTART, DOEND, DCOUNT shadows are pushed on loop start, and popped on loop end. When a byte operation is performed on a working register, only the Least Significant Byte LSB of the target register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes can be manipulated through byte wide data memory space accesses. SOFTWARE STACK POINTER/ FRAME POINTER The DSC devices contain a software stack. W15 is the dedicated software Stack Pointer SP , and will be automatically modified by exception processing and subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies the reading, writing and manipulation of the Stack Pointer e.g., creating stack frames . Note In order to protect against misaligned stack accesses, W15<0> is always clear. W15 is initialized to 0x0800 during a Reset. The user may reprogram the SP during initialization to any location within data space. W14 has been dedicated as a Stack Frame Pointer as defined by the LNK and ULNK instructions. However, W14 can be referenced by any instruction in the same manner as all other W registers. STATUS REGISTER The dsPIC DSC core has a 16-bit STATUS register SR , the LSB of which is referred to as the SR Low byte SRL and the Most Significant Byte MSB as the SR High byte SRH . See Figure 2-1 for SR layout. SRL contains all the MCU ALU operation status flags including the Z bit , as well as the CPU Interrupt Priority Level status bits, IPL<2:0> and the Repeat Active status bit, RA. During exception processing, SRL is concatenated with the MSB of the PC to form a complete word value which is then stacked. The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit DA and the Digit Carry DC status bit. PROGRAM COUNTER The Program Counter is 23-bits wide bit 0 is always clear. Therefore, the PC can address up to 4M instruction words. DS70143B-page 16 2005 Microchip Technology Inc. dsPIC30F6011A/6012A/6013A/6014A FIGURE 2-1: PROGRAMMER’S MODEL DSP Operand Registers DSP Address Registers W0/WREG W3 W4 W6 W7 W12/DSP Offset W13/DSP Write Back W14/Frame Pointer W15/Stack Pointer PUSH.S Shadow DO Shadow Legend Bit-reversed addressing is intended to simplify data reordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only. BIT-REVERSED ADDRESSING IMPLEMENTATION Bit-reversed addressing is enabled when: BWM W register selection in the MODCON register is any value other than ‘15’ the stack cannot be accessed using bit-reversed addressing and the BREN bit is set in the XBREV register and the Addressing mode used is Register Indirect with Pre-Increment or Post-Increment. If the length of a bit-reversed buffer is M = 2N bytes, then the last ‘N’ bits of the data buffer start address must be zeros. XB<14:0> is the bit-reversed address modifier or ‘pivot point’, which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size. Note: All bit-reversed EA calculations assume word sized data LSb of every EA is always clear . The XB value is scaled accordingly to generate compatible byte addresses. When enabled, bit-reversed addressing will only be executed for register indirect with pre-increment or post-increment addressing and word sized data writes. It will not function for any other Addressing mode or for byte sized data, and normal addresses will be generated instead. When bit-reversed addressing is active, the W address pointer will always be added to the address modifier XB and the offset associated with the Register Indirect Addressing mode will be ignored. In addition, as word sized data is a requirement, the LSb of the EA is ignored and always clear . Note: Modulo addressing and bit-reversed addressing should not be enabled together. In the event that the user attempts to do this, bit-reversed addressing will assume priority when active for the X WAGU, and X WAGU modulo addressing will be disabled. However, modulo addressing will continue to function in the X RAGU. If bit-reversed addressing has already been enabled by setting the BREN XBREV<15> bit, then a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer. DS70143B-page 42 2005 Microchip Technology Inc. dsPIC30F6011A/6012A/6013A/6014A FIGURE 4-2: BIT-REVERSED ADDRESS EXAMPLE Sequential Address b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0 Bit Locations Swapped Left-to-Right Around Center of Binary Value b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address Pivot Point XB = 0x0008 for a 16-word Bit-Reversed Buffer TABLE 4-2: BIT-REVERSED ADDRESS SEQUENCE 16-ENTRY Normal Address Bit-Reversed Address Decimal Decimal 0 8 4 12 2 10 6 14 1 9 5 13 3 11 7 15 TABLE 4-3: BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER Buffer Size Words XB<14:0> Bit-Reversed Address Modifier Value 4096 2048 1024 512 256 128 64 32 16 8 4 2 0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001 2005 Microchip Technology Inc. DS70143B-page 43 dsPIC30F6011A/6012A/6013A/6014A • Business of Microchip Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives CUSTOMER CHANGE NOTIFICATION SERVICE To register, access the Microchip web site at click on Customer Change Notification and follow the registration instructions. CUSTOMER SUPPORT Users of Microchip products can receive assistance through several channels: • Distributor or Representative • Local Sales Office • Field Application Engineer FAE • Technical Support • Development Systems Information Line Customers should contact their distributor, representative or field application engineer FAE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: In addition, there is a Development Systems Information Line which lists the latest versions of Microchip’s development systems software products. This line also provides information on how customers can receive currently available upgrade kits. The Development Systems Information Line numbers are: 1-800-755-2345 United States and most of Canada 1-480-792-7302 Other International Locations 2005 Microchip Technology Inc. DS70143B-page 233 dsPIC30F6011A/6012A/6013A/6014A READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at 480 Please list the following information, and use this outline to provide us with your comments about this document. To Technical Publications Manager RE Reader Response From Name Company Address City / State / ZIP / Country Telephone - Application optional Would you like a reply? Y N Total Pages Sent FAX - Device dsPIC30F6011A/6012A/ Literature Number DS70143B Questions: What are the best features of this document? How does this document meet your hardware and software development needs? Do you find the organization of this document easy to follow? If not, why? What additions to the document do you think would enhance the structure and subject? What deletions from the document could be made without affecting the overall usefulness? Is there any incorrect or misleading information what and where ? How would you improve this document? DS70143B-page 234 2005 Microchip Technology Inc. dsPIC30F6011A/6012A/6013A/6014A PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Trademark d s P I C 3 0 F 6 0 11 AT- 3 0 I / P F - E S Custom ID 3 digits or Engineering Sample ES Architecture

PDF Datasheet Preview

dsPIC30F6011A/6012A/6013A/6014A Data Sheet

High-Performance Digital Signal Controllers
2005 Microchip Technology Inc.

DS70143B

Note the following details of the code protection feature on Microchip devices
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip’s products as critical components in life support systems is not authorized except with express written approval by Microchip. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, microID, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, PowerSmart, rfPIC, and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

AmpLab, FilterLab, Migratable Memory, MXDEV, MXLAB, PICMASTER, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, dsPICDEM, dsPICDEM.net, dsPICworks, ECAN, ECONOMONITOR, FanSense, FlexROM, fuzzyLAB, In-Circuit Serial Programming, ICSP, ICEPIC, Linear Active Thermistor, MPASM, MPLIB, MPLINK, MPSIM, PICkit, PICDEM, PICDEM.net, PICLAB, PICtail, PowerCal, PowerInfo, PowerMate, PowerTool, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance and WiperLock are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in the U.S.A.

All other trademarks mentioned herein are property of their respective companies.
2005, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved.

Printed on recycled paper.

Microchip received ISO/TS-16949:2002 quality system certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona and Mountain View, California in October The Company’s quality system processes and procedures are for its 8-bit MCUs, code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified.

DS70143B-page ii
2005 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A
dsPIC30F6011A/6012A/6013A/6014A High-Performance Digital Signal Controllers

Note This data sheet summarizes features of this group of dsPIC30F devices and is not intended to be a complete reference source. For more information on the CPU, peripherals, register descriptions and general device functionality, refer to the dsPIC30F Family Reference Manual DS70046 . For more information on the device instruction set and programming, refer to the dsPIC30F Programmer’s Reference Manual DS70030 .

High-Performance Modified RISC CPU:
• Modified Harvard architecture
• C compiler optimized instruction set architecture
• Flexible addressing modes
• 84 base instructions
• 24-bit wide instructions, 16-bit wide data path
• Up to 144 Kbytes on-chip Flash program space
• Up to 48K instruction words
• Up to 8 Kbytes of on-chip data RAM
• Up to 4 Kbytes of nonvolatile data EEPROM
• 16 x 16-bit working register array
• Up to 30 MIPs operation:
- DC to 40 MHz external clock input - 4 MHz-10 MHz oscillator input with PLL
active 4x, 8x, 16x
• Up to 41 interrupt sources:
- 8 user selectable priority levels - 5 external interrupt sources - 4 processor traps

DSP Features:
• Dual data fetch
• Modulo and Bit-Reversed modes
• Two 40-bit wide accumulators with optional
saturation logic
• 17-bit x 17-bit single-cycle hardware fractional/
integer multiplier
• All DSP instructions are single cycle
- Multiply-Accumulate MAC operation
• Single-cycle ±16 shift

Peripheral Features:
• High-current sink/source I/O pins 25 mA/25 mA
• Five 16-bit timers/counters optionally pair up
16-bit timers into 32-bit timer modules
• 16-bit Capture input functions
• 16-bit Compare/PWM output functions
• Data Converter Interface DCI supports common
audio Codec protocols, including I2S and AC’97
• 3-wire SPI modules supports 4 Frame modes
• I2C module supports Multi-Master/Slave mode
and 7-bit/10-bit addressing
• Two addressable UART modules with FIFO
buffers
• Two CAN bus modules compliant with CAN 2.0B
The X AGU also supports bit-reversed addressing on destination effective addresses to greatly simplify input or output data reordering for radix-2 FFT algorithms. Refer to Section “Address Generator Units” for details on modulo and bit-reversed addressing.

The core supports Inherent no operand , Relative, Literal, Memory Direct, Register Direct, Register Indirect, Register Offset and Literal Offset Addressing modes. Instructions are associated with predefined Addressing modes, depending upon their functional requirements.

For most instructions, the core is capable of executing a data or program data memory read, a working register data read, a data memory write and a program instruction memory read per instruction cycle. As a result, 3-operand instructions are supported, allowing C = A+B operations to be executed in a single cycle.

A DSP engine has been included to significantly enhance the core arithmetic capability and throughput. It features a high-speed 17-bit by 17-bit multiplier, a 40-bit ALU, two 40-bit saturating accumulators and a 40-bit bidirectional barrel shifter. Data in the accumulator or any working register can be shifted up to 16 bits right, or 16 bits left in a single cycle. The DSP instructions operate seamlessly with all other instructions and have been designed for optimal real-time performance. The MAC class of instructions can concurrently fetch two data operands from memory while multiplying two W registers. To enable this concurrent fetching of data operands, the data space has been split for these instructions and linear for all others. This has been achieved in a transparent and flexible manner, by dedicating certain working registers to each address space for the MAC class of instructions.
2005 Microchip Technology Inc.

DS70143B-page 15
dsPIC30F6011A/6012A/6013A/6014A

The core does not support a multi-stage instruction pipeline. However, a single stage instruction prefetch mechanism is used, which accesses and partially decodes instructions a cycle ahead of execution, in order to maximize available execution time. Most instructions execute in a single cycle with certain exceptions.

The core features a vectored exception processing structure for traps and interrupts, with 62 independent vectors. The exceptions consist of up to 8 traps of which 4 are reserved and 54 interrupts. Each interrupt is prioritized based on a user assigned priority between 1 and 7 1 being the lowest priority and 7 being the highest , in conjunction with a predetermined ‘natural order’. Traps have fixed priorities ranging from 8 to

Programmer’s Model

The programmer’s model is shown in Figure 2-1 and consists of 16 x 16-bit working registers W0 through W15 , 2 x 40-bit accumulators AccA and AccB , STATUS register SR , Data Table Page register TBLPAG , Program Space Visibility Page register PSVPAG , DO and REPEAT registers DOSTART, DOEND, DCOUNT and RCOUNT and Program Counter PC . The working registers can act as data, address or offset registers. All registers are memory mapped. W0 acts as the W register for file register addressing.

Some of these registers have a shadow register associated with each of them, as shown in Figure The shadow register is used as a temporary holding register and can transfer its contents to or from its host register upon the occurrence of an event. None of the shadow registers are accessible directly. The following rules apply for transfer of registers into and out of shadows.
• PUSH.S and POP.S W0, W1, W2, W3, SR DC, N, OV, Z and C bits only are transferred.
• DO instruction DOSTART, DOEND, DCOUNT shadows are pushed on loop start, and popped on loop end.

When a byte operation is performed on a working register, only the Least Significant Byte LSB of the target register is affected. However, a benefit of memory mapped working registers is that both the Least and Most Significant Bytes can be manipulated through byte wide data memory space accesses.

SOFTWARE STACK POINTER/ FRAME POINTER

The DSC devices contain a software stack. W15 is the dedicated software Stack Pointer SP , and will be automatically modified by exception processing and subroutine calls and returns. However, W15 can be referenced by any instruction in the same manner as all other W registers. This simplifies the reading, writing and manipulation of the Stack Pointer e.g., creating stack frames .

Note In order to protect against misaligned stack accesses, W15<0> is always clear.

W15 is initialized to 0x0800 during a Reset. The user may reprogram the SP during initialization to any location within data space.

W14 has been dedicated as a Stack Frame Pointer as defined by the LNK and ULNK instructions. However, W14 can be referenced by any instruction in the same manner as all other W registers.

STATUS REGISTER

The dsPIC DSC core has a 16-bit STATUS register SR , the LSB of which is referred to as the SR Low byte SRL and the Most Significant Byte MSB as the SR High byte SRH . See Figure 2-1 for SR layout.

SRL contains all the MCU ALU operation status flags including the Z bit , as well as the CPU Interrupt Priority Level status bits, IPL<2:0> and the Repeat Active status bit, RA. During exception processing, SRL is concatenated with the MSB of the PC to form a complete word value which is then stacked.

The upper byte of the STATUS register contains the DSP Adder/Subtracter status bits, the DO Loop Active bit DA and the Digit Carry DC status bit.

PROGRAM COUNTER

The Program Counter is 23-bits wide bit 0 is always clear. Therefore, the PC can address up to 4M instruction words.

DS70143B-page 16
2005 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A

FIGURE 2-1:

PROGRAMMER’S MODEL

DSP Operand Registers

DSP Address Registers

W0/WREG

W3 W4

W6 W7

W12/DSP Offset

W13/DSP Write Back

W14/Frame Pointer

W15/Stack Pointer

PUSH.S Shadow DO Shadow Legend
Bit-reversed addressing is intended to simplify data reordering for radix-2 FFT algorithms. It is supported by the X AGU for data writes only.

BIT-REVERSED ADDRESSING IMPLEMENTATION

Bit-reversed addressing is enabled when:

BWM W register selection in the MODCON register is any value other than ‘15’ the stack cannot be accessed using bit-reversed addressing and
the BREN bit is set in the XBREV register and
the Addressing mode used is Register Indirect with Pre-Increment or Post-Increment.

If the length of a bit-reversed buffer is M = 2N bytes, then the last ‘N’ bits of the data buffer start address must be zeros.

XB<14:0> is the bit-reversed address modifier or ‘pivot point’, which is typically a constant. In the case of an FFT computation, its value is equal to half of the FFT data buffer size.

Note:

All bit-reversed EA calculations assume word sized data LSb of every EA is always clear . The XB value is scaled accordingly to generate compatible byte addresses.

When enabled, bit-reversed addressing will only be executed for register indirect with pre-increment or post-increment addressing and word sized data writes. It will not function for any other Addressing mode or for byte sized data, and normal addresses will be generated instead. When bit-reversed addressing is active, the W address pointer will always be added to the address modifier XB and the offset associated with the Register Indirect Addressing mode will be ignored. In addition, as word sized data is a requirement, the LSb of the EA is ignored and always clear .

Note:

Modulo addressing and bit-reversed addressing should not be enabled together. In the event that the user attempts to do this, bit-reversed addressing will assume priority when active for the X WAGU, and X WAGU modulo addressing will be disabled. However, modulo addressing will continue to function in the X RAGU.

If bit-reversed addressing has already been enabled by setting the BREN XBREV<15> bit, then a write to the XBREV register should not be immediately followed by an indirect read operation using the W register that has been designated as the bit-reversed pointer.

DS70143B-page 42
2005 Microchip Technology Inc.
dsPIC30F6011A/6012A/6013A/6014A

FIGURE 4-2:

BIT-REVERSED ADDRESS EXAMPLE Sequential Address
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 0

Bit Locations Swapped Left-to-Right Around Center of Binary Value
b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b1 b2 b3 b4 0 Bit-Reversed Address

Pivot Point

XB = 0x0008 for a 16-word Bit-Reversed Buffer

TABLE 4-2:

BIT-REVERSED ADDRESS SEQUENCE 16-ENTRY

Normal Address

Bit-Reversed Address

Decimal

Decimal
0 8 4 12 2 10 6 14 1 9 5 13 3 11 7 15

TABLE 4-3:

BIT-REVERSED ADDRESS MODIFIER VALUES FOR XBREV REGISTER

Buffer Size Words

XB<14:0> Bit-Reversed Address Modifier Value
4096 2048 1024 512 256 128
64 32 16 8 4 2
0x0800 0x0400 0x0200 0x0100 0x0080 0x0040 0x0020 0x0010 0x0008 0x0004 0x0002 0x0001
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• Business of Microchip Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives

CUSTOMER CHANGE NOTIFICATION SERVICE

To register, access the Microchip web site at click on Customer Change Notification and follow the registration instructions.

CUSTOMER SUPPORT

Users of Microchip products can receive assistance through several channels:
• Distributor or Representative
• Local Sales Office
• Field Application Engineer FAE
• Technical Support
• Development Systems Information Line

Customers should contact their distributor, representative or field application engineer FAE for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document.

Technical support is available through the web site at:

In addition, there is a Development Systems Information Line which lists the latest versions of Microchip’s development systems software products. This line also provides information on how customers can receive currently available upgrade kits.

The Development Systems Information Line numbers are:
1-800-755-2345 United States and most of Canada
1-480-792-7302 Other International Locations
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READER RESPONSE

It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at 480

Please list the following information, and use this outline to provide us with your comments about this document.

To Technical Publications Manager RE Reader Response

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Device dsPIC30F6011A/6012A/

Literature Number DS70143B

Questions:

What are the best features of this document?

How does this document meet your hardware and software development needs?

Do you find the organization of this document easy to follow? If not, why?

What additions to the document do you think would enhance the structure and subject?

What deletions from the document could be made without affecting the overall usefulness?

Is there any incorrect or misleading information what and where ?

How would you improve this document?

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PRODUCT IDENTIFICATION SYSTEM

To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

Trademark
d s P I C 3 0 F 6 0 11 AT- 3 0 I / P F - E S

Custom ID 3 digits or Engineering Sample ES

Architecture

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DSPIC30F6012AT-20I/PT Datasheet file may be downloaded here without warranties.

Datasheet ID: DSPIC30F6012AT-20I/PT 648101