MM74HC393M
MM74HC393M Datasheet
MM74HC393 Dual 4-Bit Binary Counter
| Part | Datasheet |
|---|---|
MM74HC393M |
MM74HC393M (pdf) |
| Related Parts | Information |
|---|---|
|
MM74HC393N |
MM74HC393N |
MM74HC393SJ |
MM74HC393SJ |
|
MM74HC393MTCX |
MM74HC393MTCX |
|
MM74HC393MTC |
MM74HC393MTC |
|
MM74HC393MX |
MM74HC393MX |
MM74HC393SJX |
MM74HC393SJX |
| PDF Datasheet Preview |
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| MM74HC393 Dual 4-Bit Binary Counter MM74HC393 Dual 4-Bit Binary Counter The MM74HC393 counter circuits contain independent ripple carry counters and utilize advanced silicon-gate CMOS technology. The MM74HC393 contains two 4-bit ripple carry binary counters, which can be cascaded to create a single divide-by-256 counter. Each of the two 4-bit counters is incremented on the HIGHto-LOW transition negative edge of the clock input, and each has an independent clear input. When clear is set HIGH all four bits of each counter are set to a low level. This enables count truncation and allows the implementation of divide-by-N counter configurations. Each of the counters outputs can drive 10 low power Schottky TTL equivalent loads. This counter is functionally as well as pin equivalent to the 74LS393. All inputs are protected from damage due to static discharge by diodes to VCC and ground. s Typical operating frequency 50 MHz s Typical propagation delay 13 ns Ck to QA s Wide operating supply voltage range s Low input current <1 µA s Low quiescent supply current 80 µA maximum 74HC Series s Fanout of 10 LS-TTL loads Ordering Code: Order Number Package Number Package Description MM74HC393M M14A 14-Lead Small Outline Integrated Circuit SOIC , JEDEC MS-012, Narrow MM74HC393SJ M14D Pb-Free 14-Lead Small Outline Package SOP , EIAJ TYPE II, 5.3mm Wide MM74HC393MTC MTC14 14-Lead Thin Shrink Small Outline Package TSSOP , JEDEC MO-153, 4.4mm Wide MM74HC393N N14A 14-Lead Plastic Dual-In-Line Package PDIP , JEDEC MS-001, Wide Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Pb-Free package per JEDEC J-STD-020B. Connection Diagram Pin Assignments for DIP, SOIC, SOP and TSSOP Top View 2005 Fairchild Semiconductor Corporation DS005337 MM74HC393 Absolute Maximum Ratings Note 2 Note 1 Supply Voltage VCC DC Input Voltage VIN DC Output Voltage VOUT Clamp Diode Current IIK, IOK DC Output Current, per pin IOUT DC VCC or GND Current, per pin ICC Storage Temperature Range TSTG Power Dissipation PD Note 3 S.O. Package only Lead Temperature TL Soldering 10 seconds to +7.0V to VCC +1.5V to VCC +0.5V ±20 mA ±25 mA ±50 mA −65°C to +150°C 600 mW 500 mW 260°C Recommended Operating Conditions Min Max Units Supply Voltage VCC DC Input or Output Voltage VIN, VOUT Operating Temperature Range TA −40 +85 Input Rise or Fall Times tr, tf VCC = 2.0V 1000 ns VCC = 4.5V VCC = 6.0V Note 1 Absolute Maximum Ratings are those values beyond which dam- age to the device may occur. Note 2 Unless otherwise specified all voltages are referenced to ground. Note 3 Power Dissipation temperature derating plastic “N” package − 12 mW/°C from 65°C to 85°C. DC Electrical Characteristics Note 4 Parameter Conditions TA = 25°C TA = −40 to 85°C TA = −55 to 125°C Units Guaranteed Limits Minimum HIGH Level Input Voltage 2.0V 4.5V 6.0V Maximum LOW Level Input Voltage |
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