SY89540UMI-TR

SY89540UMI-TR Datasheet

SY89540U

Part	Datasheet
SY89540UMI-TR	SY89540UMI-TR (pdf)

Related Parts	Information
SY89540UMI	SY89540UMI

PDF Datasheet Preview
SY89540U Precision Low Jitter 4x4 LVDS Crosspoint Switch with Internal Termination The SY89540U is a low-jitter, low skew, high-speed 4x4 crosspoint switch optimized for precision telecom and enterprise server/storage distribution applications. The SY89540U guarantees data-rates up to 3.2Gbps over temperature and voltage. The SY89540U differential input includes Micrel’s unique, 3-pin input termination architecture that directly interfaces to any differential signal AC or DC-coupled as small as 100mV 200mVpp without any level shifting or termination resistor networks in the signal path. The LVDS compatible outputs maintain extremely fast rise/fall times guaranteed to be less than 120ps. The SY89540U features a patent-pending isolation design that significantly improves on channel-tochannel crosstalk performance. The SY89540U operates from a 2.5V ±5% supply and is guaranteed over the full industrial temperature range to +85°C . The SY89540U is part of Micrel’s high-speed, Precision product line. All support documentation can be found on Micrel’s web site at Typical Performance Precision • Provides crosspoint switching between any input pairs to any output pair • Patent pending, channel-to-channel isolation design provides superior crosstalk performance • Guaranteed AC performance over temperature and voltage: • DC-to-3.2Gbps throughput <480ps propagation delay <120ps rise/fall time <30ps output-to-output skew • Ultra-low jitter design <1psRMS random jitter <10psPP deterministic jitter <10psPP total jitter clock <0.7psRMS crosstalk induced jitter • Patent pending input termination, extended CMVR, and VT pin accepts DC- and AC-coupled differential inputs • 350mV LVDS output swing • Power supply 2.5V ±5% • to +85°C temperature range • Available in 44-pin 7mm x 7mm package • Pb-Free Green package • All SONET/SDH channel select applications • All Fibre Channel multi-channel select applications • All Gigabit Ethernet multi-channel select Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc. December 2007 M9999-120607-C or 408 955-1690 Micrel, Inc. Functional Block Diagram SY89540U December 2007 M9999-120607-C or 408 955-1690 Micrel, Inc. Ordering Information 1 Package Temperature Type Range Package Marking SY89540UMI SY89540UMITR 2 MLF-44 MLF-44 Industrial SY89540U 89540U SY89540UMY SY89540UMYTR 2 MLF-44 MLF-44 Industrial SY89540U with Pb-Free bar-line indicator SY89540U with Pb-Free bar-line indicator Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electrical only. Tape and Reel ordering option. Pin Configuration SY89540U Lead Finish Sn-Pb Sn-Pb-Free Matte-Sn Pb-Free Matte-Sn 44-Pin MLF-44 December 2007 M9999-120607-C or 408 955-1690 Micrel, Inc. SY89540U Pin Description Pin Number 17, 15, 10, 8 4, 2 41, 39 16, 9, 3, 40 Pin Name IN0, /IN0, IN1, /IN1, IN2, /IN2, IN3, /IN3 VT0, VT1, VT2, VT3 Pin Function Differential Inputs These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through Note that these inputs will default to an indeterminate state if left open. Please refer to the "Input Interface Applications" section for more details. Input Termination Center-Tap Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" section for more details. VREF_AC0, Reference Voltage This output biases to It is used when AC- VREF_AC1, coupling the inputs IN, /IN . Connect VREF_AC to the VT pin. Bypass each VREF_AC2, VREF-AC pin with a 0.01µF low ESR capacitor. See "Input Interface VREF_AC3 Applications" section for more details. 18, 19 38, 37 23, 24, 26, 27, 29, 30, 32, 33 SIN0, SIN1 SOUT0, SOUT1 CONF, LOAD Q0, /Q0, Q1, /Q1, Q2, /Q2, Q3, /Q3, These single-ended TTL/CMOS-compatible inputs address the data inputs. Note that these inputs are internally connected to a pull-up resistor and will default to a logic HIGH state if left open. These single-ended TTL/CMOS-compatible inputs address the data outputs. Note that these inputs are internally connected to a pull-up resistor and will default to logic HIGH state if left open. These single-ended TTL/CMOS-compatible inputs control the transfer of the addresses to the internal multiplexers. See "Address Tables" and "Timing Diagram" sections for more details. Note that these inputs are internally connected to a pull-up resistor and will default to logic HIGH state if left open. Configuration Sequence Load Loads configuration into buffer, while Configuration Buffer holds existing switch configuration. Configuration Loads new configuration into the Configuration Buffer and updates switch configuration. Buffer Mode The SY89540U defaults to buffer mode IN to Q if the load and configuration control signals are not exercised. Differential Outputs These LVDS output pairs are the outputs of the device. Please refer to the truth table below for details. Unused output pairs may be left open. Each output is designed to drive 350mV into across the pair. 6, 22, 25, 28, 31, 34 12, 13, 20, 21,35, 36, 43, 44 GND, Exposed pad Positive power supply. Bypass with 0.1µF//0.01µF low ESR capacitors and place as close to each VCC pin. Ground. GND and EPad must both be connected to the same ground.

PDF Datasheet Preview

SY89540U

Precision Low Jitter 4x4 LVDS Crosspoint Switch with Internal Termination

The SY89540U is a low-jitter, low skew, high-speed 4x4 crosspoint switch optimized for precision telecom and enterprise server/storage distribution applications. The SY89540U guarantees data-rates up to 3.2Gbps over temperature and voltage.

The SY89540U differential input includes Micrel’s unique, 3-pin input termination architecture that directly interfaces to any differential signal AC or DC-coupled as small as 100mV 200mVpp without any level shifting or termination resistor networks in the signal path. The LVDS compatible outputs maintain extremely fast rise/fall times guaranteed to be less than 120ps.

The SY89540U features a patent-pending isolation design that significantly improves on channel-tochannel crosstalk performance.

The SY89540U operates from a 2.5V ±5% supply and is guaranteed over the full industrial temperature range to +85°C . The SY89540U is part of Micrel’s high-speed, Precision product line.

All support documentation can be found on Micrel’s web site at

Typical Performance

Precision
• Provides crosspoint switching between any input pairs to any output pair
• Patent pending, channel-to-channel isolation design provides superior crosstalk performance
• Guaranteed AC performance over temperature and voltage:
• DC-to-3.2Gbps throughput <480ps propagation delay <120ps rise/fall time <30ps output-to-output skew
• Ultra-low jitter design <1psRMS random jitter <10psPP deterministic jitter <10psPP total jitter clock <0.7psRMS crosstalk induced jitter
• Patent pending input termination, extended CMVR, and VT pin accepts DC- and AC-coupled differential inputs
• 350mV LVDS output swing
• Power supply 2.5V ±5%
• to +85°C temperature range
• Available in 44-pin 7mm x 7mm package
• Pb-Free Green package
• All SONET/SDH channel select applications
• All Fibre Channel multi-channel select
applications
• All Gigabit Ethernet multi-channel select

Precision Edge is a registered trademark of Micrel, Inc. MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.

December 2007

M9999-120607-C or 408 955-1690

Micrel, Inc.

Functional Block Diagram

SY89540U

December 2007

M9999-120607-C
or 408 955-1690

Micrel, Inc.
Ordering Information 1

Package Temperature

Type

Range

Package Marking

SY89540UMI SY89540UMITR 2

MLF-44 MLF-44

Industrial

SY89540U 89540U

SY89540UMY SY89540UMYTR 2

MLF-44 MLF-44

Industrial

SY89540U with Pb-Free bar-line indicator

SY89540U with Pb-Free bar-line indicator
Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electrical only. Tape and Reel ordering option.

Pin Configuration

SY89540U

Lead Finish Sn-Pb Sn-Pb-Free Matte-Sn Pb-Free Matte-Sn
44-Pin MLF-44

December 2007

M9999-120607-C
or 408 955-1690

Micrel, Inc.

SY89540U

Pin Description

Pin Number 17, 15, 10, 8 4, 2 41, 39
16, 9, 3, 40

Pin Name IN0, /IN0, IN1, /IN1, IN2, /IN2, IN3, /IN3

VT0, VT1, VT2, VT3

Pin Function

Differential Inputs These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-coupled signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through Note that these inputs will default to an indeterminate state if left open. Please refer to the "Input Interface Applications" section for more details.

Input Termination Center-Tap Each side of the differential input pair terminates to a VT pin. The VT pins provide a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" section for more details.

VREF_AC0, Reference Voltage This output biases to It is used when AC-

VREF_AC1, coupling the inputs IN, /IN . Connect VREF_AC to the VT pin. Bypass each

VREF_AC2, VREF-AC pin with a 0.01µF low ESR capacitor. See "Input Interface

VREF_AC3 Applications" section for more details.
18, 19 38, 37
23, 24, 26, 27, 29, 30, 32, 33

SIN0, SIN1 SOUT0, SOUT1 CONF, LOAD

Q0, /Q0, Q1, /Q1, Q2, /Q2, Q3, /Q3,

These single-ended TTL/CMOS-compatible inputs address the data inputs. Note that these inputs are internally connected to a pull-up resistor and will default to a logic HIGH state if left open.

These single-ended TTL/CMOS-compatible inputs address the data outputs. Note that these inputs are internally connected to a pull-up resistor and will default to logic HIGH state if left open.

These single-ended TTL/CMOS-compatible inputs control the transfer of the addresses to the internal multiplexers. See "Address Tables" and "Timing Diagram" sections for more details. Note that these inputs are internally connected to a pull-up resistor and will default to logic HIGH state if left open.

Configuration Sequence

Load Loads configuration into buffer, while Configuration Buffer holds existing switch configuration.

Configuration Loads new configuration into the Configuration Buffer and updates switch configuration.

Buffer Mode

The SY89540U defaults to buffer mode IN to Q if the load and configuration control signals are not exercised.

Differential Outputs These LVDS output pairs are the outputs of the device. Please refer to the truth table below for details. Unused output pairs may be left open. Each output is designed to drive 350mV into across the pair.
6, 22, 25, 28, 31, 34
12, 13, 20, 21,35, 36,
43, 44

GND, Exposed pad

Positive power supply. Bypass with 0.1µF//0.01µF low ESR capacitors and place as close to each VCC pin.

Ground. GND and EPad must both be connected to the same ground.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived SY89540UMI-TR Datasheet file may be downloaded here without warranties.

Datasheet ID: SY89540UMI-TR 647958