DS1220Y-120+

DS1220Y-120+ Datasheet

DS1220Y 16k Nonvolatile SRAM

Part	Datasheet
DS1220Y-120+	DS1220Y-120+ (pdf)

Related Parts	Information
DS1220Y-150+	DS1220Y-150+

PDF Datasheet Preview
10 years minimum data retention in the absence of external power Data is automatically protected during power loss Directly replaces 2k x 8 volatile static RAM or EEPROM Unlimited write cycles Low-power CMOS JEDEC standard 24-pin DIP package Read and write access times as fast as 100 ns Full ±10% operating range Optional industrial temperature range of -40°C to +85°C, designated IND Not Recommended for New Design DS1220Y 16k Nonvolatile SRAM PIN ASSIGNMENT A7 1 A6 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 DQ0 9 DQ1 10 DQ2 11 GND 12 24 VCC 23 A8 21 WE 19 A10 17 DQ7 14 DQ4 13 DQ3 24-Pin ENCAPSULATED PACKAGE 720-mil EXTENDED PIN DESCRIPTION A0-A10 DQ0-DQ7 - Address Inputs - Data In/Data Out - Chip Enable - Write Enable OE VCC GND - Output Enable - Power +5V - Ground The DS1220Y 16k Nonvolatile SRAM is a 16,384-bit, fully static, nonvolatile RAM organized as 2048 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAM can be used in place of existing 2k x 8 SRAMs directly conforming to the popular bytewide 24-pin DIP standard. The DS1220Y also matches the pinout of the 2716 EPROM or the 2816 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. 1 of 8 121907 READ MODE DS1220Y The DS1220Y executes a read cycle whenever WE Write Enable is inactive high and CE Chip Enable and OE Output Enable are active low . The unique address specified by the 11 address inputs A0-A10 defines which of the 2048 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC Access Time after the last address input signal is stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is either tCO for CE or tOE for OE rather than address access. WRITE MODE The DS1220Y executes a write cycle whenever the WE and CE signals are active low after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time tWR before another cycle can be initiated. The OE control signal should be kept inactive high during write cycles to avoid bus contention. However, if the output drivers are enabled CE and OE active then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1220Y provides full-functional capability for VCC greater than volts and write protects at nominal. Data is maintained in the absence of VCC without any additional support circuitry. The DS1220Y constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write protects itself, all inputs become “don’t care,” and all outputs become high-impedance. As VCC falls below approximately volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately volts, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds volts. 2 of 8 ORDERING INFORMATION TEMPERATURE RANGE DS1220Y-100 0°C to +70°C DS1220Y-100+ 0°C to +70°C DS1220Y-100IND -40°C to +85°C DS1220Y-100IND+ -40°C to +85°C DS1220Y-120 0°C to +70°C DS1220Y-120+ 0°C to +70°C DS1220Y-150 0°C to +70°C DS1220Y-150+ 0°C to +70°C DS1220Y-200 0°C to +70°C DS1220Y-200+ 0°C to +70°C DS1220Y-200IND -40°C to +85°C DS1220Y-200IND+ -40°C to +85°C + Denotes lead-free/RoHS-compliant product. SUPPLY TOLERANCE 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% PIN/PACKAGE 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD SPEED GRADE 100ns 120ns 150ns 200ns PACKAGE INFORMATION For the latest package outline information, go to PACKAGE TYPE 24 DIP DOCUMENT NO. 56-G0002-001 7 of 8 Added package information table. 121907 Removed the DIP module package drawing and dimension table.

PDF Datasheet Preview

10 years minimum data retention in the
absence of external power Data is automatically protected during power
loss Directly replaces 2k x 8 volatile static RAM
or EEPROM Unlimited write cycles Low-power CMOS JEDEC standard 24-pin DIP package Read and write access times as fast as 100 ns Full ±10% operating range Optional industrial temperature range of
-40°C to +85°C, designated IND

Not Recommended for New Design

DS1220Y 16k Nonvolatile SRAM

PIN ASSIGNMENT

A7 1 A6 2 A5 3 A4 4 A3 5 A2 6 A1 7 A0 8 DQ0 9 DQ1 10

DQ2 11

GND 12
24 VCC
23 A8
21 WE
19 A10
17 DQ7
14 DQ4
13 DQ3
24-Pin ENCAPSULATED PACKAGE 720-mil EXTENDED

PIN DESCRIPTION

A0-A10 DQ0-DQ7
- Address Inputs - Data In/Data Out
- Chip Enable
- Write Enable

OE VCC GND
- Output Enable - Power +5V - Ground

The DS1220Y 16k Nonvolatile SRAM is a 16,384-bit, fully static, nonvolatile RAM organized as 2048 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAM can be used in place of existing 2k x 8 SRAMs directly conforming to the popular bytewide 24-pin DIP standard. The DS1220Y also matches the pinout of the 2716 EPROM or the 2816 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
1 of 8
121907

READ MODE

DS1220Y

The DS1220Y executes a read cycle whenever WE Write Enable is inactive high and CE Chip

Enable and OE Output Enable are active low . The unique address specified by the 11 address inputs A0-A10 defines which of the 2048 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC Access Time after the last address input signal is stable, providing
that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data
access must be measured from the later-occurring signal and the limiting parameter is either tCO for CE or
tOE for OE rather than address access.

WRITE MODE

The DS1220Y executes a write cycle whenever the WE and CE signals are active low after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time tWR before another cycle can be initiated. The OE control signal should be kept inactive high during write cycles to avoid bus contention. However, if the output drivers are enabled CE and OE active then WE will disable the outputs in tODW from its falling edge.

DATA RETENTION MODE

The DS1220Y provides full-functional capability for VCC greater than volts and write protects at nominal. Data is maintained in the absence of VCC without any additional support circuitry. The DS1220Y constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write protects itself, all inputs become “don’t care,” and all outputs become high-impedance. As VCC falls below approximately volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately volts, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds volts.
2 of 8
ORDERING INFORMATION

TEMPERATURE RANGE

DS1220Y-100
0°C to +70°C

DS1220Y-100+
0°C to +70°C

DS1220Y-100IND
-40°C to +85°C

DS1220Y-100IND+
-40°C to +85°C

DS1220Y-120
0°C to +70°C

DS1220Y-120+
0°C to +70°C

DS1220Y-150
0°C to +70°C

DS1220Y-150+
0°C to +70°C

DS1220Y-200
0°C to +70°C

DS1220Y-200+
0°C to +70°C

DS1220Y-200IND
-40°C to +85°C

DS1220Y-200IND+
-40°C to +85°C
+ Denotes lead-free/RoHS-compliant product.

SUPPLY TOLERANCE
5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10%

PIN/PACKAGE
24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD 24 / 720 EMOD

SPEED GRADE
100ns 120ns 150ns 200ns

PACKAGE INFORMATION

For the latest package outline information, go to

PACKAGE TYPE 24 DIP

DOCUMENT NO. 56-G0002-001
7 of 8

Added package information table.
121907

Removed the DIP module package drawing and dimension table.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DS1220Y-120+ Datasheet file may be downloaded here without warranties.

Datasheet ID: DS1220Y-120+ 647151