SY100S336AFC

SY100S336AFC Datasheet

SY100S336A

Part	Datasheet
SY100S336AFC	SY100S336AFC (pdf)

Related Parts	Information
SY100S336AJC	SY100S336AJC

PDF Datasheet Preview
Micrel, Inc. ENHANCED 4-STAGE COUNTER/SHIFT REGISTER SY100S336A SY100S336A s Max. shift frequency of 700MHz s Clock to Q delay max. of 1100ps s Sn to TC speed improved by 50% s Sn set-up and hold time reduced by more than 50% s IEE min. of s Industry standard 100K ECL levels s Internal input pull-down resistors s Extended supply voltage option: VEE = to s Voltage and temperature compensation for improved noise immunity s 50% faster than Fairchild 300K at lower power s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages PIN NAMES Pin CP CEP D0/CET S0 S2 MR VEES VCCA P0 P3 D3 TC Q0 Q3 Q0 Q3 Function Clock Pulse Input Count Enable Parallel Input Active LOW Serial Data Input/Count Enable Trickle Input Active LOW Select Inputs Master Reset Input VEE Substrate VCCO for ECL Outputs Preset Inputs Serial Data Input Terminal Count Output Data Outputs Complementary Data Outputs The SY100S336A is functionally the same as the SY100S336, but has Sn to TC speed and Sn set-up and hold times significantly improved, allowing for higher clock frequency when used as a cascaded multi-stage counter. The SY100S336A functions either as a modulo-16 up/ down counter or as a 4-bit bidirectional shift register and is designed for use in high-performance ECL systems. Three Select inputs Sn are provided for determining the mode of operation. The Function Table lists the available modes of operation. In order to allow cascading for multistage counters, two Count Enable controls CEP, CET are provided. The CET input also functions as the Serial Data input S0 for a shift-up operation, while the D3 input serves as the Serial Data input for the shift-down operation. When the device is in the counting mode, the Terminal Count TC goes to a logical LOW when the count reaches 15 for count-up or reaches 0 for count-down. When in the shift mode, the TC output simply repeats the Q3 output. The flexiblity provided by the TC/Q3 output and the D0/ CET input allows these signals to be interconnected from one stage to the next higher stage for multistage counting or shift-up operations. The individual Presets Pn allow initialization of the counter by entering data in parallel to preset the counter. A logic HIGH on the Master Reset MR overrides all other inputs and asynchronously clears the flip-flops. An additional synchronous Clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have pulldown resistors. M9999-032206 or 408 955-1690 Micrel, Inc. SY100S336A PACKAGE/ORDERING INFORMATION P1 P2 P3 VEES D3 Q3 Ordering Information P0 CP VEE VEES MR S0 S1 11 10 9 8 7 6 5 Top View PLCC J28-1 19 20 21 22 23 24 25 Q2 VCCA VCC Q1 Package Operating Type Range Package Marking Lead Finish SY100S336AFC SY100S336AFCTR 1 F24-1 F24-1 Commercial SY100S336AFC Sn-Pb Sn-Pb SY100S336AJC SY100S336AJCTR 1 SY100S336AJZ 2 J28-1 J28-1 J28-1 SY100S336AJZTR 1, 2 J28-1 Commercial SY100S336AJC Sn-Pb Commercial SY100S336AJC Sn-Pb Commercial SY100S336AJZ with Matte-Sn Pb-Free bar-line indicator Commercial SY100S336AJZ with Matte-Sn Pb-Free bar-line indicator S2 CEP D0/CET VEES TC Q0 28-Pin PLCC J28-1 Tape and Reel. Pb-Free package is recommended for new designs. S1 S0 MR VEE CP P0 24 23 22 21 20 19 CEP 2 D0/CET 3 TC 4 Q0 5 Top View 16 P3 Flatpack F24-1 7 8 9 10 11 12 Q1 VCC VCCA Q2 24-Pin Cerpack F24-1

PDF Datasheet Preview

Micrel, Inc.

ENHANCED 4-STAGE COUNTER/SHIFT REGISTER

SY100S336A

SY100S336A
s Max. shift frequency of 700MHz s Clock to Q delay max. of 1100ps s Sn to TC speed improved by 50% s Sn set-up and hold time reduced by more than 50% s IEE min. of s Industry standard 100K ECL levels s Internal input pull-down resistors s Extended supply voltage option:

VEE = to s Voltage and temperature compensation for improved
noise immunity s 50% faster than Fairchild 300K at lower power s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC
packages

PIN NAMES

Pin CP CEP D0/CET

S0 S2 MR VEES VCCA P0 P3 D3 TC Q0 Q3 Q0 Q3

Function Clock Pulse Input Count Enable Parallel Input Active LOW Serial Data Input/Count Enable Trickle Input Active LOW Select Inputs Master Reset Input VEE Substrate VCCO for ECL Outputs Preset Inputs Serial Data Input Terminal Count Output Data Outputs Complementary Data Outputs

The SY100S336A is functionally the same as the SY100S336, but has Sn to TC speed and Sn set-up and hold times significantly improved, allowing for higher clock frequency when used as a cascaded multi-stage counter.

The SY100S336A functions either as a modulo-16 up/ down counter or as a 4-bit bidirectional shift register and is designed for use in high-performance ECL systems. Three Select inputs Sn are provided for determining the mode of operation. The Function Table lists the available modes of operation. In order to allow cascading for multistage counters, two Count Enable controls CEP, CET are provided. The CET input also functions as the Serial Data input S0 for a shift-up operation, while the D3 input serves as the Serial Data input for the shift-down operation.

When the device is in the counting mode, the Terminal Count TC goes to a logical LOW when the count reaches 15 for count-up or reaches 0 for count-down. When in the shift mode, the TC output simply repeats the Q3 output.

The flexiblity provided by the TC/Q3 output and the D0/ CET input allows these signals to be interconnected from one stage to the next higher stage for multistage counting or shift-up operations. The individual Presets Pn allow initialization of the counter by entering data in parallel to preset the counter. A logic HIGH on the Master Reset MR overrides all other inputs and asynchronously clears the flip-flops. An additional synchronous Clear is provided, as well as a complement function which synchronously inverts the contents of the flip-flops. All inputs have pulldown resistors.

M9999-032206 or 408 955-1690

Micrel, Inc.

SY100S336A
PACKAGE/ORDERING INFORMATION

P1 P2 P3 VEES D3 Q3
Ordering Information

P0 CP VEE VEES MR S0 S1
11 10 9 8 7 6 5

Top View

PLCC J28-1
19 20 21 22 23 24 25

Q2 VCCA VCC Q1

Package Operating

Type

Range

Package Marking

Lead Finish

SY100S336AFC SY100S336AFCTR 1

F24-1 F24-1

Commercial

SY100S336AFC

Sn-Pb Sn-Pb

SY100S336AJC SY100S336AJCTR 1 SY100S336AJZ 2

J28-1 J28-1 J28-1

SY100S336AJZTR 1, 2 J28-1

Commercial

SY100S336AJC

Sn-Pb

Commercial

SY100S336AJC

Sn-Pb

Commercial SY100S336AJZ with Matte-Sn Pb-Free bar-line indicator

Commercial SY100S336AJZ with Matte-Sn Pb-Free bar-line indicator

S2 CEP D0/CET VEES

TC Q0
28-Pin PLCC J28-1

Tape and Reel. Pb-Free package is recommended for new designs.

S1 S0 MR VEE CP P0
24 23 22 21 20 19

CEP 2

D0/CET 3 TC 4 Q0 5

Top View 16 P3

Flatpack F24-1
7 8 9 10 11 12

Q1 VCC VCCA Q2
24-Pin Cerpack F24-1

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Datasheet ID: SY100S336AFC 647930