SY100S331FC

SY100S331FC Datasheet

SY100S331 FINAL

Part	Datasheet
SY100S331FC	SY100S331FC (pdf)

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TRIPLE D FLIP-FLOP SY100S331 FINAL s Max. toggle frequency of 800MHz s Differential outputs s IEE min. of s Industry standard 100K ECL levels s Extended supply voltage option: VEE = to s Voltage and temperature compensation for improved noise immunity s Internal input pull-down resistors s 150% faster than Fairchild s 40% lower power than Fairchild s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC packages The SY100S331 offers three D-type, edge-triggered master/slave flip-flops with true and complement outputs, designed for use in high-performance ECL systems. Each flip-flop is controlled by a common clock CPc , as well as its own clock pulse CPn . The resultant clock signal controlling the flip-flop is the logical OR operation of these two clock signals. Data enters the master when both CPc and CPn are LOW and enters the slave on the rising edge of either CPc or CPn or both . Additional control signals include Master Set MS and Master Reset MR inputs. Each flip-flop also has its own Direct Set SDn and Direct Clear CDn signals. The MR, MS, SDn and DCn signals override the clock signals. The inputs on this device have pull-down resistors. PIN CONFIGURATIONS SD0 CD0 CP0 VEES D0 Q0 BLOCK DIAGRAM CPC CP2 MS CPC VEE VEES MR SD1 11 10 9 8 7 6 5 Top View PLCC J28-1 19 20 21 22 23 24 25 Q1 VCCA VCC Q2 CP1 CD1 SD2 VEES CD2 CP2 D2 D1 SD1 MR VEE CPC MS 24 23 22 21 20 19 CP1 1 18 SD0 CD1 2 17 CD0 SD2 3 CD2 4 CP2 5 Top View 16 CP0 Flatpack F24-1 14 Q0 13 Q0 7 8 9 10 11 12 Q2 VCC VCCA Q1 MS MR Issue Date July, 1999 Micrel PIN NAMES Pin CP0 CP2 CPc D0 D2 CD0 CD2 SDn MR MS Q0 Q2 Q0 Q2 VEES VCCA Function Individual Clock Inputs Common Clock Input Data Inputs Individual Direct Clear Inputs Individual Direct Set Inputs Master Reset Input Master Set Input Data Outputs Complementary Data Outputs VEE Substrate VCCO for ECL Outputs SY100S331 TRUTH TABLES PRODUCT ORDERING CODE Ordering Code SY100S331FC SY100S331JC SY100S331JCTR Package Type F24-1 J28-1 J28-1 Operating Range Commercial Micrel 24 LEAD CERPACK F24-1 SY100S331 Micrel 28 LEAD PLCC J28-1 SY100S331 MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA TEL + 1 408 980-9191 FAX + 1 408 914-7878 WEB This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. 2000 Micrel Incorporated 7

PDF Datasheet Preview

TRIPLE D FLIP-FLOP

SY100S331 FINAL
s Max. toggle frequency of 800MHz s Differential outputs s IEE min. of s Industry standard 100K ECL levels s Extended supply voltage option:

VEE = to s Voltage and temperature compensation for improved
noise immunity s Internal input pull-down resistors s 150% faster than Fairchild s 40% lower power than Fairchild s Function and pinout compatible with Fairchild F100K s Available in 24-pin CERPACK and 28-pin PLCC
packages

The SY100S331 offers three D-type, edge-triggered master/slave flip-flops with true and complement outputs, designed for use in high-performance ECL systems. Each flip-flop is controlled by a common clock CPc , as well as its own clock pulse CPn . The resultant clock signal controlling the flip-flop is the logical OR operation of these two clock signals. Data enters the master when both CPc and CPn are LOW and enters the slave on the rising edge of either CPc or CPn or both .

Additional control signals include Master Set MS and Master Reset MR inputs. Each flip-flop also has its own Direct Set SDn and Direct Clear CDn signals. The MR, MS, SDn and DCn signals override the clock signals. The inputs on this device have pull-down resistors.

PIN CONFIGURATIONS

SD0 CD0 CP0 VEES D0 Q0

BLOCK DIAGRAM

CPC CP2

MS CPC VEE VEES MR SD1
11 10 9 8 7 6 5

Top View

PLCC

J28-1
19 20 21 22 23 24 25

Q1 VCCA VCC Q2

CP1 CD1 SD2 VEES CD2 CP2

D2 D1 SD1 MR VEE CPC MS
24 23 22 21 20 19

CP1 1
18 SD0

CD1 2
17 CD0

SD2 3 CD2 4 CP2 5

Top View 16 CP0

Flatpack F24-1
14 Q0
13 Q0
7 8 9 10 11 12

Q2 VCC VCCA Q1

MS MR

Issue Date July, 1999

Micrel

PIN NAMES

Pin CP0 CP2 CPc D0 D2 CD0 CD2 SDn MR MS Q0 Q2 Q0 Q2 VEES VCCA

Function Individual Clock Inputs Common Clock Input Data Inputs Individual Direct Clear Inputs Individual Direct Set Inputs Master Reset Input Master Set Input Data Outputs Complementary Data Outputs VEE Substrate VCCO for ECL Outputs

SY100S331

TRUTH TABLES
PRODUCT ORDERING CODE
Ordering Code

SY100S331FC SY100S331JC SY100S331JCTR

Package Type F24-1 J28-1 J28-1

Operating Range

Commercial

Micrel
24 LEAD CERPACK F24-1

SY100S331

Micrel
28 LEAD PLCC J28-1

SY100S331

MICREL-SYNERGY 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA TEL + 1 408 980-9191 FAX + 1 408 914-7878 WEB

This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. 2000 Micrel Incorporated 7

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived SY100S331FC Datasheet file may be downloaded here without warranties.

Datasheet ID: SY100S331FC 647929