KSZ8895RQI
KSZ8895RQI Datasheet
KSZ8895MQ/RQ/FMQ
| Part | Datasheet |
|---|---|
KSZ8895RQI |
KSZ8895RQI (pdf) |
| Related Parts | Information |
|---|---|
KSZ8895MQ-EVAL |
KSZ8895MQ-EVAL |
KSZ8895FMQI TR |
KSZ8895FMQI TR |
KSZ8895MQI |
KSZ8895MQI |
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KSZ8895FMQ TR |
KSZ8895FMQ TR |
KSZ8895RQ |
KSZ8895RQ |
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KSZ8895FMQ |
KSZ8895FMQ |
KSZ8895FMQI |
KSZ8895FMQI |
KSZ8895MQ |
KSZ8895MQ |
KSZ8895FMQ-EVAL |
KSZ8895FMQ-EVAL |
| PDF Datasheet Preview |
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| KSZ8895MQ/RQ/FMQ Integrated 5-Port 10/100 Managed Ethernet Switch with MII/RMII Interface The KSZ8895MQ/RQ/FMQ is a highly-integrated, Layer 2 managed, five-port switch with numerous features designed to reduce system cost. Intended for cost-sensitive 10/100Mbps five-port switch systems with low power consumption, on-chip termination, and internal core power controllers, it supports high-performance memory bandwidth and shared memory-based switch fabric with non-blocking configuration. Its extensive feature set includes power management, programmable rate limit and priority ratio, tag/port-based VLAN, packets filtering, four-queue QoS prioritization, management interfaces, and MIB counters. The KSZ8895 family provides multiple CPU data interfaces to effectively address both current and emerging fast Ethernet applications when port 5 is configured to separate MAC5 with SW5-MII/RMII and PHY5 with P5-MII/RMII interfaces. Functional Diagram The KSZ8895 family offers three configurations, providing the flexibility to meet different requirements: • KSZ8895MQ Five 10/100Base-T/TX transceivers, one SW5-MII and one P5-MII interface, • KSZ8895RQ Five 10/100Base-T/TX transceivers, one SW5-RMII and one P5-RMII interface • KSZ8895FMQ Three 10/100Base-T/TX transceivers on Ports 1, 2, 5 and two 100Base-FX transceivers on Ports 3, 4, one SW5-MII and one P5-MII interface All registers of MACs and PHYs units can be managed by the SPI or the SMI interface. MIIM registers can be accessed through the MDC/MDIO interface. EEPROM can set all control registers for the unmanaged mode. KSZ8895MQ/RQ/FMQ are 128-pin PQFP packages. Note SW5 indicates the MAC5 of the switch side, P5 indicates the PHY5 of the Port Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 408 944-0800 • fax + 1 408 474-1000 • March 19, 2014 Micrel, Inc. Advanced Switch Features • IEEE 802.1q VLAN support for up to 128 active VLAN groups full-range 4096 of VLAN IDs . • Static MAC table supports up to 32 entries. • VLAN ID tag/untag options, per port basis • IEEE 802.1p/q tag insertion or removal on a per port basis based on ingress port egress . • Programmable rate limiting at the ingress and egress on a per port basis. • Jitter-free per packet based rate limiting support. • Broadcast storm protection with percentage control global and per port basis . • IEEE 802.1d rapid spanning tree protocol RSTP support. • Tail tag mode 1 byte added before FCS support at Port 5 to inform the processor which ingress port receives the packet. • 1.4Gbps high-performance memory bandwidth and shared memory-based switch fabric with fully non-blocking configuration. • Dual MII with MAC5 and PHY5 on port 5, SW5-MII/RMII for MAC 5 and P5-MII/RMII for PHY • Enable/Disable option for huge frame size up to 2000 Bytes per frame. • IGMP v1/v2 snooping Ipv4 support for multicast packet filtering. • IPv4/IPv6 QoS support. • Support unknown unicast/multicast address and unknown VID packet filtering. • Self-address filtering. Comprehensive Configuration Register Access • Serial management interface MDC/MDIO to all PHYs registers and SMI interface MDC/MDIO to all registers. • High speed SPI up to 25MHz and I2C master Interface to all internal registers. • I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode. • Control registers configurable on the fly port-priority, 802.1p/d/q, AN . QoS/CoS Packet Prioritization Support • Per port, 802.1p and DiffServ-based. • 1/2/4-queue QoS prioritization selection. • Programmable weighted fair queuing for ratio control. • Re-mapping of 802.1p priority field per port basis. Integrated Five-Port 10/100 Ethernet Switch • New generation switch with five MACs and five PHYs with fully compliant with IEEE 802.3u standard. • PHYs designed with patented enhanced mixed-signal technology. • Non-blocking switch fabric assures fast packet delivery by utilizing a 1K MAC address lookup table and a store-andforward architecture. KSZ8895MQ/RQ/FMQ • On-chip 64Kbyte memory for frame buffering not shared with 1K unicast address table . • Full duplex IEEE 802.3x flow control PAUSE with force mode option. Ordering Information Temperature Range KSZ8895MQ 0°C to 70°C KSZ8895MQI −40°C to +85°C KSZ8895RQ 0°C to 70°C KSZ8895RQI −40°C to +85°C KSZ8895FMQ 0°C to 70°C KSZ8895FMQI −40°C to +85°C KSZ8895MQ-EVAL KSZ8895RQ-EVAL KSZ8895FMQ-Eval Note Please consult sales for the availability Date 09/13/10 11/16/10 01/20/11 03/18/11 08/30/11 02/24/12 11/28/12 03/12/14 Package Lead Finish/Grade 128-Pin PQFP Pb-Free/Commercial 128-Pin PQFP Pb-Free/Industrial 128-Pin PQFP Pb-Free/Commercial 128-Pin PQFP Pb-Free/Industrial 128-Pin PQFP Pb-Free/Commercial 128-Pin PQFP Pb-Free/Industrial Evaluation Board for KSZ8895MQ Evaluation Board for KSZ8895RQ Evaluation Board for KSZ8895FMQ Initial document created Update the ordering information and some data. Update the register number, descriptions and correct typo error. Correct typo error for package information and update some descriptions for SMI mode and IGMP and update register default values, pins type and some parameters. Update descriptions for Pin, register 1 chip ID, port register, VLAN table and I2C master. Update the equation in the broadcast storm protection section. Update table of strap-in pins. Update the ordering information for RQ parts. Update the ordering information for FMQ parts available. Correct typos. Update the operation rating to ±5% and TTL min/max I/O voltage in different VDDIO. Add register 165 for FMQ part with fiber mode. Update a note for pin 125 descriptions. Change I/O from TTL to CMOS. Update SPI description from 127 to 255 for access registers. Update Register 6 offset. Update register offset mapping index. Correct typos. Updates timing data for MII PHY mode. Update the table of tail tag rules. Update description for Register 1 bits Update Table 8 from bit [57:55] to bit Update the port register control 2 bit [6] description bits [20:16] change to bits Update Table Add evaluation Board in ordering information table. Update a note for pin 126 descriptions. March 12, 2014 Micrel, Inc. KSZ8895MQ/RQ/FMQ Contents System Level Pin Configuration Pin Description Pin for Strap-In Introduction Functional Overview Physical Layer Transceiver 100BASE-TX Transmit 100BASE-TX Receive PLL Clock Scrambler/Descrambler 100BASE-TX only 100BASE-FX 100BASE-FX Signal Detection 100BASE-FX Far End 10BASE-T 10BASE-T Receive MDI/MDI-X Auto Crossover Straight Cable Crossover Cable Auto-Negotiation On-Chip Termination Resistors Internal 1.2V LDO Controller Functional Overview Power Management Normal Operation Mode Energy Detect Mode Soft Power Down Mode Power Saving Port-based Power Down Functional Overview Switch Core Address Look-Up Learning Migration Aging Forwarding Switching Engine Media Access Controller MAC Operation Inter-Packet Gap IPG Backoff Late Collision Illegal Frames Flow Half-Duplex Back Pressure Broadcast Storm MII Interface Operation March 12, 2014 Micrel, Inc. KSZ8895MQ/RQ/FMQ Port 5 PHY 5 P5-MII/RMII Port 5 MAC 5 SW5-MII Interface for the KSZ8895MQ/FMQ Port 5 MAC 5 Switch SW5-RMII Interface for the KSZ8895RQ SNI Interface Operation Advanced QoS Priority Support Port-Based 802.1p-Based Priority DiffServ-Based Priority Spanning Tree Rapid Spanning Tree Support Tail Tagging Mode IGMP Support Port Mirroring Support VLAN Support Rate Limiting Support Ingress Rate Egress Rate Limit Transmit Queue Ratio Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast Configuration Interface I2C Master Serial Bus Configuration SPI Slave Serial Bus Configuration MII Management Interface MIIM Serial Management Interface Register Description Global Registers Register 0 0x00 Chip ID0 Register 1 0x01 Chip ID1 / Start Register 2 0x02 Global Control 0 Register 3 0x03 Global Control 1 Register 4 0x04 Global Control 2 Register 5 0x05 Global Control 3 Register 6 0x06 Global Control 4 Register 7 0x07 Global Control 5 Register 8 0x08 Global Control 6 Register 9 0x09 Global Control 7 Register 10 0x0A Global Control Register 11 0x0B Global Control Register 12 0x0C Global Control 10 Register 13 0x0D Global Control 11 Register 14 0x0E Power Down Management Control 1 Register 15 0x0F Power Down Management Control March 12, 2014 Micrel, Inc. KSZ8895MQ/RQ/FMQ Port Registers Register 16 0x10 Port 1 Control Register 32 0x20 Port 2 Control Register 48 0x30 Port 3 Control Register 64 0x40 Port 4 Control Register 80 0x50 Port 5 Control Register 17 0x11 Port 1 Control Register 33 0x21 Port 2 Control Register 49 0x31 Port 3 Control Register 65 0x41 Port 4 Control Register 81 0x51 Port 5 Control Register 18 0x12 Port 1 Control Register 34 0x22 Port 2 Control Register 50 0x32 Port 3 Control Register 66 0x42 Port 4 Control Register 82 0x52 Port 5 Control Register 19 0x13 Port 1 Control Register 35 0x23 Port 2 Control Register 51 0x33 Port 3 Control Register 67 0x43 Port 4 Control Register 83 0x53 Port 5 Control Register 20 0x14 Port 1 Control Register 36 0x24 Port 2 Control Register 52 0x34 Port 3 Control Register 68 0x44 Port 4 Control Register 84 0x54 Port 5 Control Register 87 0x57 RMII Management Control Register 25 0x19 Port 1 Status 0 Register 41 0x29 Port 2 Status 0 Register 57 0x39 Port 3 Status 0 Register 73 0x49 Port 4 Status 0 Register 89 0x59 Port 5 Status 0 Register 26 0x1A Port 1 PHY Special Register 42 0x2A Port 2 PHY Special Register 58 0x3A Port 3 PHY Special Register 74 0x4A Port 4 PHY Special Register 90 0x5A Port 5 PHY Special Register 27 0x1B Reserved Register 43 0x2B Reserved Register 59 0x3B Reserved Register 75 0x4B Reserved Register 91 0x5B Reserved Register 28 0x1C Port 1 Control 5 Register 44 0x2C Port 2 Control 5 March 12, 2014 Micrel, Inc. KSZ8895MQ/RQ/FMQ Register 60 0x3C Port 3 Control 5 Register 76 0x4C Port 4 Control 5 Register 92 0x5C Port 5 Control 5 Register 29 0x1D Port 1 Control 6 Register 45 0x2D Port 2 Control 6 Register 61 0x3D Port 3 Control 6 Register 77 0x4D Port 4 Control 6 Register 93 0x5D Port 5 Control 6 Register 30 0x1E Port 1 Status Register 46 0x2E Port 2 Status Register 62 0x3E Port 3 Status Register 78 0x4E Port 4 Status Register 94 0x5E Port 5 Status Register 31 0x1F Port 1 Control 7 and Status 2 Register 47 0x2F Port 2 Control 7 and Status 2 Register 63 0x3F Port 3 Control 7 and Status 2 Register 79 0x4F Port 4 Control 7 and Status 2 Register 95 0x5F Port 5 Control 7 and Status 2 Advanced Control Registers Register 104 0x68 MAC Address Register 0 Register 105 0x69 MAC Address Register 1 Register 106 0x6A MAC Address Register 107 0x6B MAC Address Register 108 0x6C MAC Address Register 109 0X6D MAC Address Register 5 Register 110 0x6E Indirect Access Control 0 Register 111 0x6F Indirect Access Control Register 112 0x70 Indirect Data Register 8 Register 113 0x71 Indirect Data Register 7 Register 114 0x72 Indirect Data Register 6 Register 115 0x73 Indirect Data Register 5 Register 116 0x74 Indirect Data Register 4 Register 117 0x75 Indirect Data Register 3 Register 118 0x76 Indirect Data Register 2 Register 119 0x77 Indirect Data Register 1 Register 120 0x78 Indirect Data Register 0 Register 124 0x7C Interrupt Status Register 125 0x7D Interrupt Mask Register 128 0x80 Global Control 12 Register 129 0x81 Global Control 13 Register 130 0x82 Global Control 14 Register 131 0x83 Global Control 15 Register 132 0x84 Global Control 16 Register 133 0x85 Global Control 17 March 12, 2014 Micrel, Inc. KSZ8895MQ/RQ/FMQ Register 134 0x86 Global Control 18 Register 135 0x87 Global Control 19 Register 144 0x90 TOS Priority Control Register 0 Register 145 0x91 TOS Priority Control Register 1 Register 146 0x92 TOS Priority Control Register 2 Register 147 0x93 TOS Priority Control Register 3 Register 148 0x94 TOS Priority Control Register 4 Register 149 0x95 TOS Priority Control Register 5 Register 150 0x96 TOS Priority Control Register 6 Register 151 0x97 TOS Priority Control Register 7 Register 152 0x98 TOS Priority Control Register 8 Register 153 0x99 TOS Priority Control Register 9 Register 154 0x9A TOS Priority Control Register 155 0x9B TOS Priority Control Register 156 0x9C TOS Priority Control Register 157 0x9D TOS Priority Control Register 158 0x9E TOS Priority Control Register 159 0x9F TOS Priority Control Register 15 Register 165 0xA5 Fiber Control Register 176 0xB0 Port 1 Control 8 Register 192 0xC0 Port 2 Control 8 Register 208 0xD0 Port 3 Control 8 Register 224 0xE0 Port 4 Control 8 Register 240 0xF0 Port 5 Control Register 177 0xB1 Port 1 Control 9 Register 193 0xC1 Port 2 Control 9 Register 209 0xD1 Port 3 Control 9 Register 225 0xE1 Port 4 Control 9 Register 241 0xF1 Port 5 Control Register 178 0xB2 Port 1 Control 10 Register 194 0xC2 Port 2 Control 10 Register 210 0xD2 Port 3 Control 10 Register 226 0xE2 Port 4 Control 10 Register 242 0xF2 Port 5 Control Register 179 0xB3 Port 1 Control 11 Register 195 0xC3 Port 2 Control 11 Register 211 0xD3 Port 3 Control 11 Register 227 0xE3 Port 4 Control 11 Register 243 0xF3 Port 5 Control Register 180 0xB4 Port 1 Control 12 Register 196 0xC4 Port 2 Control 12 Register 212 0xD4 Port 3 Control 12 Register 228 0xE4 Port 4 Control 12 Register 244 0xF4 Port 5 Control March 12, 2014 Micrel, Inc. KSZ8895MQ/RQ/FMQ Register 181 0xB5 Port 1 Control 13 Register 197 0xC5 Port 2 Control 13 Register 213 0xD5 Port 3 Control 13 Register 229 0xE5 Port 4 Control 13 Register 245 0xF5 Port 5 Control Register 182 0xB6 Port 1 Rate Limit Control Register 198 0xC6 Port 2 Rate Limit Control Register 214 0xD6 Port 3 Rate Limit Control Register 230 0xE6 Port 4 Rate Limit Control Register 246 0xF6 Port 5 Rate Limit Control Register 183 0xB7 Port 1 Priority 0 Ingress Limit Control Register 199 0xC7 Port 2 Priority 0 Ingress Limit Control 1 Register 215 0xD7 Port 3 Priority 0 Ingress Limit Control 1 Register 231 0xE7 Port 4 Priority 0 Ingress Limit Control Register 247 0xF7 Port 5 Priority 0 Ingress Limit Control Register 184 0xB8 Port 1 Priority 1 Ingress Limit Control Register 200 0xC8 Port 2 Priority 1 Ingress Limit Control 2 Register 216 0xD8 Port 3 Priority 1 Ingress Limit Control 2 Register 232 0xE8 Port 4 Priority 1 Ingress Limit Control Register 248 0xF8 Port 5 Priority 1 Ingress Limit Control Register 185 0xB9 Port 1 Priority 2 Ingress Limit Control Register 201 0xC9 Port 2 Priority 2 Ingress Limit Control 3 Register 217 0xD9 Port 3 Priority 2 Ingress Limit Control 3 Register 233 0xE9 Port 4 Priority 2 Ingress Limit Control Register 249 0xF9 Port 5 Priority 2 Ingress Limit Control Register 186 0xBA Port 1 Priority 3 Ingress Limit Control 4 Register 202 0xCA Port 2 Priority 3 Ingress Limit Control 4 Register 218 0xDA Port 3 Priority 3 Ingress Limit Control 4 Register 234 0xEA Port 4 Priority 3 Ingress Limit Control 4 Register 250 0xFA Port 5 Priority 3 Ingress Limit Control 4 Register 187 0xBB Port 1 Queue 0 Egress Limit Control 1 Register 203 0xCB Port 2 Queue 0 Egress Limit Control 1 Register 219 0xDB Port 3 Queue 0 Egress Limit Control 1 Register 235 0xEB Port 4 Queue 0 Egress Limit Control 1 Register 251 0xFB Port 5 Queue 0 Egress Limit Control 1 Register 188 0xBC Port 1 Queue 1 Egress Limit Control 2 Register 204 0xCC Port 2 Queue 1 Egress Limit Control Register 220 0xDC Port 3 Queue 1 Egress Limit Control Register 236 0xEC Port 4 Queue 1 Egress Limit Control 2 Register 252 0xFC Port 5 Queue 1 Egress Limit Control 2 Register 189 0xBD Port 1 Queue 2 Egress Limit Control 3 Register 205 0xCD Port 2 Queue 2 Egress Limit Control Register 221 0xDD Port 3 Queue 2 Egress Limit Control Register 237 0xED Port 4 Queue 2 Egress Limit Control 3 March 12, 2014 Micrel, Inc. KSZ8895MQ/RQ/FMQ Register 253 0xFD Port 5 Queue 2 Egress Limit Control 3 Register 190 0xBE Port 1 Queue 3 Egress Limit Control 4 Register 206 0xCE Port 2 Queue 3 Egress Limit Control 4 Register 222 0xDE Port 3 Queue 3 Egress Limit Control 4 Register 238 0xEE Port 4 Queue 3 Egress Limit Control 4 Register 254 0xFE Port 5 Queue 3 Egress Limit Control 4 Data Rate Selection Table in 100BT Data Rate Selection Table in 10BT Register 191 0xBF Testing Register 207 0xCF Reserved Control Register 223 0xDF Test Register 239 0xEF Test Register 3 Register 255 0xFF Testing Register4 Static MAC Address Table VLAN Table Dynamic MAC Address Table MIB Management Information Base Counters MIIM Registers Register 0h MII Control Register 1h MII Status Register 2h PHYID HIGH Register 3h PHYID LOW Register 4h Advertisement Register 5h Link Partner Ability Register 1dh Reserved Register 1fh PHY Special Control/Status Absolute Maximum Ratings Operating Ratings Electrical Characteristics Timing Diagrams EEPROM SNI Timing MII Timing RMII SPI Timing Auto-Negotiation Timing MDC/MDIO Reset Circuit Selection of Isolation Selection of Reference Crystal Package Information 1 March 12, 2014 Micrel, Inc. KSZ8895MQ/RQ/FMQ List of Figures Figure Broadband Gateway 13 Figure Integrated Broadband Router 13 Figure Standalone Switch 14 Figure Using KSZ8895FMQ for Dual Media Converter 14 Figure KSZ8895MQ/RQ/FMQ 128-Pin PQFP Pins Configuration 15 Figure Typical Straight Cable Connection 28 Figure Typical Crossover Cable Connection 29 Figure Auto-Negotiation 30 Figure Destination Address Lookup Flow Chart, Stage 1 35 Figure Destination Address Resolution Flow Chart, Stage 36 Figure 802.1p Priority Field 42 Figure Tail Tag Frame Format 45 Figure KSZ8895MQ/RQ/FMQ EEPROM Configuration Timing Diagram 49 Figure SPI Write Data Cycle 50 Figure SPI Read Data Cycle 50 Figure SPI Multiple Write 51 Figure SPI Multiple Read 51 Figure EEPROM Interface Input Receive Timing 106 Figure EEPROM Interface Output Transmit Timing Diagram 106 Figure SNI Input Timing 107 Figure SNI Output Timing 107 Figure MAC Mode MII Timing Data Received from MII 108 Figure MAC Mode MII Timing Data Transmitted from MII 108 Figure PHY Mode MII Timing Data Received from 109 Figure PHY Mode MII Timing Data Transmitted from 109 Figure RMII Timing Data Received from RMII 110 Figure RMII Timing Data Transmitted to RMII 110 Figure SPI Input Timing 111 Figure SPI Output 112 Figure Auto-Negotiation Timing 113 Figure MDC/MDIO 114 Figure Reset Timing 115 Figure Recommended Reset Circuit 116 Figure Recommended Circuit for Interfacing with CPU/FPGA 116 March 12, 2014 Micrel, Inc. KSZ8895MQ/RQ/FMQ |
| More datasheets: MIKROE-2296 | MPC9351FA | MDM-37PSP | KSZ8895MQ-EVAL | KSZ8895FMQI TR | KSZ8895MQI | KSZ8895FMQ TR | KSZ8895RQ | KSZ8895FMQ | KSZ8895FMQI |
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