KSZ8864RMNU
KSZ8864RMNU Datasheet
KSZ8864RMN
| Part | Datasheet |
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KSZ8864RMNU |
KSZ8864RMNU (pdf) |
| Related Parts | Information |
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KSZ8864RMN-EVAL |
KSZ8864RMN-EVAL |
KSZ8864RMN |
KSZ8864RMN |
KSZ8864RMNI |
KSZ8864RMNI |
KSZ8864RMNU-TR |
KSZ8864RMNU-TR |
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| KSZ8864RMN Integrated 4-Port 10/100 Managed Switch with Two MACs MII or RMII Interfaces The KSZ8864RMN is a highly-integrated, Layer 2 managed 4-port switch with optimized design, plentiful features and smallest package size. It is designed for costsensitive 10/100Mbps 4-port switch systems with on-chip termination, lowest-power consumption, and small package to save system cost. It has 1.4Gbps highperformance memory bandwidth, shared memory-based switch fabric with full non-blocking configuration. It also provides an extensive feature set such as the power management, programmable rate limiting and priority ratio, tag/port-based VLAN, packet filtering, quality of service QoS , four queue prioritization, management interface, MIB counters. Port 3 and Port 4 support either MII or RMII interfaces with SW3-MII/RMII and SW4-MII/RMII see Functional Diagram for KSZ8864RMN data interface. An industrial temperature-grade version of the KSZ8864RMNI and a qualified AEC-Q100 Automotive version of the KSZ8864RMNU are also available see the Ordering Information section .The KSZ8864RMN provides multiple CPU control/data interfaces to effectively address both current and emerging fast Ethernet applications. The KSZ8864RMN consists of 10/100 fast Ethernet PHYs with patented and enhanced mixed-signal technology, media access control MAC units, a high-speed nonblocking switch fabric, a dedicated address lookup engine, and an on-chip frame buffer memory. The KSZ8864RMN contains four MACs and two PHYs. The two PHYs support the 10/100Base-T/TX. All registers of MACs and PHYs units can be managed by the control interface of SPI or the SMI. MIIM registers of the PHYs can be accessed through the MDC/MDIO interface. EEPROM can set all control registers by I2C controller interface for the unmanaged mode. Datasheets and support documentation can be found on Micrel’s website at: Functional Diagram Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 408 944-0800 • fax + 1 408 474-1000 • March 26, 2015 Micrel, Inc. Advanced Switch Features • IEEE 802.1q VLAN support for up to 128 VLAN groups full-range 4096 of VLAN IDs . • Static MAC table supports up to 32 entries. • VLAN ID tag/untag options, per port basis. • IEEE 802.1p/q tag insertion or removal on a per port basis based on ingress port egress . • Programmable rate limiting at the ingress and egress on a per port basis. • Jitter-free per packet based rate limiting support. • Broadcast storm protection with percentage control global and per port basis . • IEEE 802.1d rapid spanning tree protocol RSTP support. • Tail tag mode 1 byte added before FCS support at Port 4 to inform the processor which ingress port receives the packet. • 1.4Gbps high-performance memory bandwidth and shared memory based switch fabric with fully nonblocking configuration. • Dual MII/RMII with MAC 3 SW3-MII/RMII and MAC 4 SW4-MII/RMII interfaces. • Enable/Disable option for huge frame size up to 2000 Bytes per frame. • IGMP v1/v2 snooping Ipv4 support for multicast packet filtering. • IPv4/IPv6 QoS support. • Support unknown unicast/multicast address and unknown VID packet filtering. • Self-address filtering. Comprehensive Configuration Register Access • Serial management interface MDC/MDIO to all PHYs registers and SMI interface MDC/MDIO to all registers. • High-speed SPI up to 25MHz and I2C master Interface to all internal registers. • I/0 pins strapping and EEPROM to program selective registers in unmanaged switch mode. • Control registers configurable on-the-fly port-priority, 802.1p/d/q, QoS/CoS Packet Prioritization Support • Per port, 802.1p and DiffServ-based. • 1/2/4-queue QoS prioritization selection. • Programmable weighted fair queuing for ratio control. • Re-mapping of 802.1p priority field per port basis. KSZ8864RMN Integrated 4-Port 10/100 Ethernet Switch • New generation switch with five MACs and five PHYs that are fully compliant with the IEEE 802.3u standard. • Non-blocking switch fabric assures fast packet delivery by utilizing an 1K MAC address lookup table and a store-and-forward architecture. • On-chip 64Kbyte memory for frame buffering not shared with 1K unicast address table . • Full-duplex IEEE 802.3x flow control PAUSE with force mode option. • Half-duplex back pressure flow control. • HP Auto MDI/MDI-X and IEEE Auto crossover support. • MII interface of MAC supports both MAC mode and PHY mode. • Per port LED Indicators for link, activity, and 10/100 speed. • Register port status support for link, activity, full/half duplex and 10/100 speed. • On-chip terminations and internal biasing technology for cost down and lowest power consumption. Switch Monitoring Features • Port mirroring/monitoring/sniffing ingress and/or egress traffic to any port or MII/RMII. • MIB counters for fully-compliant statistics gathering 34 MIB counters per port. • Loop-back support for MAC, PHY and remote diagnostic of failure. • Interrupt for the link change on any ports. Low-Power Dissipation • Full-chip software power-down and per port software Ordering Information Part Number KSZ8864RMN KSZ8864RMNI KSZ8864RMNU Automotive AEC-Q100 Qualified Temperature Range 0°C to 70°C −40°C to +85°C −40°C to +85°C Package 64-Pin QFN 64-Pin QFN 64-Pin QFN Lead Finish/Grade Pb-Free/Commercial Pb-Free/Industrial Pb-Free/Automotive Date 10/29/10 12/16/10 01/20/11 03/18/11 09/19/11 02/21/12 03/26/15 Initial document created. Correct typo issue and others. Update ordering information and junction thermal data. Update the registers numbers, descriptions and typo error. Update descriptions for VLAN table and I2C master. Update the equation in broadcast storm protection section. Add KSZ8864RMNU automotive part in the ordering information table. Update the status register name and register bits description. Update the SPI access registers range from 127 to Update the operation rating to Update TTL to CMOS and Min/Max I/O voltage in different VDDIO. Correct typo. Update the table of tail tag rules. Update table 6 from bit [57:55] to bit Update description of the port register control 2 bit [6] from bits [20:16] to bits Update description of the port register control 6 bit [1] and the port register status 1 bit Update description for the port register control 9 bit Update pin function for pin 47 SCONF1 in the pin description. Update data in table Update package information. March 26, 2015 Micrel, Inc. KSZ8864RMN Contents Features 2 Pin 9 Pin Description 10 Pin for Strap-In 16 19 Functional Overview Physical Layer Transceiver 19 100BASE-TX Transmit 19 100BASE-TX Receive 19 PLL Clock 19 Scrambler/De-Scrambler 100BASE-TX 19 10BASE-T Transmit 20 10BASE-T Receive 20 MDI/MDI-X Auto Crossover 20 Auto-Negotiation 22 On-Chip Termination Resistors 24 Functional Overview Power Management 24 Normal Operation Mode 24 Energy Detect Mode 24 Soft Power-Down Mode 25 Power Saving 25 Port-Based Power-Down Mode 25 Functional Overview Switch Core 25 Address Look-Up 25 Learning 25 Migration 25 Aging 25 Forwarding 26 Switching Engine 26 Media Access Controller MAC Operation 26 Inter-Packet Gap IPG 26 Backoff 26 Late Collision 26 Illegal Frames 26 Flow 26 Half-Duplex Back 29 March 26, 2015 Micrel, Inc. KSZ8864RMN Broadcast Storm Protection 29 MII Interface Operation 29 Switch MAC3/MAC4 SW3/SW4-MII Interface 29 Switch MAC3/MAC4 SW3/SW4-RMII 31 Advanced Functionality 33 Spanning Tree 34 Rapid Spanning Tree Support 35 Tail Tagging Mode 36 IGMP Support 37 Port Mirroring Support 37 VLAN Support 37 Rate Limiting Support 38 Ingress Rate Limit 38 Egress Rate 39 Transmit Queue Ratio Programming 39 Filtering for Self-Address, Unknown Unicast/Multicast Address and Unknown VID Packet/IP Multicast 39 Configuration Interface 39 SPI Slave Serial Bus Configuration 40 MII Management Interface MIIM 43 Serial Management Interface SMI 43 Register Description 45 Global Registers 46 Port Registers 56 Advanced Control Registers 65 Data Rate Selection Table in 100BT 80 Data Rate Selection Table in 10BT 81 Static MAC Address Table 83 VLAN Table 86 Dynamic MAC Address Table 89 MIB Management Information Base Counters 91 For Port 1 91 All Ports Dropped Packet MIB 92 Format of “All Dropped Packet” MMIB Counter 92 MIIM Registers 94 Absolute Maximum Ratings 98 Operating Ratings 98 Electrical Characteristics 98 March 26, 2015 Micrel, Inc. KSZ8864RMN Timing Diagrams 100 EEPROM 100 MII Timing 101 RMII 103 SPI Timing 104 Auto-Negotiation Timing 106 MDC/MDIO 107 Reset Timing 108 Selection of Isolation Transformer 110 Selection of Transformer Venders 110 Selection of Reference Crystal 110 Package Information 111 March 26, 2015 Micrel, Inc. KSZ8864RMN List of Figures Figure Typical Straight Cable Connection 21 Figure Typical Crossover Cable Connection 22 Figure Auto-Negotiation 23 Figure Destination Address Lookup Flow Chart − Stage 1 27 Figure Destination Address Resolution Flow Chart − Stage 28 Figure 802.1p Priority Field Format 34 Figure Tail-Tag Frame Format 36 Figure KSZ8864RMN EEPROM Configuration Timing Diagram 40 Figure SPI Write Data Cycle 41 Figure SPI Read Data Cycle 41 Figure SPI Multiple Write 42 Figure SPI Multiple Read 42 Figure EEPROM Interface Input Receive Timing 100 Figure EEPROM Interface Output Transmit Timing 100 Figure MAC Mode MII Timing − Data Received from MII 101 Figure MAC Mode MII Timing − Data Transmitted from MII 101 Figure PHY Mode MII Timing − Data Received from 102 Figure PHY Mode MII Timing − Data Transmitted from 102 Figure RMII Timing − Data Received from RMII 103 Figure RMII Timing − Data Transmitted to RMII 103 Figure SPI Input Timing 104 Figure SPI Output 105 Figure Auto-Negotiation Timing 106 Figure MDC/MDIO 107 Figure Reset 108 Figure Recommended Reset Circuit 109 Figure Recommended Circuit for Interfacing with CPU/FPGA 109 March 26, 2015 Micrel, Inc. KSZ8864RMN List of Tables Table MDI/MDI-X Pin Definitions 20 Table Internal Function Block Status 24 Table Switch MAC 3 SW3-MII and MAC 4 SW4-MII Signals 30 Table MAC3 SW3-RMII and MAC4 SW4-RMII Connection 32 Table Tail Tag Rules 36 Table FID+DA Look-Up in the VLAN Mode 38 Table FID+SA Look-Up in the VLAN Mode 38 Table SPI Connections 41 Table MII Management Interface Frame Format 43 Table Serial Management Interface SMI Frame Format 43 Table 100BT Rate Selection for the Rate 80 Table 10BT Rate Selection for the Rate 81 Table Format of Static MAC Table for Reads 83 Table Format of Static MAC Table for Writes 84 Table VLAN Table 86 Table VLAN ID and Indirect Registers 88 Table Dynamic MAC Address Table 89 Table EEPROM Timing Parameters 100 Table MAC Mode MII Timing 101 Table PHY Mode MII Timing Parameters 102 Table RMII Timing Parameters 103 Table SPI Input Timing 104 Table SPI Output Timing Parameters 105 Table Auto-Negotiation Timing 106 Table MDC/MDIO Typical Timing 107 Table Reset Timing Parameters 108 Table Transformer Selection Criteria 110 Table Qualified Magnetic Vendors 110 Table Typical Reference Crystal Characteristics 110 March 26, 2015 Micrel, Inc. Pin Configuration KSZ8864RMN 64-Pin QFN March 26, 2015 Micrel, Inc. KSZ8864RMN |
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