KSZ8051MNLI-TR

KSZ8051MNLI-TR Datasheet

KSZ8051MNL/RNL

Part	Datasheet
KSZ8051MNLI-TR	KSZ8051MNLI-TR (pdf)

Related Parts	Information
KSZ8051RNL	KSZ8051RNL
KSZ8051RNL-TR	KSZ8051RNL-TR
KSZ8051MNL	KSZ8051MNL
KSZ8051MNL-TR	KSZ8051MNL-TR
KSZ8051MNLI	KSZ8051MNLI
KSZ8051MNL-EVAL	KSZ8051MNL-EVAL

PDF Datasheet Preview
KSZ8051MNL/RNL 10Base-T/100Base-TX Physical Layer Transceiver The KSZ8051 is a single supply 10Base-T/100Base-TX Ethernet physical layer transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair UTP cable. The KSZ8051 is a highly integrated, compact solution. It reduces board cost and simplifies board layout by using on-chip termination resistors for the differential pairs and by integrating a low noise regulator to supply the 1.2V core. The KSZ8051MNL offers the Media Independent Interface MII and the KSZ8051RNL offers the Reduced Media Independent Interface RMII for direct connection with MII/ RMII compliant Ethernet MAC processors and switches. • Single-chip 10Base-T/100Base-TX IEEE compliant Ethernet Transceiver • MII Interface support KSZ8051MNL • RMII v1.2 Interface support with 50MHz reference clock output to MAC, and option to input 50MHz reference clock KSZ8051RNL • Back-to-Back mode support for 100Mbps copper repeater or media converter • MDC/MDIO Management Interface for PHY register configuration • Programmable interrupt output • LED outputs for link, activity and speed status indication A 25MHz crystal is used to generate all required clocks, including the 50MHz RMII reference clock output for the KSZ8051RNL. The KSZ8051 provides diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ8051 I/Os and board. Micrel TDR-based cable diagnostics permit identification of faulty copper cabling. The KSZ8051MNL and KSZ8051RNL are available in 32pin, lead-free QFN packages See Ordering Information . Data sheets and support documentation can be found on Micrel’s web site at: • On-chip termination resistors for the differential pairs • Baseline Wander Correction • HP Auto MDI/MDI-X for reliable detection and correction for straight-through and crossover cables with disable and enable option • Auto-negotiation to automatically select the highest link up speed 10/100 Mbps and duplex half/full • Power down and power saving modes • TDR-based cable diagnostics for identification of faulty copper cabling • Parametric NAND Tree support for fault detection between chip I/Os and board. Functional Diagram LinkMD is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 408 944-0800 • fax + 1 408 474-1000 • July 2010 M9999-070910-1.0 Micrel, Inc. More Features • Loopback modes for diagnostics • Single 3.3V power supply with VDD I/O options for 1.8V, 2.5V, or 3.3V • Built-in 1.2V regulator for core • Available in 32-pin 5mm x 5mm QFN package • Game Console • IP Phone • IP Set-top Box • IP TV • LOM • Printer KSZ8051MNL/RNL Ordering Information Temp. Range KSZ8051MNL KSZ8051MNLI 1 0°C to 70°C -40°C to 85°C KSZ8051RNL KSZ8051RNLI 1 0°C to 70°C -40°C to 85°C Note Contact factory for lead time. Package 32-Pin QFN 32-Pin QFN 32-Pin QFN 32-Pin QFN Lead Finish Pb-Free Pb-Free Pb-Free Pb-Free Description MII, Commercial Temperature MII, Industrial Temperature RMII, Commercial Temperature RMII, Industrial Temperature July 2010 M9999-070910-1.0 Micrel, Inc. 6/22/10 Summary of Changes Data sheet created. KSZ8051MNL/RNL July 2010 M9999-070910-1.0 Micrel, Inc. KSZ8051MNL/RNL Contents 100Base-TX 19 100Base-TX 19 10Base-T Transmit 19 10Base-T Receive 19 Scrambler/De-scrambler 100Base-TX 20 SQE and Jabber Function 10Base-T 20 PLL Clock 20 Auto-Negotiation 20 MII Data Interface KSZ8051MNL only 21 MII Signal 22 Transmit Clock TXC 22 Transmit Enable TXEN 22 Transmit Data [3:0] TXD[3:0] 22 Receive Clock 22 Receive Data Valid 22 Receive Data[3:0] RXD[3:0] 23 Receive Error RXER 23 Carrier Sense CRS 23 Collision COL 23 MII Signal Diagram 23 RMII Data Interface KSZ8051RNL only 24 RMII 25MHz Clock 24 RMII 50MHz Clock 24 RMII Signal Definition 24 Reference Clock REF_CLK 24 July 2010 M9999-070910-1.0 Micrel, Inc. KSZ8051MNL/RNL Transmit Enable TXEN 25 Transmit Data [1:0] TXD[1:0] 25 Carrier Sense/Receive Data Valid 25 Receive Data [1:0] RXD[1:0] 25 Receive Error RXER 25 Collision 25 RMII Signal 25 RMII 25MHz Clock 26 RMII 50MHz Clock 26 Back-to-Back Mode 100Mbps Copper Repeater / Media 27 MII Back-to-Back Mode KSZ8051MNL 27 RMII Back-to-Back Mode KSZ8051RNL only 28 MII Management MIIM 28 Interrupt INTRP 29 HP Auto MDI/MDI-X 29 Straight Cable 29 Crossover Cable 30 Cable 30 NAND Tree Support 30 NAND Tree I/O 32 Power Management 32 Power Saving 32 Energy Detect Power Down Mode 32 Power Down Mode 32 Slow Oscillator Mode 32 Reference Circuit for Power and Ground Connections 33 Register 34 Register Description 34 Register Description 35 Register Description 36 Register Description 37 Register Description 38 Register Description 39 Register Description 40 Register Description 41 Register Description 42 Register Description 43 Absolute Maximum Ratings 1 44 Operating Ratings 2 44 Electrical Characteristics 3 44 Electrical Characteristics 3 Continued 45 Timing Diagrams 46 MII SQE Timing 10Base-T 46 July 2010 M9999-070910-1.0 Micrel, Inc. KSZ8051MNL/RNL MII Transmit Timing 10Base-T 47 MII Receive Timing 10Base-T 48 MII Transmit Timing 100Base-TX 49 MII Receive Timing 100Base-TX 50 RMII 51 Auto-Negotiation Timing 52 MDC/MDIO Timing 53 Reset 54 Reset Circuit 55 Reference Circuits for LED Strapping 56 Magnetics Specification 57 Reference Clock Connection and 57 Package 59 July 2010 M9999-070910-1.0 Micrel, Inc. KSZ8051MNL/RNL List of Figures Figure Auto-Negotiation Flow 21 Figure KSZ8051MNL MII Interface 23 Figure KSZ8051RNL RMII Interface 25MHz Clock Mode 26 Figure KSZ8051RNL RMII Interface 50MHz Clock Mode 26 Figure KSZ8051MNL/RNL and KSZ8041FTL Back-to-Back Media Converter 27 Figure Typical Straight Cable Connection 29 Figure Typical Crossover Cable Connection 30 Figure KSZ8051MNL/RNL Power and Ground 33 Figure MII SQE Timing 10Base-T 46 Figure MII Transmit Timing 10Base-T 47 Figure MII Receive Timing 10Base-T 48 Figure MII Transmit Timing 49 Figure MII Receive Timing 50 Figure RMII Timing Data Received from RMII 51 Figure RMII Timing Data Input to RMII 51 Figure Auto-Negotiation Fast Link Pulse FLP Timing 52 Figure MDC/MDIO 53 Figure Reset 54 Figure Recommended Reset 55 Figure Recommended Reset Circuit for interfacing with CPU/FPGA Reset 55 Figure Reference Circuits for LED Strapping 56 Figure 25MHz Crystal / Oscillator Reference Clock Connection 57 Figure 50MHz Oscillator Reference Clock Connection 58 July 2010 M9999-070910-1.0 Micrel, Inc. KSZ8051MNL/RNL List of Tables Table MII Signal Definition 22 Table RMII Signal 24 Table MII Signal Connection for MII Back-to-Back Mode 100Base-TX Copper 27 Table RMII Signal Connection for RMII Back-to-Back Mode 100Base-TX Copper Repeater 28 Table MII Management Frame Format for KSZ8051MNL/RNL 28 Table MDI/MDI-X Pin Definition 29 Table NAND Tree Test Pin Order for KSZ8051MNL 31 Table NAND Tree Test Pin Order for KSZ8051RNL 31 Table KSZ8051MNL/RNL Power Pin 33 Table MII SQE Timing 10Base-T Parameters 46 Table MII Transmit Timing 10Base-T Parameters 47 Table MII Receive Timing 10Base-T Parameters 48 Table MII Transmit Timing 100Base-TX Parameters 49 Table MII Receive Timing 100Base-TX Parameters 50 Table RMII Timing Parameters KSZ8051RNL 25MHz input to XI pin, 50MHz output from REF_CLK pin .............. 51 Table RMII Timing Parameters KSZ8051RNL 50MHz input to XI 51 Table Auto-Negotiation Fast Link Pulse FLP Timing Parameters 52 Table MDC/MDIO Timing Parameters 53 Table Reset Timing Parameters 54 Table Magnetics Selection Criteria 57 Table Qualified Single Port 10/100 57 Table 25MHz Crystal / Reference Clock Selection Criteria 58 Table 50MHz Oscillator / Reference Clock Selection Criteria 58 July 2010 M9999-070910-1.0 Micrel, Inc. Pin Configuration KSZ8051MNL KSZ8051MNL/RNL 32-Pin 5mm x 5mm QFN July 2010 M9999-070910-1.0 Micrel, Inc. KSZ8051MNL/RNL Pin Description KSZ8051MNL Pin Number Pin Name Type 1 Pin Function Ground VDD_1.2 1.2V core VDD power supplied by KSZ8051MNL Decouple with 2.2uF and 0.1uF capacitors to ground.

PDF Datasheet Preview

KSZ8051MNL/RNL
10Base-T/100Base-TX Physical Layer Transceiver

The KSZ8051 is a single supply 10Base-T/100Base-TX Ethernet physical layer transceiver for transmission and reception of data over standard CAT-5 unshielded twisted pair UTP cable.

The KSZ8051 is a highly integrated, compact solution. It reduces board cost and simplifies board layout by using on-chip termination resistors for the differential pairs and by integrating a low noise regulator to supply the 1.2V core.

The KSZ8051MNL offers the Media Independent Interface MII and the KSZ8051RNL offers the Reduced Media Independent Interface RMII for direct connection with MII/ RMII compliant Ethernet MAC processors and switches.
• Single-chip 10Base-T/100Base-TX IEEE compliant Ethernet Transceiver
• MII Interface support KSZ8051MNL
• RMII v1.2 Interface support with 50MHz reference clock output to MAC, and option to input 50MHz reference clock KSZ8051RNL
• Back-to-Back mode support for 100Mbps copper repeater or media converter
• MDC/MDIO Management Interface for PHY register configuration
• Programmable interrupt output
• LED outputs for link, activity and speed status indication

A 25MHz crystal is used to generate all required clocks, including the 50MHz RMII reference clock output for the KSZ8051RNL.

The KSZ8051 provides diagnostic features to facilitate system bring-up and debugging in production testing and in product deployment. Parametric NAND tree support enables fault detection between KSZ8051 I/Os and board. Micrel TDR-based cable diagnostics permit identification of faulty copper cabling.
The KSZ8051MNL and KSZ8051RNL are available in 32pin, lead-free QFN packages See Ordering Information .

Data sheets and support documentation can be found on Micrel’s web site at:
• On-chip termination resistors for the differential pairs
• Baseline Wander Correction
• HP Auto MDI/MDI-X for reliable detection and correction for straight-through and crossover cables with disable and enable option
• Auto-negotiation to automatically select the highest link up speed 10/100 Mbps and duplex half/full
• Power down and power saving modes
• TDR-based cable diagnostics for identification
of faulty copper cabling
• Parametric NAND Tree support for fault detection between chip I/Os and board.

Functional Diagram

LinkMD is a registered trademark of Micrel, Inc.

Micrel Inc.
• 2180 Fortune Drive
• San Jose, CA 95131
• USA
• tel +1 408 944-0800
• fax + 1 408 474-1000
•

July 2010

M9999-070910-1.0

Micrel, Inc.

More Features
• Loopback modes for diagnostics
• Single 3.3V power supply with VDD I/O options for
1.8V, 2.5V, or 3.3V
• Built-in 1.2V regulator for core
• Available in 32-pin 5mm x 5mm QFN package
• Game Console
• IP Phone
• IP Set-top Box
• IP TV
• LOM
• Printer

KSZ8051MNL/RNL
Ordering Information

Temp. Range

KSZ8051MNL KSZ8051MNLI 1
0°C to 70°C -40°C to 85°C

KSZ8051RNL KSZ8051RNLI 1
0°C to 70°C -40°C to 85°C

Note Contact factory for lead time.

Package 32-Pin QFN 32-Pin QFN 32-Pin QFN 32-Pin QFN

Lead Finish Pb-Free Pb-Free Pb-Free Pb-Free

Description MII, Commercial Temperature MII, Industrial Temperature RMII, Commercial Temperature RMII, Industrial Temperature

July 2010

M9999-070910-1.0

Micrel, Inc.
6/22/10

Summary of Changes Data sheet created.

KSZ8051MNL/RNL

July 2010

M9999-070910-1.0

Micrel, Inc.

KSZ8051MNL/RNL

Contents
100Base-TX 19 100Base-TX 19 10Base-T Transmit 19 10Base-T Receive 19 Scrambler/De-scrambler 100Base-TX 20 SQE and Jabber Function 10Base-T 20 PLL Clock 20 Auto-Negotiation 20 MII Data Interface KSZ8051MNL only 21 MII Signal 22

Transmit Clock TXC 22 Transmit Enable TXEN 22 Transmit Data [3:0] TXD[3:0] 22 Receive Clock 22 Receive Data Valid 22 Receive Data[3:0] RXD[3:0] 23 Receive Error RXER 23 Carrier Sense CRS 23 Collision COL 23 MII Signal Diagram 23 RMII Data Interface KSZ8051RNL only 24 RMII 25MHz Clock 24 RMII 50MHz Clock 24 RMII Signal Definition 24 Reference Clock REF_CLK 24

July 2010

M9999-070910-1.0

Micrel, Inc.

KSZ8051MNL/RNL

Transmit Enable TXEN 25 Transmit Data [1:0] TXD[1:0] 25 Carrier Sense/Receive Data Valid 25 Receive Data [1:0] RXD[1:0] 25 Receive Error RXER 25 Collision 25 RMII Signal 25 RMII 25MHz Clock 26 RMII 50MHz Clock 26 Back-to-Back Mode 100Mbps Copper Repeater / Media 27 MII Back-to-Back Mode KSZ8051MNL 27 RMII Back-to-Back Mode KSZ8051RNL only 28 MII Management MIIM 28 Interrupt INTRP 29 HP Auto MDI/MDI-X 29 Straight Cable 29 Crossover Cable 30 Cable 30 NAND Tree Support 30 NAND Tree I/O 32 Power Management 32 Power Saving 32 Energy Detect Power Down Mode 32 Power Down Mode 32 Slow Oscillator Mode 32 Reference Circuit for Power and Ground Connections 33 Register 34 Register Description 34 Register Description 35 Register Description 36 Register Description 37 Register Description 38 Register Description 39 Register Description 40 Register Description 41 Register Description 42 Register Description 43 Absolute Maximum Ratings 1 44 Operating Ratings 2 44 Electrical Characteristics 3 44 Electrical Characteristics 3 Continued 45 Timing Diagrams 46 MII SQE Timing 10Base-T 46

July 2010

M9999-070910-1.0

Micrel, Inc.

KSZ8051MNL/RNL

MII Transmit Timing 10Base-T 47 MII Receive Timing 10Base-T 48 MII Transmit Timing 100Base-TX 49 MII Receive Timing 100Base-TX 50 RMII 51 Auto-Negotiation Timing 52 MDC/MDIO Timing 53 Reset 54 Reset Circuit 55 Reference Circuits for LED Strapping 56 Magnetics Specification 57 Reference Clock Connection and 57 Package 59

July 2010

M9999-070910-1.0

Micrel, Inc.

KSZ8051MNL/RNL

List of Figures

Figure Auto-Negotiation Flow 21 Figure KSZ8051MNL MII Interface 23 Figure KSZ8051RNL RMII Interface 25MHz Clock Mode 26 Figure KSZ8051RNL RMII Interface 50MHz Clock Mode 26 Figure KSZ8051MNL/RNL and KSZ8041FTL Back-to-Back Media Converter 27 Figure Typical Straight Cable Connection 29 Figure Typical Crossover Cable Connection 30 Figure KSZ8051MNL/RNL Power and Ground 33 Figure MII SQE Timing 10Base-T 46 Figure MII Transmit Timing 10Base-T 47 Figure MII Receive Timing 10Base-T 48 Figure MII Transmit Timing 49 Figure MII Receive Timing 50 Figure RMII Timing Data Received from RMII 51 Figure RMII Timing Data Input to RMII 51 Figure Auto-Negotiation Fast Link Pulse FLP Timing 52 Figure MDC/MDIO 53 Figure Reset 54 Figure Recommended Reset 55 Figure Recommended Reset Circuit for interfacing with CPU/FPGA Reset 55 Figure Reference Circuits for LED Strapping 56 Figure 25MHz Crystal / Oscillator Reference Clock Connection 57 Figure 50MHz Oscillator Reference Clock Connection 58

July 2010

M9999-070910-1.0

Micrel, Inc.

KSZ8051MNL/RNL

List of Tables

Table MII Signal Definition 22 Table RMII Signal 24 Table MII Signal Connection for MII Back-to-Back Mode 100Base-TX Copper 27 Table RMII Signal Connection for RMII Back-to-Back Mode 100Base-TX Copper Repeater 28 Table MII Management Frame Format for KSZ8051MNL/RNL 28 Table MDI/MDI-X Pin Definition 29 Table NAND Tree Test Pin Order for KSZ8051MNL 31 Table NAND Tree Test Pin Order for KSZ8051RNL 31 Table KSZ8051MNL/RNL Power Pin 33 Table MII SQE Timing 10Base-T Parameters 46 Table MII Transmit Timing 10Base-T Parameters 47 Table MII Receive Timing 10Base-T Parameters 48 Table MII Transmit Timing 100Base-TX Parameters 49 Table MII Receive Timing 100Base-TX Parameters 50 Table RMII Timing Parameters KSZ8051RNL 25MHz input to XI pin, 50MHz output from REF_CLK pin .............. 51 Table RMII Timing Parameters KSZ8051RNL 50MHz input to XI 51 Table Auto-Negotiation Fast Link Pulse FLP Timing Parameters 52 Table MDC/MDIO Timing Parameters 53 Table Reset Timing Parameters 54 Table Magnetics Selection Criteria 57 Table Qualified Single Port 10/100 57 Table 25MHz Crystal / Reference Clock Selection Criteria 58 Table 50MHz Oscillator / Reference Clock Selection Criteria 58

July 2010

M9999-070910-1.0

Micrel, Inc.

Pin Configuration KSZ8051MNL

KSZ8051MNL/RNL
32-Pin 5mm x 5mm QFN

July 2010

M9999-070910-1.0

Micrel, Inc.

KSZ8051MNL/RNL

Pin Description KSZ8051MNL

Pin Number Pin Name

Type 1 Pin Function

Ground

VDD_1.2
1.2V core VDD power supplied by KSZ8051MNL

Decouple with 2.2uF and 0.1uF capacitors to ground.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived KSZ8051MNLI-TR Datasheet file may be downloaded here without warranties.

Datasheet ID: KSZ8051MNLI-TR 647877