TS68040 Companion Mode Allows QUICC to be a TS68040 Companion Chip and
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TS68EN360VA25L (pdf) |
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TS68EN360VA33L |
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• CPU32+ Processor MIPS at 25 MHz 32-bit Version of the CPU32 Core Fully Compatible with the CPU32 Background Debug Mode Byte-misaligned Addressing • Up to 32-bit Data Bus Dynamic Bus Sizing for 8 and 16 Bits • Up to 32 Address Lines At Least 28 Always Available • Complete Static Design 0 - 25 MHz Operation • Slave Mode to Disable CPU32+ Allows Use with External Processors Multiple QUICCs Can Share One System Bus One Master TS68040 Companion Mode Allows QUICC to be a TS68040 Companion Chip and Intelligent Peripheral 22 MIPS at 25 MHz Peripheral Device of TSPC603e see DC415/D note • Four General-purpose Timers Superset of MC68302 Timers Four 16-bit Timers or Two 32-bit Timers Gate Mode Can Enable/Disable Counting • Two Independent DMAs IDMAs • System Integration Module SIM60 • Communications Processor Module CPM • Four Baud Rate Generators • Four SCCs Ethernet/IEEE Optional on SCC1-Full 10 Mbps Support • Two SMC • VCC = +5V ± 5% • fmax = 25 MHz and 33 MHz • Military Temperature Range -55°C < TC < +125°C • PD = W at 25 MHz 5.25V 2 W at 33 MHz 5.25V 32-bit Quad Integrated Communication Controller TS68EN360 The TS68EN360 QUad Integrated Communication Controller QUICC is a versatile one-chip integrated microprocessor and peripheral combination that can be used in a variety of controller applications. It particularly excels in communications activities. The QUICC pronounced “quick” can be described as a next-generation TS68302 with higher performance in all areas of device operation, increased flexibility, major extensions in capability, and higher integration. The term “quad” comes from the fact that there are four serial communications controllers SCCs on the device however, there are actually seven serial channels four SCCs, two serial management controllers SMCs , and one serial peripheral interface SPI . Screening/Quality This product is manufactured in full compliance with • MIL-STD-883 class B • QML class Q • or according to Atmel standards R suffix PGA 241 Ceramic Pin Grid Array Cavity Up A suffix CERQUAD 240 Ceramic Leaded Chip Carrier Cavity Down Introduction QUICC Architecture Overview The QUICC is 32-bit controller that is an extension of other members of the TS68300 family. Like other members of the TS68300 family, the QUICC incorporates the intermodule bus IMB . The TS68302 is an exception, having an 68000 bus on chip. The IMB provides a common interface for all modules of the TS68300 family, which allows the development of new devices more quickly by using the library of existing modules. Although the IMB definition always included an option for an on-chip 32-bit bus, the QUICC is the first device to implement this option. The QUICC is comprised of three modules the CPU32+ core, the SIM60, and the CPM. Each module utilizes the 32-bit IMB. The TS68EN360 QUICC block diagram is shown in Figure Figure QUICC Block Diagram CPU32+ CORE SIM 60 SYSTEM PROTECTION JTAG PERIODIC TIMER BREAKPOINT LOGIC CLOCK GENERATION OTHER FEATURES DRAM CONTROLLER AND CHIP SELECTS IMB 32 BIT EXTERNAL BUS INTERFACE SYSTEM I/F TWO IDMAs COMMUNICATIONS PROCESSOR RISC CONTROLLER FOURTEEN SERIAL DMAs 2.5-KBYTE DUAL-PORT Lead material and finish shall be as specified in MIL-STD-883 see enclosed “Ordering Information” on page Package The macrocircuits are packaged in hermetically sealed ceramic packages which are conform to case outlines of MIL-STD-1835 or as follow • PGA but see “241-pin PGA” on page 77 • CERQUAD The precise case outlines are described at the end of the specification “Package Mechanical Data” on page 77 and into MIL-STD-1835. Electrical Characteristics Table Absolute Maximum Ratings Rating Value Unit Supply Voltage 1 2 Input Voltage 1 2 Storage Temperature Range TSTG -55 to +150 Note This device contains protective circuitry against damage due to high static voltages or electrical fields however, it isadvised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-imped- ance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e.g., eithreGND or VDD . Notes Permanent damage can occur if maximum ratings are exceeded. Exposure to voltages or currents in excess of recom- mended values affects device reliability. Device modules may not operate normally while being exposed to electrical extremes. Although sections of the device contain circuitry to protect against damage from high static voltages or electrical fieldsa, kt e normal precautions to avoid exposure to voltages higher than maximum-rated voltages. The supply voltage VCC must start and restart from 0.0V otherwise, the 360 will not come out of reset properly.Unless otherwise stated, all voltages are referenced to the reference terminal. Table Recommended Conditions Of Use Unless otherwise stated, all voltages are referenced to the reference terminal. Symbol Parameter Min. VCC VIL VIH Tcase VOH fsys Supply Voltage Range Logic Low Level Input Voltage Range Logic High Level Input Voltage Range Operating Temperature High Level Output Voltage System Frequency For 25 MHz version For 33 MHz version GND -55 Typ. 25 33 Max. VCC +125 Unit V °C V Table Thermal Characteristics Symbol Parameter Thermal Resistance - Junction to Case Thermal Resistance - Junction to Ambient 240-pin Cerquad 241-pin PGA 240-pin Cerquad 241-pin PGA Ordering Information Hi-REL Product Commercial Atmel Part-Number TS68EN360MRB/C25L TS68EN360MRB/C33L TS68EN360MR1B/C25L TS68EN360MR1B/C33L TS68EN360MAB/C25L TS68EN360MAB/C33L TS68EN360DES01MXCL TS68EN360DES02MXCL TS68EN360DES01MXAL TS68EN360DES02MXAL TS68EN360DES01MYAL TS68EN360DES02MYAL Norms MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 MIL-STD-883 DSCC Package PGA 241 Gold PGA 241 Gold PGA 241 Tinned PGA 241 Tinned CERQUAD 240 CERQUAD 240 PGA 241 Gold PGA 241 Gold PGA 241 Tinned PGA 241 Tinned CERQUAD 240 CERQUAD 240 Temperature Range Tc °C -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 -55/+125 Frequency MHz 25 33 25 33 25 33 25 33 25 33 25 33 Drawing Number 5962-9760701MXC 5962-9760702MXC 5962-9760701MXA 5962-9760702MXA 5962-9760701MYA 5962-9760702MYA Standard Product Commercial Atmel Part-Number TS68EN360VR25L TS68EN360MR25L TS68EN360VA25L TS68EN360MA25L TS68EN360VR33L TS68EN360MR33L TS68EN360VA33L TS68EN360MA33L Norms Atmel Standard Atmel Standard Atmel Standard Atmel Standard Atmel Standard Atmel Standard Atmel Standard Atmel Standard Package PGA 241 PGA 241 CERQUAD 240 CERQUAD 240 PGA 241 PGA 241 CERQUAD 240 CERQUAD 240 Temperature Range Tc °C -40/+85 -55/+125 -40/+85 -55/+125 -40/+85 -55/+125 -40/+85 -55/+125 Frequency MHz 25 33 Drawing Number Internal TSX TS68EN360 M R 1 B/C 25 X Prototype version Generic Temperature range TC M -55°C, +125°C V -40°C, +110°C 0°C, +70°C R = Pin grid array 241 gold A = CERQUAD 240 tin Hirel lead finish _ = Gold for PGA _ = Hot solder dip for CERQUAD 1 = Hot solder dip for PGA - On request Operating frequency 25 MHz 33 MHz Screening = Standard B/C = MIL STD 883 Class B/T = According to MIL-STD883 D/T = Standard + Burn in 80 TS68EN360 TS68EN360 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL 1 408 441-0311 FAX 1 408 487-2600 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL 41 26-426-5555 FAX 41 26-426-5500 Asia Atmel Asia, Ltd. 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