ATSAMA5D35A-CUR

ATSAMA5D35A-CUR Datasheet


The use of undefined length16-beat bursts, or less, is discouraged since this generally decreases significantly the overall bus bandwidth due to arbitration and slave latencies at each first access of a burst. If the master does not permanently and continuously request the same slave or has an intrinsically limited average throughput, the ULBT should be left at its default unlimited value, knowing that the AHB specification natively limits all word bursts to 256 beats and double-word bursts to 128 beats because of its 1 Kbyte address boundaries. Unless duly needed, the ULBT should be left at its default value of 0 for power saving. This selection can be done through the ULBT field of the Master Configuration Registers MATRIX_MCFG .

Part Datasheet
ATSAMA5D35A-CUR ATSAMA5D35A-CUR ATSAMA5D35A-CUR (pdf)
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ARM-based Embedded MPU

SAMA5D3 Series

DATASHEET

The Atmel SAMA5D3 series is a high-performance, power-efficient embedded MPU based on the processor, achieving 536 MHz with power consumption levels below mW in low-power mode. The device features a floating point unit for high-precision computing and accelerated data processing, and a high data bandwidth architecture. It integrates advanced user interface and connectivity peripherals and security features. The SAMA5D3 series features an internal multi-layer bus architecture associated with 39 DMA channels to sustain the high bandwidth required by the processor and the high-speed peripherals. The device offers support for DDR2/LPDDR/LPDDR2 and MLC NAND Flash memory with 24-bit ECC. The comprehensive peripheral set includes an LCD controller with overlays for hardware-accelerated image composition, a touchscreen interface and a CMOS sensor interface. Connectivity peripherals include Gigabit EMAC with IEEE1588, 10/100 EMAC, multiple CAN, UART, SPI and I2C. With its secure boot mechanism, hardware accelerated engines for encryption AES, TDES and hash function SHA , the SAMA5D3 ensures anti-cloning, code protection and secure external data transfers. The SAMA5D3 series is optimized for control panel/HMI applications and applications that require high levels of connectivity in the industrial and consumer markets. Its lowpower consumption levels make the SAMA5D3 particularly suited for battery-powered devices. There are five SAMA5D3 devices in this series. Table 1-1 “SAMA5D3 Device Differences” shows the differences in the embedded features. All other features are available on all derivatives this includes the three USB ports as well as the encryption engine and secure boot features.

Core Processor with ARM v7-A Instruction Set CPU Frequency up to 536 MHz 32 Kbyte Data Cache, 32 Kbyte Instruction Cache, Virtual Memory System Architecture VMSA Fully Integrated MMU and Floating Point Unit VFPv4

Memories One 160 Kbyte Internal ROM Single-cycle Access at System Speed, Embedded Boot Loader Boot on 8-bit NAND Flash, SDCard, eMMC, serial selectable Order One 128 Kbyte Internal SRAM, Single-cycle Access at System Speed High Bandwidth 32-bit Multi-port Dynamic RAM Controller supporting 512 Mbyte 8 bank DDR2/LPDDR/LPDDR2 with datapath scrambling Independent Static Memory Controller with datapath scrambling and SLC/MLC NAND Support with up to 24-bit Error Correcting Code PMECC

System running up to 166 MHz Reset Controller, Shut Down Controller, Periodic Interval Timer, Watchdog Timer and Real-time Clock Boot Mode Select Option, Remap Command Internal Low-power 32 kHz RC Oscillator and Fast 12 MHz RC Oscillator Selectable 32768 Hz Low-power Oscillator and 12 MHz Oscillator One 400 to 1000 MHz PLL for the System and one PLL at 480 MHz optimized for USB High Speed 39 DMA Channels including two 8-channel 64-bit Central DMA Controllers 64-bit Advanced Interrupt Controller Three Programmable External Clock Signals Programmable Fuse Box with 256 fuse bits, 192 of them available for Customer

Low Power Management Shut Down Controller Battery Backup Registers Clock Generator and Power Management Controller Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities

Peripherals LCD TFT Controller with Overlay, Alpha-blending, Rotation, Scaling and Color Space Conversion ITU-R BT. 601/656 Image Sensor Interface Three HS/FS/LS USB Ports with On-Chip Transceivers One Device Controller One Host Controller with Integrated Root Hub 3 Downstream Ports One 10/100/1000 Mbps Gigabit Ethernet MAC Controller GMAC with IEEE1588 support One 10/100 Mbps Ethernet MAC Controller EMAC Two CAN Controllers with 8 Mailboxes, fully Compliant with CAN Part A and Part B Softmodem Interface Three High Speed Memory Card Hosts eMMC and SD Two Master/Slave Serial Peripheral Interfaces Two Synchronous Serial Controllers Three Two-wire Interface up to 400 Kbit/s supporting I2C Protocol and SMBUS Four USARTs, two UARTs, one DBGU Two Three-channel 32-bit Timer/Counters One 4-channel 16-bit PWM Controller

SAMA5D3 Series [DATASHEET]

One 12-channel 12-bit Analog-to-Digital Converter with Resistive Touch-Screen function Safety

Power-on Reset Cells Independent Watchdog Main Crystal Clock Failure Detection Write Protection Registers SHA Supports Secure Hash Algorithm SHA1, SHA224, SHA256, SHA384, SHA512 Memory Management Unit Security TRNG True Random Number Generator Encryption Engine

AES 256-bit, 192-bit, 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications TDES Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications Secure Boot Solution I/O Five 32-bit Parallel Input/Output Controllers 160 I/Os Input Change Interrupt Capability on Each I/O Line, Selectable Schmitt Trigger Input Individually Programmable Open-drain, Pull-up and Pull-down Resistor, Synchronous Output, Filtering Slew Rate Control on High Speed I/Os Impedance Control on DDR I/Os Package 324-ball LFBGA, 15 x 15 x mm, pitch mm 324-ball TFBGA, 12 x 12 x mm, pitch mm

Table SAMA5D3 Device Differences

Peripherals

SAMA5D31 SAMA5D33

CAN0, CAN1

EMAC

GMAC

HSMCI2

LCDC

UART0, UART1

SAMA5D34 X

SAMA5D35 X

SAMA5D36 X

SAMA5D3 Series [DATASHEET]

Block Diagram

Figure SAMA5D3 Block Diagram

NTRST VHHHHBHHHHGSSSSDDDDPPMMCBBC

FIQ IRQ DRXD DTXD PCK0-PCK2

XIN XOUT

XIN32 XOUT32

SHDN WKUP VDDBU NRST

SysC AIC DBGU

PLLA

PLLUTMI Osc12 MHz
12 MHZ RC Osc

WDT RC OSC 32K
4 GPBR

SHDC

POR PIOA PIOC PIOE
Data Ordering

The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding.

SAMA5D3 Series [DATASHEET]

All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows the user to program the same component order as the sensor, reducing software treatments to restore the right format.
Table Data Ordering in YCbCr Mode

Mode

Byte 0

Default

Mode 1

Mode 2

Mode 3

Byte 1 Y i Y i Cb i Cr i

Byte 2 Cr i Cb i Y i+1 Y i+1

Byte 3 Y i+1 Y i+1 Cr i Cb i

Table RGB Format in Default Mode, RGB_CFG = 00, No Swap

Mode

Byte

Byte 0

RGB 8:8:8

Byte 1 Byte 2

G7 i B7 i

G6 i B6 i

G5 i B5 i

G4 i B4 i

Byte 3

R7 i+1 R6 i+1 R5 i+1 R4 i+1

Byte 0

RGB 5:6:5

Byte 1 Byte 2

G2 i R4 i+1

G1 i R3 i+1

G0 i R2 i+1

B4 i R1 i+1

Byte 3

G2 i+1 G1 i+1 G0 i+1 B4 i+1

D3 R3 i G3 i B3 i R3 i+1 R0 i B3 i R0 i+1 B3 i+1

D2 R2 i G2 i B2 i R2 i+1 G5 i B2 i G5 i+1 B2 i+1

D1 R1 i G1 i B1 i R1 i+1 G4 i B1 i G4 i+1 B1 i+1

D0 R0 i G0 i B0 i R0 i+1 G3 i B0 i G3 i+1 B0 i+1

Table RGB Format, RGB_CFG = 10 Mode 2 , No Swap

Mode

Byte

Byte 0

RGB 5:6:5

Byte 1 Byte 2
All devices are marked with the Atmel logo and the ordering code. Additional marking may be in one of the following formats:

YYWW V

SAMA5D3 Series [DATASHEET] 1786
SAMA5D3 Ordering Information
Table SAMA5D3 Ordering Information
Ordering Code

Carrier Type

ATSAMA5D31A-CU ATSAMA5D31A-CUR

LFBGA324

ATSAMA5D31A-CFU ATSAMA5D31A-CFUR

TFBGA324

ATSAMA5D33A-CU

ATSAMA5D33A-CUR

ATSAMA5D34A-CU

ATSAMA5D34A-CUR

ATSAMA5D35A-CU

ATSAMA5D35A-CUR ATSAMA5D36A-CU

LFBGA324

ATSAMA5D36A-CUR

ATSAMA5D35A-CN

ATSAMA5D35A-CNR

ATSAMA5D36A-CN

ATSAMA5D36A-CNR

Packing Tray

Tape and Reel Tray

Tape and Reel Tray

Tape and Reel Tray

Tape and Reel Tray

Tape and Reel Tray

Tape and Reel Tray

Tape and Reel Tray

Tape and Reel

Package Type Operating Temperature Range

Green

Industrial -40°C to 85°C

Industrial -40°C to 105°C

SAMA5D3 Series [DATASHEET] 1787

SAMA5D3 Series Errata

Standard Boot Strategies

Boot ROM Boot on MCI1 is Not Working Boot on MCI1 is not working. Problem Fix/Workaround Use a different boot media.

Boot ROM NAND Flash Detection using ONFI Parameters does Not Work During Nandflash initialization, the ONFI parameter detection may not work correctly. This can lead to incorrect configuration of ECC settings and to reading wrong data from the Nandflash memory, thus making it impossible to boot from this memory. Problem Fix/Workaround When programming the bootable program in the Nandflash, always use the header method, with any Nandflash memory, ONFI compliant or not.

Static Memory Controller HSMC

HSMC ECC Value after ERASE is Not Correct When ERASE page command is issued, the NAND Flash page resets to "ALL_ONE" pattern. The ECC value of ALL_ONE is a fixed but non-zero pattern leading to error detection after page erase. Problem Fix/Workaround None.

LCD Controller LCDC

LCDC PWM Is Not Usable with DIV_1 When PWMPS field is set to DIV_1 value, the pwm ouput is stuck. It works fine for every other divider DIV_2 up to DIV_64 . Problem Fix/Workaround None.

PWM Controller PWM
Section “SAMA5D3 Ordering Information”
Updated Table 56-1 “SAMA5D3 Ordering Information” includes adding SAMA5D36 device references and introduction of 324-ball TFBGA package
8822 9035

Section “SAMA5D3 Series Errata” Updated Section “LCD Controller LCDC ” Added Section “Watchdog Timer WDT ”
8971 8969

SAMA5D3 Series [DATASHEET] 1805

Comments

Change Request Ref.

Introduction:

Section “Chip Identification”, updated Chip ID “0x8A5C07C1” --> “0x8A5C07C2”.
“Description” , added a cross-reference to Table 1-1 “SAMA5D3 Device Differences” in the last paragraph. rfo

Replaced “Cortex ” references with in “Description” and further on in the entire document.

Removed “AT91SAM” from the document title.

Standard Boot Strategies:

Section “NAND Flash Boot NAND Flash Detection”, added the eccBitReq field description in “NAND 8796 Flash Specific Header Detection”

SFR:

Added a row for SFR_UTMICKTRIM register offset value “0x30” in Table 16-1 "Register Mapping" and the corresponding Table "UTMI Clock Trimming Register".
8683

External Memories:

Section “Product Dependencies”, updated LPDDR2 Mode data in Table 28-2 “DDR2 I/O Lines Usage vs rfo Operating Modes” DDR_WE, DDR_RAS - DDR_CAS, and DDR_A[13..0] .

Section “2x16-bit LPDDR2”, added references on CAx LP-DDR2 signals and Table 28-3 “CAx LPDDR2 Signal Connection”.

USART Added a paragraph on IRDA_FILTER programming criteria in Section “IrDA Demodulator” and in the corresponding field description in Section “USART IrDA FILTER Register”. Section “USART FI DI RATIO Register”, expanded FI_DI_RATIO field to 16 bits in the register table.
8508 8643

FUSE Section “Embedded Characteristics”, added references on FUSE bits. Added Section “FUSE Bit Mapping” and Section “Special Functions”.
8785

Electrical Characteristics:

Section “12 MHz RC Oscillator Characteristics”, updated the IDDON value in Table

Section “32 kHz Oscillator Characteristics”, added a row on PON in Table

Section “12-Bit ADC Characteristics”, updated data in:
- Table 54-22 “Analog Power Supply Characteristics”
- Table 54-23 “Channel Conversion Time and ADC Clock”
- Table 54-24 “External Voltage Reference Input”
- Table 54-25 “INL, DNL, 12-bit mode, VDDANA 2.4V to 3.6V supply voltage conditions”
- Table 54-26 “Gain Error, 12-bit Mode, VDDANA 2.4V to 3.6V supply voltage conditions”
- Table 54-27 “Error offset with or without calibration, 12-bit Mode, VDDANA 2.4V to 3.6V supply voltage conditions”
- Table 54-28 “Dynamic Performance Characteristics in Single ended and 12 bits mode 1 ” and
- Table 54-29 “Dynamic Performance Characteristics in Differential and 12 bits mode 1 ”

Added Section “MPDDRC Timings”

Section “SSC Timings”, updated PIXCLK frequency maximum value and fixed transmitter parameter data rfo
for SSC7 in Table 54-47 “SSC Timings with 3.3V Peripheral supply” and Table 54-48 “SSC Timing with 1V8 Peripheral supply”

SAMA5D3 Series [DATASHEET] 1806

Comments Mechanical Characteristics Added “Nominal Ball Diameter” and “Solder” rows in Table 55-4 “Package Information”. Errata Added the introduction paragraph in Section “SAMA5D3 Series Errata”. Added Section “Boot ROM NAND Flash Detection using ONFI Parameters does Not Work”.
SAMA5D3 Ordering Information 1787 SAMA5D3 Series Errata 1788

Standard Boot Strategies 1788 Static Memory Controller HSMC 1788 LCD Controller LCDC 1788 PWM Controller PWM 1788 Gigabit Ethernet MAC GMAC 1789 Watchdog Timer WDT 1790

SAMA5D3 Series [DATASHEET] 1816

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Datasheet ID: ATSAMA5D35A-CUR 519376