PCX7457VGH1000NC

PCX7457VGH1000NC Datasheet


The letter X in the part number designates a "Prototype" product that has not been qualified by Atmel. Reliability of a PCX part-number is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes.

Part Datasheet
PCX7457VGH1000NC PCX7457VGH1000NC PCX7457VGH1000NC (pdf)
Related Parts Information
PCX7457VGU933NC PCX7457VGU933NC PCX7457VGU933NC
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• 3000 Dhrystone MIPS at GHz
• Selectable Bus Clock 30 CPU Bus Dividers up to 28x
• 13 Selectable Core-to-L3 Frequency Divisors
• Selectable MPx/60x Interface Voltage 1.8V, 2.5V
• Selectable L3 Interface of 1.8V or 2.5V
• PD Typical 12.6W at 1 GHz at VDD = 1.3V 8.3W at 1 GHz at VDD = 1.1V, Full Operating

Conditions
• Nap, Doze and Sleep Modes for Power Saving
• Superscalar Four Instructions Fetched Per Clock Cycle
• 4 GB Direct Addressing Range
• Virtual Memory 4 Hexabytes 252
• 64-bit Data and 36-bit Address Bus Interface
• Integrated L1 36 KB Instruction and 32 KB Data Cache
• Integrated L2 512 KB
• 11 Independent Execution Units and Three Register Files
• Write-back and Write-through Operations
• fINT Max = 1 GHz to be Confirmed
• fBUS Max = 133 MHz/166 MHz

PowerPC 7457 RISC Microprocessor

PC7457

The PC7457 is implementations of the microprocessor family of reduced instruction set computer RISC microprocessors. This document describes pertinent electrical and physical characteristics of the PC7457.

The PC7457 is the fourth implementation of the fourth generation G4 microprocessors from Freescale. The PC7457 implements the full PowerPC 32-bit architecture and is targeted at networking and computing systems applications. The PC7457 consists of a processor core, a 512 Kbyte L2, and an internal L3 tag and controller which support a glueless backside L3 cache through a dedicated high-bandwidth interface.

The core is a high-performance superscalar design supporting a double-precision floating-point unit and a SIMD multimedia unit. The memory storage subsystem supports the MPX bus interface to main memory and other system resources. The L3 interface supports 1, 2, or 4M bytes of external SRAM for L3 cache and/or private memory data. For systems implementing 4M bytes of SRAM, a maximum of 2M bytes may be used as cache the remaining 2M bytes must be private memory.

Note that the PC7457 is a footprint-compatible, drop-in replacement in a PC7455 application if the core power supply is 1.3V.

Screening
• CBGA Upscreenings Based on Atmel Standards
• Full Military Temperature Range TJ = -55° C, +125° C , Industrial Temperature Range TJ = -40° C, +110° C
• HCTE Package for the 7457

G suffix CBGA 483 Ceramic Ball Grid Array

GH suffix HITCE 483 Ceramic Ball Grid Array
2 PC7457

Block Diagram

Figure PC7457 Microprocessor Block Diagram

Additional Features
- Time Base Counter/Decrementer - Clock Multiplier - JTAG/COP Interface - Thermal/Power Management - Performance Monitor

Completion Unit 96-Bit 3 Instructions

Completion Queue 16-Entry

Instruction Unit

Branch Processing Unit BTIC 128-Entry CTR BHT 2048-Entry LR

Fetcher

Dispatch Unit

VR Issue 4-Entry/2-Issue

GPR Issue 6-Entry/3-Issue

Instruction Queue 12-Word

FPR Issue 2-Entry/1-Issue

Instruction MMU SRs 128-Entry Shadow ITLB

IBAT Array
128-Bit 4 Instructions 32-Kbyte

Tags I Cache

Data MMU
128-Entry

Original DTLB

DBAT Array

Tags
32-Kbyte D Cache

Completes up
to three instructions per clock
This section provides the AC electrical characteristics for the PC7457. After fabrication, functional parts are sorted by maximum processor core frequency as shown in section “Clock AC Specifications” and tested for conformance to the AC specifications for that frequency. The processor core frequency is determined by the bus SYSCLK frequency and the settings of the PLL_CFG[0:4] signals. Parts are sold by maximum processor core frequency See “Ordering Information” on page

Clock AC Specifications

Table 7-2 provides the clock AC timing specifications as defined in Figure 7-1 and represents the tested operating frequencies of the devices. The maximum system bus frequency, fSYSCLK, given in Table 7-2 is considered a practical maximum in a typical single-processor system. The actual maximum SYSCLK frequency for any application of the PC7457 will be a function of the AC timings of the PC7457, the AC timings for the system controller, bus loading, printed-circuit
board topology, trace lengths, and so forth, and may be less than the value given in Table

Table Clock AC Timing Specifications See “Recommended Operating Conditions 1 ” on page 12

Maximum Processor Core Frequency
600 MHz
867 MHz
1000 MHz

Characteristic

VDD = 1.1V

VDD = 1.1V

VDD = 1.1V
fCORE 1 fVCO 1 fSYSCLK 1 2 tSYSCLK 2 tKR, tKF 3 tKHKL/tSYSCLK 4

Processor frequency VCO frequency SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time SYSCLK duty cycle measured at OVDD/2 SYSCLK jitter 5 6
500 1000
33 6 40
600 1200 167
30 1 60 150
500 1000
33 6 40
867 1733 167
30 1 60 150
500 1000
1000 2000 167

Internal PLL relock time 7

Unit MHz
ns % ps µs

Symbol fCORE 1 fVCO 1 fSYSCLK 1 2 tSYSCLK 2 tKR, tKF 3

Characteristic Processor frequency VCO frequency SYSCLK frequency SYSCLK cycle time SYSCLK rise and fall time
20 PC7457

Maximum Processor Core Frequency
867 MHz
1000 MHz
1200 MHz
1267 MHz

VDD = 1.3V Min Max

VDD = 1.3V Min Max

VDD = 1.3V Min Max

VDD = 1.3V Min Max
600 867 600 1000 600 1200 600 1267
Ordering Information
xx 7457

Product Part Code 1 Identifier

Temperature Range TJ 1

Package 1

Screening Level

Max Internal

Processor Speed 1

Modifier 1 Level 1

PC X 2
7457

G CBGA GH HiTCE

V GHY HiTCE

U Upscreening CBGA

Blank standard
933 MHz 1000 MHz

N 1.1V ± 50 mV

For availability of the different versions, contact your local Atmel sales office.

The letter X in the part number designates a "Prototype" product that has not been qualified by Atmel. Reliability of a PCX part-number is not guaranteed and such part-number shall not be used in Flight Hardware. Product changes may still occur while shipping prototypes.
56 PC7457

PC7457

Date Substantive Change s
03/06 Remove PC7447. Modification Table 6-1 on page 13? and ordering information

Updated document to new Atmel template

Updated section numbering and changed reference from part number specifications to addendums

Table 6-2 on page 13 Added CTE information

Table 7-2 on page 20 Modified jitter specifications to conform to JEDEC standards, changed jitter specification to cycle-to-cycle jitter instead of long- and short-term jitter changed jitter bandwidth recommendations

Table 7-7 on page 29 Deleted note 9 and renumbered.

Table 7-8 on page 31 Deleted note 5 and renumbered
06/2005

Added Section ”System Bus Clock SYSCLK and Spread Spectrum Sources” on page 50

Section on page 47 Corrected note regarding different PLL configurations for earlier devices all PC7457 devices to date conform to this table

Section on page 52 Added information about unused L3_ADDR signals.

HCTE package information

Preliminary specification α-site release subsequent to preliminary specification Motorola changed to Freescale

Figure 7-3 on page 22 Corrected pin lists for input and output AC timing to correctly show HIT as an outputonly signal
11/2004 Added specifications for 1267 MHz devices removed specs for 1300 MHz devices.

Changed recommendations regarding use of L3 clock jitter in AC timing analysis in Section “L3 Clock AC

Specifications” on page 24 the L3 jitter is now fully comprehended in the AC timing specs and does not
need to be included in the timing analysis

PC7457

Table of Contents

Features 1 Description 1 Screening 2 1 Block Diagram 3 2 General Parameters 4 3 Overview 4 Signal Description 10 5 Detailed Specification 11 6 Applicable Documents 11

Design and Construction Thermal Characteristics
7 Electrical Characteristics 19

Static Characteristics Dynamic Characteristics
8 Preparation for Delivery 36

Handling Package Parameters for the PC7457, 483 CBGA and 483 HCTE
9 Mechanical Dimensions for the PC7457, 483 CBGA 41 10 Substrate Capacitors for the PC7457, 483 CBGA 42 11 Mechanical Dimensions for the PC7457, 483 HCTE 43 12 Substrate Capacitors for the PC7457, 483 HCTE 44 13 Mechanical Dimensions for the PC7457, 483 HCTE ROHS compliant 45 14 Substrate Capacitors for the PC7457, 483 HCTE ROHS Compliant 45 15 System Design Information 47

Clocks PLL Power Supply Filtering Decoupling Recommendations Connection Recommendations Output Buffer DC Impedance

Pull-up/Pull-down Resistor Requirements JTAG Configuration Signals
16 Definitions 56

Life Support Applications
Table of Contents i
ii PC7457

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More datasheets: 84872024 | 84872020 | 84872033 | 5962F1123501QXA | FAN5308MPX | 7A0124 | 10226-2200VE | 10226-2210VE | 540-021 | PCX7457VGU933NC


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Datasheet ID: PCX7457VGH1000NC 519351