ATSAM4E8CA-AUR

ATSAM4E8CA-AUR Datasheet

Reset is invoked on power up or a warm reset. The exception model treats reset as a special form of exception. When reset is asserted, the operation of the processor stops, potentially at any point in an instruction. When reset is deasserted, execution restarts from the address provided by the reset entry in the vector table. Execution restarts as privileged execution in Thread mode. Non Maskable Interrupt NMI

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ATSAM4E8CA-AUR	ATSAM4E8CA-AUR (pdf)

Related Parts	Information
ATSAM4E8EA-AU	ATSAM4E8EA-AU
ATSAM4E8EA-AUR	ATSAM4E8EA-AUR
ATSAM4E8CA-AU	ATSAM4E8CA-AU
ATSAM4E8CA-ANR	ATSAM4E8CA-ANR
ATSAM4E8EA-AN	ATSAM4E8EA-AN
ATSAM4E8CA-AN	ATSAM4E8CA-AN

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ARM-based Flash MCU SAM4E16E SAM4E8E SAM4E16C SAM4E8C DATASHEET The Atmel SAM4E series of Flash microcontrollers is based on the high-performance 32-bit RISC processor and includes a floating point unit FPU . It operates at a maximum speed of 120 MHz and features up to 1024 Kbytes of Flash, 2 Kbytes of cache memory and up to 128 Kbytes of SRAM. The SAM4E offers a rich set of advanced connectivity peripherals including 10/100 Mbps Ethernet MAC supporting IEEE 1588 and dual CAN. With a singleprecision FPU, advanced analog features, as well as a full set of timing and control functions, the SAM4E is the ideal solution for industrial automation, home and building control, machine-to-machine communications, automotive aftermarket and energy management applications. The peripheral set includes a full-speed USB device port with embedded transceiver, a 10/100 Mbps Ethernet MAC supporting IEEE 1588, a high-speed MCI for SDIO/SD/MMC, an external bus interface featuring a static memory controller providing connection to SRAM, PSRAM, NOR Flash, LCD module and NAND Flash, a parallel I/O capture mode for camera interface, hardware acceleration for AES256, two USARTs, two UARTs, two TWIs, three SPIs, as well as a 4-channel PWM, nine general-purpose 16-bit timers with stepper motor and quadrature decoder logic support , one RTC, two analog front end interfaces 16-bit ADC, DAC, MUX and PGA , one 12-bit DAC 2-ch and an analog comparator. Core with 2 Kbytes Cache running at up to 120 MHz 1 Memory Protection Unit MPU DSP Instruction Floating Point Unit FPU Instruction Set Memories Up to 1024 Kbytes Embedded Flash 128 Kbytes Embedded SRAM 16 Kbytes ROM with Embedded Boot Loader Routines UART and IAP Routines Static Memory Controller SMC SRAM, NOR, NAND Support. NAND Flash Controller. System Embedded Voltage Regulator for Single Supply Operation Power-on-Reset POR , Brown-out Detector BOD and Dual Watchdog for Safe Operation Quartz or Ceramic Resonator Oscillators 3 to 20 MHz Main Power with Failure Detection and Optional Lowpower kHz for RTC or Device Clock RTC with Gregorian and Persian Calendar Mode, Waveform Generation in Low-power Modes RTC Clock Calibration Circuitry for kHz Crystal Frequency Compensation High Precision 4/8/12 MHz Factory Trimmed Internal RC Oscillator with 4 MHz Default Frequency for Device Startup. In-application Trimming Access for Frequency Adjustment Slow Clock Internal RC Oscillator as Permanent Low-power Mode Device Clock One PLL up to 240 MHz for Device Clock and for USB Temperature Sensor Up to 2 Peripheral DMA Controller with up to 33 Channels PDC One 4-channel DMA Controller Low-power Modes Sleep and Backup Modes Ultra Low-power RTC Peripherals Two USARTs with USART1 ISO7816, RS-485, SPI, Manchester and Modem Modes USB Device Full Speed 12 Mbits , 2668 byte FIFO, up to 8 Endpoints. On-chip Transceiver Two 2-wire UARTs Two-wire Interfaces TWI High-speed Multimedia Card Interface SDIO/SD Card/MMC One Master/Slave Serial Peripheral Interface SPI with Chip Select Signals Three 3-Channel 32-bit Timer/Counter with Capture, Waveform, Compare and PWM Mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor 32-bit Real-time Timer and RTC with Calendar and Alarm Features One Ethernet MAC EMAC 10/100 Mbps in MII mode only with Dedicated DMA and Support for IEEE1588, Wake-on-LAN Two CAN Controllers with eight Mailboxes 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time Generator Counter for Motor Control Real-time Event Management SAM4E [DATASHEET] Cryptography AES 256-bit Key Algorithm compliant with FIPS Publication 197 Analog AFE Analog Front End 2x16-bit ADC, up to 24-channels, Differential Input Mode, Programmable Gain Stage, Auto Calibration and Automatic Offset Correction One 2-channel 12-bit 1 Msps DAC One Analog Comparator with Flexible Input Selection, Selectable Input Hysteresis I/O Up to 117 I/O Lines with External Interrupt Capability Edge or Level Sensitivity , Debouncing, Glitch Filtering and On-die Series Resistor Termination Bidirectional Pad, Analog I/O, Programmable Pull-up/Pull-down Five 32-bit Parallel Input/Output Controllers, Peripheral DMA Assisted Parallel Capture Mode Packages 144-ball LFBGA, 10x10 mm, pitch mm 100-ball TFBGA, 9x9 mm, pitch mm 144-lead LQFP, 20x20 mm, pitch mm 100-lead LQFP, 14x14 mm, pitch mm Note 120 MHz -40/+105°C, VDDCORE = 1.2V or using internal voltage regulator SAM4E [DATASHEET] Configuration Summary The SAM4E series devices differ in memory size, package and features. Table 1-1 summarizes the configurations of the device family. Table Configuration Summary SAM4E16E SAM4E8E Flash 1024 Kbytes 512 Kbytes SRAM 128 Kbytes CMCC 2 Kbytes LFBGA 144 Package LQFP 144 Number of PIOs External Bus Interface Analog Front End AFE0 8-bit Data, 4 Chip Selects, 24-bit Address Up to 16 bits 1 16 8 ch 2 EMAC 12-bit DAC Timer 2 ch. 9 4 PDC Channels USART/ UART 24 +9 2/2 6 Full Speed The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory. Additional Memory Attributes Shareable For a shareable memory region, the memory system provides data synchronization between bus masters in a system with multiple bus masters, for example, a processor with a DMA controller. Strongly-ordered memory is always shareable. If multiple bus masters can access a non-shareable memory region, the software must ensure data coherency between the bus masters. Execute Never XN Means the processor prevents instruction accesses. A fault exception is generated only on execution of an instruction executed from an XN region. Memory System Ordering of Memory Accesses For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing this does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, the software must insert a memory barrier instruction between the memory access instructions, see “Software Ordering of Memory Accesses” However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of the memory accesses is described below. Table Ordering of the Memory Accesses Caused by Two Instructions Device Access Strongly- Normal ordered Access Non-shareable Access Normal Access Device access, nonshareable Device access, shareable Strongly-ordered access Where: Means that the memory system does not guarantee the ordering of the accesses. < Means that accesses are observed in program order, that is, A1 is always observed before A2. SAM4E [DATASHEET] 59 Behavior of Memory Accesses The behavior of accesses to each region in the memory map is: Table Memory Access Behavior Address Range Memory Region Memory Type XN Description - Code Normal 1 - Executable region for program code. Data can also be put here. - SRAM Normal 1 - Executable region for data. Code can also be put here. This region includes bit band and bit band alias areas, see Table - Peripheral Device 1 This region includes bit band and bit band alias areas, see Table - External RAM Normal 1 - Executable region for data. - External device Device 1 XN External Device memory Private Peripheral Bus Stronglyordered 1 This region includes the NVIC, System timer, and system control block. - Reserved Device 1 XN Reserved Note See “Memory Regions, Types and Attributes” for more information. The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends that programs always use the Code region. This is because the processor has separate buses that enable instruction fetches and data accesses to occur simultaneously. The MPU can override the default memory access behavior described in this section. For more information, see “Memory Protection Unit MPU ” Additional Memory Access Constraints For Caches and Shared Memory When a system includes caches or shared memory, some memory regions have additional access constraints, and some regions are subdivided, as Table 12-5 shows: Table Memory Region Shareability and Cache Policies Address Range Memory Region Memory Type Shareability Code Normal 1 SRAM Normal 1 Software Ordering of Memory Accesses The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions. This is because: The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence. The processor has multiple bus interfaces Memory or devices in the memory map have different wait states Some memory accesses are buffered or speculative. “Memory System Ordering of Memory Accesses” describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, the software must include memory barrier instructions to force that ordering. The processor provides the following memory barrier instructions DMB The Data Memory Barrier DMB instruction ensures that outstanding memory transactions complete before subsequent memory transactions. See “DMB” DSB The Data Synchronization Barrier DSB instruction ensures that outstanding memory transactions complete before subsequent instructions execute. See “DSB” ISB The Instruction Synchronization Barrier ISB ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. See “ISB” MPU Programming Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by subsequent instructions. SAM4E [DATASHEET] 61 Bit-banding A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions. The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions Accesses to the 32 MB SRAM alias region map to the 1 MB SRAM bit-band region, as shown in Table Accesses to the 32 MB peripheral alias region map to the 1 MB peripheral bit-band region, as shown in Table Table SRAM Memory Bit-banding Regions Address Range Memory Region Instruction and Data Accesses SRAM bit-band region Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit-addressable through bit-band alias. SRAM bit-band alias Data accesses to this region are remapped to bit-band region. A write operation is performed as read-modifywrite. Instruction accesses are not remapped. Table Peripheral Memory Bit-banding Regions Address Range Memory Region Instruction and Data Accesses Peripheral bit-band alias Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bitaddressable through bit-band alias. Peripheral bit-band region Data accesses to this region are remapped to bit-band region. A write operation is performed as read-modifywrite. Instruction accesses are not permitted. Notes A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or peripheral bit-band region. Bit-band accesses can use byte, halfword, or word transfers. The bit-band transfer size matches the transfer size of the instruction making the bit-band access. The following formula shows how the alias region maps onto the bit-band region bit_word_offset = byte_offset x 32 + bit_number x 4 bit_word_addr = bit_band_base + bit_word_offset where Bit_word_offset is the position of the target bit in the bit-band memory region. Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit. Bit_band_base is the starting address of the alias region. Byte_offset is the number of the byte in the bit-band region that contains the targeted bit. Bit_number is the bit position, 0-7, of the targeted bit. Figure 12-4 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region: The alias word at 0x23FFFFE0 maps to bit[0] of the bit-band byte at 0x23FFFFE0 = + + The alias word at maps to bit[7] of the bit-band byte at = + + The alias word at maps to bit[0] of the bit-band byte at = + 032 + 0 SAM4E [DATASHEET] 62 The alias word at 0x2200001C maps to bit[7] of the bit-band byte at 0x2200001C = 032 + Figure Bit-band Mapping 32 MB alias region 0x23FFFFEC 0x23FFFFE8 0x23FFFFE4 0x23FFFFE0 0x2200001C 0x22000018 0x22000014 0x22000010 1 MB SRAM bit-band region 76543210765432107654321076543210 DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access memory. Condition Flags This instruction does not change the flags. Examples DMB Data Memory Barrier SAM4E [DATASHEET] Data Synchronization Barrier. Syntax where: cond is an optional condition code, see “Conditional Execution” Operation DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete. Condition Flags This instruction does not change the flags. Examples DSB Data Synchronisation Barrier Instruction Synchronization Barrier. Syntax where: cond is an optional condition code, see “Conditional Execution” Operation ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from cache or memory again, after the ISB instruction has been completed. Condition Flags This instruction does not change the flags. Examples ISB Instruction Synchronisation Barrier SAM4E [DATASHEET] Move the contents of a special register to a general-purpose register. Syntax Rd, spec_reg where: cond is an optional condition code, see “Conditional Execution” is the destination register. spec_reg can be any of APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL. Operation Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to clear the Q flag. In process swap code, the programmers model state of the process being swapped out must be saved, including relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These operations use MRS in the state-saving instruction sequence and MSR in the state-restoring instruction sequence. Note BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction. See “MSR” Restrictions Rd must not be SP and must not be PC. Byte ordering scheme in which bytes of decreasing significance in a data word are stored at increasing addresses in memory. See also “Byte-invariant” , “Endianness” , “Little-endian LE ” Memory in which a byte or halfword at a word-aligned address is the most significant byte or halfword within the word at that address, a byte at a halfword-aligned address is the most significant byte within the halfword at that address. See also “Little-endian memory” Breakpoint A breakpoint is a mechanism provided by debuggers to identify an instruction at which program execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of register contents, memory locations, variable values at fixed points in the program execution to test that the program is operating correctly. Breakpoints are removed after the program is successfully tested. SAM4E [DATASHEET] Byte-invariant In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access. An ARM byte-invariant implementation also supports unaligned halfword and word memory accesses. It expects multi-word accesses to be word-aligned. Cache Condition field A block of on-chip or off-chip fast access memory locations, situated between the processor and main memory, used for storing and retrieving copies of often used instructions, data, or instructions and data. This is done to greatly increase the average speed of memory accesses and so improve processor performance. A four-bit field in an instruction that specifies a condition under which the instruction can execute. Conditional execution Context Coprocessor If the condition code flags indicate that the corresponding condition is true when the instruction starts executing, it executes normally. Otherwise, the instruction does nothing. The environment that each process operates in for a multitasking operating system. In ARM processors, this is limited to mean the physical address range that it can access in memory and the associated memory access permissions. A processor that supplements the main processor. Cortex-M4 does not support any coprocessors. Debugger Direct Memory Access DMA Doubleword A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging. An operation that accesses main memory directly, without the processor performing any accesses to the data concerned. A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated. Doubleword-aligned Endianness A data item having a memory address that is divisible by eight. Byte ordering. The scheme that determines the order that successive bytes of a data word are stored in memory. An aspect of the system’s memory mapping. See also “Little-endian LE ” and “Big-endian BE ” SAM4E [DATASHEET] Exception An event that interrupts program execution. When an exception occurs, the processor suspends the normal program flow and starts execution at the address indicated by the corresponding exception vector. The indicated address contains the first instruction of the handler for the exception. An exception can be an interrupt request, a fault, or a software-generated system exception. Faults include attempting an invalid memory access, attempting to execute an instruction in an invalid processor state, and attempting to execute an undefined instruction. Exception service routine See “Interrupt handler” Exception vector Flat address mapping See “Interrupt vector” A system of organizing memory in which each physical address in the memory space is the same as the corresponding virtual address. Halfword Illegal instruction Implementation-defined A 16-bit data item. An instruction that is architecturally Undefined. The behavior is not architecturally defined, but is defined and documented by individual implementations. Implementation-specific The behavior is not architecturally defined, and does not have to be documented by individual implementations. Used when there are a number of implementation options available and the option chosen does not affect software compatibility. Index register In some load and store instruction descriptions, the value of this register is used as an offset to be added to or subtracted from the base register value to form the address that is sent to memory. Some addressing modes optionally enable the index register value to be shifted prior to the addition or subtraction. See also “Base register” Instruction cycle count Interrupt handler Interrupt vector The number of cycles that an instruction occupies the Execute stage of the pipeline. A program that control of the processor is passed to when an interrupt occurs. One of a number of fixed addresses in low memory, or in high memory if high vectors are configured, that contains the first instruction of the corresponding interrupt handler. SAM4E [DATASHEET] Little-endian LE Little-endian memory Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory. See also “Big-endian BE ” , “Byte-invariant” , “Endianness” Memory in which a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at that address, a byte at a halfword-aligned address is the least significant byte within the halfword at that address. See also “Big-endian memory” Load/store architecture A processor architecture where data-processing operations only operate on register contents, not directly on memory contents. Memory Protection Unit MPU Prefetching Hardware that controls access permissions to blocks of memory. An MPU does not perform any address translation. In pipelined processors, the process of fetching instructions from memory to fill up the pipeline before the preceding instructions have finished executing. Prefetching an instruction does not mean that the instruction has to be executed. Preserved Read Region Reserved Preserved by writing the same value back that has been previously read from the same field on the same processor. Reads are defined as memory operations that have the semantics of a load. Reads include the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP. A partition of memory space. A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces Unpredictable results if the contents of the field are not zero. These fields are reserved for use in future extensions of the architecture or are implementation-specific. All reserved bits not used by the implementation must be written as 0 and read as Thread-safe Thumb instruction In a multi-tasking environment, thread-safe functions use safeguard mechanisms when accessing shared resources, to ensure correct operation without the risk of shared access conflicts. One or two halfwords that specify an operation for a processor to perform. Thumb instructions must be halfword-aligned. SAM4E [DATASHEET] Unaligned Undefined Unpredictable Warm reset WA WB Word Write-allocate WA Write-back WB Write buffer Write-through WT A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned. For example, a word stored at an address that is not divisible by four. Indicates an instruction that generates an Undefined instruction exception. One cannot rely on the behavior. Unpredictable behavior must not represent security holes. Unpredictable behavior must not halt or hang the processor, or any parts of the system. Also known as a core reset. Initializes the majority of the processor excluding the debug controller and debug logic. This type of reset is useful if debugging features of a processor. See “Write-allocate WA ” See “Write-back WB ” A 32-bit data item. Writes are defined as operations that have the semantics of a store. Writes include the Thumb instructions STM, STR, STRH, STRB, and PUSH. In a write-allocate cache, a cache miss on storing data causes a cache line to be allocated into the cache. In a write-back cache, data is only written to main memory when it is forced out of the cache on line replacement following a cache miss. Otherwise, writes by the processor only update the cache. This is also known as copyback. A block of high-speed memory, arranged as a FIFO buffer, between the data cache and main memory, whose purpose is to optimize stores to main memory. In a write-through cache, data is written to main memory at the same time as the cache is updated. SAM4E [DATASHEET] Debug and Test Features The SAM4 Series Microcontrollers feature a number of complementary debug and test capabilities. The Serial Wire/JTAG Debug Port SWJ-DP combining a Serial Wire Debug Port SW-DP and JTAG Debug JTAG-DP port is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace. Embedded Characteristics Debug access to all memory and registers in the system, including Cortex-M4 register bank when the core is running, halted, or held in reset. Serial Wire Debug Port SW-DP and Serial Wire JTAG Debug Port SWJ-DP debug access Flash Patch and Breakpoint FPB unit for implementing breakpoints and code patches Data Watchpoint and Trace DWT unit for implementing watchpoints, data tracing, and system profiling Instrumentation Trace Macrocell ITM for support of printf style debugging IEEE1149.1 JTAG Boundary-can on All Digital Pins SAM4E [DATASHEET] Debug and Test Block Diagram Ordering Information Table Ordering Codes for SAM4E Devices Ordering Code Flash MRL Kbytes ATSAM4E16EA-CU ATSAM4E16EA-CUR A ATSAM4E16EA-AU ATSAM4E16EA-AUR A ATSAM4E16EA-AN ATSAM4E16EA-ANR A ATSAM4E16CA-CU 1024 ATSAM4E16CA-CUR A ATSAM4E16CA-AU ATSAM4E16CA-AUR A ATSAM4E16CA-AN ATSAM4E16CA-ANR A ATSAM4E8EA-CU ATSAM4E8EA-CUR ATSAM4E8EA-AU ATSAM4E8EA-AUR ATSAM4E8EA-AN ATSAM4E8EA-ANR ATSAM4E8CA-CU ATSAM4E8CA-CUR ATSAM4E8CA-AU ATSAM4E8CA-AUR ATSAM4E8CA-AN ATSAM4E8CA-ANR Package LFBGA144 LQFP144 TFBGA100 LQFP100 LFBGA144 LQFP144 TFBGA100 LQFP100 Conditioning Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Package Type Green Temperature Operating Range Industrial -40°C to 85°C Industrial -40°C to 85°C Industrial -40°C to 105°C Industrial -40°C to 85°C Industrial -40°C to 85°C Industrial -40°C to 105°C Industrial -40°C to 85°C Industrial -40°C to 85°C All devices are marked with the Atmel logo and the ordering code. Additional marking is as follows: YYWW V Errata Watchdog Not Stopped in Wait Mode When the Watchdog is enabled and the bit WAITMODE = 1 is used to enter wait mode, the watchdog is not halted. If the time spent in Wait Mode is longer than the Watchdog time-out, the device will be reset if Watchdog reset is enabled. Problem Fix/Workaround When entering wait mode, the Wait For Event WFE instruction of the processor Cortex-M4 must be used with the SLEEPDEEP of the System Control Register SCB_SCR of the Cortex-M = Brownout Detector Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected In active mode or in wait mode, if the Brownout Detector is disabled SUPC_MR BODDIS=1 and power is lost on VDDCORE while VDDIO is powered, the device might not be properly reset and may behave unpredictably. Problem Fix/Workaround When the Brownout Detector is disabled in active or in wait mode, VDDCORE always needs to be powered. SAM4E [DATASHEET] 1363 SAM4E [DATASHEET] 1364 Change Request Ref. Introduction In “Features” - added information on Two-wire Interface in Peripherals section and Wake-on-LAN for EMAC - changed operating temperature range to 105°C Updated Table 1-1 “Configuration Summary” with TWI information In Section “Package and Pinout”, added the FFPI signals to Table 4-1 “SAM4E 100-ball TFBGA Pinout”, rfo 9045 Table 4-2 “SAM4E 144-ball LFBGA Pinout”, Table 4-3 “SAM4E 100-lead LQFP Pinout” and Table 4-4 “SAM4E 144-lead LQFP Pinout”. Updated Section “Low-power Modes”. Added information on WFE. 9073 In Section “General-purpose I/O Lines” on page 21, added information on GPIOs as analog input. 8992 Removed Section “Processor and Architecture”. Removed Sections 11-4 to Reordered introduction sections. Removed Note regarding PIOs and 144-pin package at bottom of Table 11-5, “Multiplexing on PIO Controller D 9018 PIOD ,” on page 40 and Table 11-6, “Multiplexing on PIO Controller E PIOE ,” on page RSTC In Section “Reset Controller Status Register”, RSTTYP information corrected. 8847 RTT: Added notes in Section “Functional Description”, Section “Real-time Timer Mode Register” and in Section “Real-time Timer Alarm Register”. 9026 RTC In Section “Alarm”, added new information and note. In Section “RTC Accurate Clock Calibration”, updated information on temperature range. 8900, 9027 9033 In Section “RTC Time Alarm Register” and Section “RTC Calendar Alarm Register”, added notes. 9027 WDT In Section “Description”, added information on slow clock at 32 kHz. 8429 In Section “Embedded Characteristics”, added that Watchdog Clock is independent from Processor Clock. Moved note WDD, WDV from Section “Watchdog Timer Status Register” to Section “Watchdog rfo Timer Mode Register”. EFC: In Section “Lock Bit Protection”, added notes on FARG exceeding limits. Updated existing note in Section “GPNVM Bit”. Added Section “Optimized Partial Programming”. Added note on programming limitations in Section “Write Commands”. 8854 8985 FFPI Removed information throughout on Serial Fast Flash Programming not available for device. 9007 SAM4E [DATASHEET] 1365 Ordering Information Table 48-1 “Ordering Codes for SAM4E Devices” updated with new ordering codes for parts at 105°C and for rfo tape & reel Errata Added Section “Errata on SAM4E Devices” that includes Section “Watchdog Not Stopped in Wait 9075 Mode” and Section “Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected” SAM4E [DATASHEET] 1367 Change Request Ref. Introduction: Updated the section structure and added references to 100-ball TFBGA and 100-lead LQFP packages in: 8580 - Section “Features” - Table 1-1 “Configuration Summary” - Figure 2-1 “SAM4E 100-pin Block Diagram” - Section “100-ball TFBGA Package and Pinout” - Section “100-lead LQFP Package and Pinout” - Table 11-1 “PIO available according to Pin Count” Added Analog Comparator ACC and Reinforced Safety Watchdog Timer RSWDT blocks in Figure 2-2 “SAM4E 144-pin Block Diagram”. 8605/rfo Updated the description of power supply pins in Section “Power Supplies”. 8644 Updated Figure 11-3 “Power Management Controller Block Diagram”. Removed RC80M references in Figure 10-1 “System Controller Block Diagram” and Figure 11-2 “Clock Generator Block Diagram”. 8724 Add data on consumption and wake-up time in Table 5-1 “Low-power Mode Configuration Summary”. Removed “AT91SAM” from the document title and further on in the entire document where appropriate . Replaced “Cortex ” references with in “Description” and further on in the entire document. Section “Chip Identification”, replaced “Table SAM4E Chip ID Register” with a cross-reference to rfo the corresponding Table 14-1 “SAM4E Chip ID Registers” Section “Chip Identifier CHIPID ” . Removed package dimension references in Section “Package and Pinout”. Added a phrase on the flash write commands usage in Section “Flash Overview” the last paragraph . rfo Updated package information in Section “Peripheral Signal Multiplexing on I/O Lines”: - replaced “100/144 pin version” with “144 pin version” in Table 11-4 “Multiplexing on PIO Controller C PIOC ” - removed “144 pin version” in Table 11-5 “Multiplexing on PIO Controller D PIOD ” Updated Figure 7-1 “SAM4E Product Mapping”. 8825 Replaced GRX by GRX1 on line PD6 in Table 11-5 “Multiplexing on PIO Controller D PIOD ”. 8897 CHIPID: Section “Chip Identifier CHIPID User Interface”, updated the ARCH bitfield table in “ARCH Architecture 8603 Identifier” removed rows with not relevant information 0x43, 0x88, 0x89, 0x8A, 0x93, 0x94, and 0x95 . Section “Embedded Characteristics”, replaced ‘0x0011_0201’ with ‘0x0012_0201’ and ‘0x0011_0209’ with 8851 ‘0x0012_0209’ in Table 14-1 “SAM4E Chip ID Registers”. Section “Chip ID Extension Register”, updated value in the Flash Size table and removed package references in the Product Number table. RTT: Section “Block Diagram”, replaced ‘CLKSRC’ source reference with ‘RTC1HZ’ in Figure 16-1 “Real-time 8574 Timer”. Updated the 4th and the 8th paragraphs in Section “Functional Description” “Setting the RTC 1 HZ clock to and “The RTTINC bit in RTT_SR is set...” respectively . Section “Real-time Timer Mode Register”, added notes in “RTTDIS Real-time Timer Disable” and “RTC1HZ Real-Time Clock 1Hz Clock Selection”. Ordering Codes: Added references to 100-ball TFBGA and 100-lead LQFP packages in Table 48-1 “Ordering Codes for SAM4E 8580 Devices”. Initial release Change Request Ref. SAM4E [DATASHEET] 1373 SAM4E [DATASHEET] 1374 Table of Contents Description1 Features 2 Configuration Summary 4 Block Diagram 5 Signal Description 7 Package and Pinout 11 100-ball TFBGA Package and Pinout 11 144-ball LFBGA Package and Pinout 12 100-lead LQFP Package and Pinout 13 144-lead LQFP Package and Pinout 14 Power Considerations 15 Power Supplies 15 Voltage Regulator 15 Typical Powering Schematics 15 Low-power Modes 16 Wake-up Sources 19 Fast Start-up 20 Input/Output Lines 21 General-purpose I/O Lines 21 System I/O Lines 22 Product Mapping 23 Memories 24 Embedded Memories 24 External Memories 28 Cortex-M Cache Controller CMCC 28 Real-time Event Management 29 Embedded Characteristics 29 Real-time Event Mapping List 30 System Controller 31 System Controller and Peripherals Mapping 32 Power-on-Reset, Brownout and Supply Monitor 32 Reset Controller 32 Peripherals 34 Peripheral Identifiers 34 Peripheral Signal Multiplexing on I/O Lines 36 ARM Cortex-M4 43 Description 43 SAM4E [DATASHEET] Embedded Characteristics 44 Block Diagram 45 Cortex-M4 Models 46 Power Management 75 Cortex-M4 Instruction Set 77 Cortex-M4 Core Peripherals 188 Nested Vectored Interrupt Controller NVIC 189 System Control Block SCB 199 System Timer SysTick 225 Memory Protection Unit MPU 230 Floating Point Unit FPU 243 Glossary 252 Debug and Test Features 257 Description 257 Embedded Characteristics 257 Debug and Test Block Diagram 258 Application Examples 259 Debug and Test Pin Description 260 Functional Description 261 Chip Identifier CHIPID 267 Description 267 Embedded Characteristics 267 Power Management Controller PMC User Interface 268 Reset Controller RSTC 275 Embedded Characteristics 275 Block Diagram 275 Functional Description 275 Reset Controller RSTC User Interface 282 Real-time Timer RTT 287 Description 287 Embedded Characteristics 287 Block Diagram 287 Functional Description 288 Real-time Timer RTT User Interface 290 Reinforced Safety Watchdog Timer RSWDT 295 Description 295 Embedded Characteristics 295 Block Diagram 296 Functional Description 297 Reinforced Safety Watchdog Timer RSWDT User Interface 299 Real-time Clock RTC 303 Ordering Information 1361 Errata on SAM4E Devices 1363 Marking 1363 Errata 1363 SAM4E [DATASHEET] viii Atmel Corporation 1600 Technology Drive San Jose, CA 95110 USA Tel +1 408 441-0311 Fax +1 408 487-2600 Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel +852 2245-6100 Fax +852 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel +49 89-31970-0 Fax +49 89-3194621 Atmel Japan G.K. 16F Shin-Osaki Kangyo Bldg 1-6-4 Osaki, Shinagawa-ku Tokyo 141-0032 JAPAN Tel +81 3 6417-0300 Fax +81 3 6417-0370 logo and combinations thereof, Enabling Unlimited and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. and are registered trademarks or trademarks of ARM Ltd. and others are registered trademarks or trademarks of Microsoft Corporation in the US and/or other countries. Other terms and product names may be trademarks of others. Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. 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ARM-based Flash MCU

SAM4E16E SAM4E8E SAM4E16C SAM4E8C DATASHEET

The Atmel SAM4E series of Flash microcontrollers is based on the high-performance 32-bit RISC processor and includes a floating point unit FPU . It operates at a maximum speed of 120 MHz and features up to 1024 Kbytes of Flash, 2 Kbytes of cache memory and up to 128 Kbytes of SRAM. The SAM4E offers a rich set of advanced connectivity peripherals including 10/100 Mbps Ethernet MAC supporting IEEE 1588 and dual CAN. With a singleprecision FPU, advanced analog features, as well as a full set of timing and control functions, the SAM4E is the ideal solution for industrial automation, home and building control, machine-to-machine communications, automotive aftermarket and energy management applications. The peripheral set includes a full-speed USB device port with embedded transceiver, a 10/100 Mbps Ethernet MAC supporting IEEE 1588, a high-speed MCI for SDIO/SD/MMC, an external bus interface featuring a static memory controller providing connection to SRAM, PSRAM, NOR Flash, LCD module and NAND Flash, a parallel I/O capture mode for camera interface, hardware acceleration for AES256, two USARTs, two UARTs, two TWIs, three SPIs, as well as a 4-channel PWM, nine general-purpose 16-bit timers with stepper motor and quadrature decoder logic support , one RTC, two analog front end interfaces 16-bit ADC, DAC, MUX and PGA , one 12-bit DAC 2-ch and an analog comparator.

Core with 2 Kbytes Cache running at up to 120 MHz 1 Memory Protection Unit MPU DSP Instruction Floating Point Unit FPU Instruction Set

Memories Up to 1024 Kbytes Embedded Flash 128 Kbytes Embedded SRAM 16 Kbytes ROM with Embedded Boot Loader Routines UART and IAP Routines Static Memory Controller SMC SRAM, NOR, NAND Support. NAND Flash Controller.

System Embedded Voltage Regulator for Single Supply Operation Power-on-Reset POR , Brown-out Detector BOD and Dual Watchdog for Safe Operation Quartz or Ceramic Resonator Oscillators 3 to 20 MHz Main Power with Failure Detection and Optional Lowpower kHz for RTC or Device Clock RTC with Gregorian and Persian Calendar Mode, Waveform Generation in Low-power Modes RTC Clock Calibration Circuitry for kHz Crystal Frequency Compensation High Precision 4/8/12 MHz Factory Trimmed Internal RC Oscillator with 4 MHz Default Frequency for Device Startup. In-application Trimming Access for Frequency Adjustment Slow Clock Internal RC Oscillator as Permanent Low-power Mode Device Clock One PLL up to 240 MHz for Device Clock and for USB Temperature Sensor Up to 2 Peripheral DMA Controller with up to 33 Channels PDC One 4-channel DMA Controller

Low-power Modes Sleep and Backup Modes Ultra Low-power RTC

Peripherals Two USARTs with USART1 ISO7816, RS-485, SPI, Manchester and Modem Modes USB Device Full Speed 12 Mbits , 2668 byte FIFO, up to 8 Endpoints. On-chip Transceiver Two 2-wire UARTs Two-wire Interfaces TWI High-speed Multimedia Card Interface SDIO/SD Card/MMC One Master/Slave Serial Peripheral Interface SPI with Chip Select Signals Three 3-Channel 32-bit Timer/Counter with Capture, Waveform, Compare and PWM Mode. Quadrature Decoder Logic and 2-bit Gray Up/Down Counter for Stepper Motor 32-bit Real-time Timer and RTC with Calendar and Alarm Features One Ethernet MAC EMAC 10/100 Mbps in MII mode only with Dedicated DMA and Support for IEEE1588, Wake-on-LAN Two CAN Controllers with eight Mailboxes 4-channel 16-bit PWM with Complementary Output, Fault Input, 12-bit Dead Time Generator Counter for Motor Control Real-time Event Management

SAM4E [DATASHEET]

Cryptography AES 256-bit Key Algorithm compliant with FIPS Publication 197

Analog AFE Analog Front End 2x16-bit ADC, up to 24-channels, Differential Input Mode, Programmable Gain Stage, Auto Calibration and Automatic Offset Correction One 2-channel 12-bit 1 Msps DAC One Analog Comparator with Flexible Input Selection, Selectable Input Hysteresis

I/O Up to 117 I/O Lines with External Interrupt Capability Edge or Level Sensitivity , Debouncing, Glitch Filtering and On-die Series Resistor Termination Bidirectional Pad, Analog I/O, Programmable Pull-up/Pull-down Five 32-bit Parallel Input/Output Controllers, Peripheral DMA Assisted Parallel Capture Mode

Packages 144-ball LFBGA, 10x10 mm, pitch mm 100-ball TFBGA, 9x9 mm, pitch mm 144-lead LQFP, 20x20 mm, pitch mm 100-lead LQFP, 14x14 mm, pitch mm

Note 120 MHz -40/+105°C, VDDCORE = 1.2V or using internal voltage regulator

SAM4E [DATASHEET]

Configuration Summary

The SAM4E series devices differ in memory size, package and features. Table 1-1 summarizes the configurations of the device family.

Table Configuration Summary

SAM4E16E

SAM4E8E

Flash
1024 Kbytes
512 Kbytes

SRAM
128 Kbytes

CMCC
2 Kbytes

LFBGA 144

Package

LQFP 144

Number of PIOs

External Bus Interface

Analog Front End AFE0
8-bit Data, 4 Chip Selects, 24-bit Address

Up to 16 bits 1 16 8 ch 2

EMAC
12-bit DAC Timer
2 ch. 9 4

PDC Channels USART/ UART
24 +9 2/2 6

Full Speed
The different ordering requirements for Device and Strongly-ordered memory mean that the memory system can buffer a write to Device memory, but must not buffer a write to Strongly-ordered memory. Additional Memory Attributes

Shareable For a shareable memory region, the memory system provides data synchronization between bus masters in a system with multiple bus masters, for example, a processor with a DMA controller. Strongly-ordered memory is always shareable. If multiple bus masters can access a non-shareable memory region, the software must ensure data coherency between the bus masters.

Execute Never XN Means the processor prevents instruction accesses. A fault exception is generated only on execution of an instruction executed from an XN region.
Memory System Ordering of Memory Accesses
For most memory accesses caused by explicit memory access instructions, the memory system does not guarantee that the order in which the accesses complete matches the program order of the instructions, providing this does not affect the behavior of the instruction sequence. Normally, if correct program execution depends on two memory accesses completing in program order, the software must insert a memory barrier instruction between the memory access instructions, see “Software Ordering of Memory Accesses”
However, the memory system does guarantee some ordering of accesses to Device and Strongly-ordered memory. For two memory access instructions A1 and A2, if A1 occurs before A2 in program order, the ordering of the memory accesses is described below.
Table Ordering of the Memory Accesses Caused by Two Instructions

Device Access

Strongly-

Normal
ordered

Access

Non-shareable

Access

Normal Access

Device access, nonshareable

Device access, shareable

Strongly-ordered access

Where:
Means that the memory system does not guarantee the ordering of the accesses.
< Means that accesses are observed in program order, that is, A1 is always observed before A2.

SAM4E [DATASHEET] 59

Behavior of Memory Accesses The behavior of accesses to each region in the memory map is:

Table Memory Access Behavior

Address Range

Memory Region

Memory Type

XN Description
- Code

Normal 1 -

Executable region for program code. Data can also be put here.
- SRAM

Normal 1 -

Executable region for data. Code can also be put here.

This region includes bit band and bit band alias areas, see Table
- Peripheral

Device 1

This region includes bit band and bit band alias areas, see Table
- External RAM

Normal 1 -

Executable region for data.
- External device

Device 1 XN External Device memory

Private Peripheral Bus

Stronglyordered 1

This region includes the NVIC, System timer, and system control block.
- Reserved

Device 1 XN Reserved

Note See “Memory Regions, Types and Attributes” for more information.

The Code, SRAM, and external RAM regions can hold programs. However, ARM recommends that programs always use the Code region. This is because the processor has separate buses that enable instruction fetches and data accesses to occur simultaneously.

The MPU can override the default memory access behavior described in this section. For more information, see “Memory Protection Unit MPU ” Additional Memory Access Constraints For Caches and Shared Memory

When a system includes caches or shared memory, some memory regions have additional access constraints, and some regions are subdivided, as Table 12-5 shows:

Table Memory Region Shareability and Cache Policies

Address Range Memory Region

Memory Type

Shareability

Code

Normal 1

SRAM

Normal 1
Software Ordering of Memory Accesses

The order of instructions in the program flow does not always guarantee the order of the corresponding memory transactions. This is because:

The processor can reorder some memory accesses to improve efficiency, providing this does not affect the behavior of the instruction sequence.

The processor has multiple bus interfaces Memory or devices in the memory map have different wait states Some memory accesses are buffered or speculative.
“Memory System Ordering of Memory Accesses” describes the cases where the memory system guarantees the order of memory accesses. Otherwise, if the order of memory accesses is critical, the software must include memory barrier instructions to force that ordering. The processor provides the following memory barrier instructions DMB

The Data Memory Barrier DMB instruction ensures that outstanding memory transactions complete before subsequent memory transactions. See “DMB” DSB

The Data Synchronization Barrier DSB instruction ensures that outstanding memory transactions complete before subsequent instructions execute. See “DSB” ISB

The Instruction Synchronization Barrier ISB ensures that the effect of all completed memory transactions is recognizable by subsequent instructions. See “ISB” MPU Programming

Use a DSB followed by an ISB instruction or exception return to ensure that the new MPU configuration is used by subsequent instructions.

SAM4E [DATASHEET] 61

Bit-banding

A bit-band region maps each word in a bit-band alias region to a single bit in the bit-band region. The bit-band regions occupy the lowest 1 MB of the SRAM and peripheral memory regions.

The memory map has two 32 MB alias regions that map to two 1 MB bit-band regions Accesses to the 32 MB SRAM alias region map to the 1 MB SRAM bit-band region, as shown in Table Accesses to the 32 MB peripheral alias region map to the 1 MB peripheral bit-band region, as shown in Table

Table SRAM Memory Bit-banding Regions

Address Range

Memory Region

Instruction and Data Accesses

SRAM bit-band region

Direct accesses to this memory range behave as SRAM memory accesses, but this region is also bit-addressable through bit-band alias.

SRAM bit-band alias

Data accesses to this region are remapped to bit-band region. A write operation is performed as read-modifywrite. Instruction accesses are not remapped.

Table Peripheral Memory Bit-banding Regions

Address Range

Memory Region

Instruction and Data Accesses

Peripheral bit-band alias

Direct accesses to this memory range behave as peripheral memory accesses, but this region is also bitaddressable through bit-band alias.

Peripheral bit-band region

Data accesses to this region are remapped to bit-band region. A write operation is performed as read-modifywrite. Instruction accesses are not permitted.

Notes A word access to the SRAM or peripheral bit-band alias regions map to a single bit in the SRAM or peripheral bit-band region.

Bit-band accesses can use byte, halfword, or word transfers. The bit-band transfer size matches the transfer size of the instruction making the bit-band access.

The following formula shows how the alias region maps onto the bit-band region bit_word_offset = byte_offset x 32 + bit_number x 4 bit_word_addr = bit_band_base + bit_word_offset
where Bit_word_offset is the position of the target bit in the bit-band memory region. Bit_word_addr is the address of the word in the alias memory region that maps to the targeted bit. Bit_band_base is the starting address of the alias region. Byte_offset is the number of the byte in the bit-band region that contains the targeted bit. Bit_number is the bit position, 0-7, of the targeted bit.

Figure 12-4 shows examples of bit-band mapping between the SRAM bit-band alias region and the SRAM bit-band region:

The alias word at 0x23FFFFE0 maps to bit[0] of the bit-band byte at 0x23FFFFE0 = + +

The alias word at maps to bit[7] of the bit-band byte at = + +

The alias word at maps to bit[0] of the bit-band byte at = + 0*32 + 0

SAM4E [DATASHEET] 62

The alias word at 0x2200001C maps to bit[7] of the bit-band byte at 0x2200001C = 0*32 +

Figure Bit-band Mapping
32 MB alias region
0x23FFFFEC 0x23FFFFE8 0x23FFFFE4 0x23FFFFE0
0x2200001C 0x22000018 0x22000014 0x22000010
1 MB SRAM bit-band region
76543210765432107654321076543210
DMB acts as a data memory barrier. It ensures that all explicit memory accesses that appear, in program order, before the DMB instruction are completed before any explicit memory accesses that appear, in program order, after the DMB instruction. DMB does not affect the ordering or execution of instructions that do not access memory.

Condition Flags

This instruction does not change the flags.

Examples DMB Data Memory Barrier

SAM4E [DATASHEET]

Data Synchronization Barrier.

Syntax
where:
cond
is an optional condition code, see “Conditional Execution”

Operation

DSB acts as a special data synchronization memory barrier. Instructions that come after the DSB, in program order, do not execute until the DSB instruction completes. The DSB instruction completes when all explicit memory accesses before it complete.

Condition Flags

This instruction does not change the flags.

Examples DSB Data Synchronisation Barrier

Instruction Synchronization Barrier.

Syntax
where:
cond
is an optional condition code, see “Conditional Execution”

Operation

ISB acts as an instruction synchronization barrier. It flushes the pipeline of the processor, so that all instructions following the ISB are fetched from cache or memory again, after the ISB instruction has been completed.

Condition Flags

This instruction does not change the flags.

Examples ISB Instruction Synchronisation Barrier

SAM4E [DATASHEET]

Move the contents of a special register to a general-purpose register.

Syntax Rd, spec_reg
where:
cond
is an optional condition code, see “Conditional Execution”
is the destination register.
spec_reg
can be any of APSR, IPSR, EPSR, IEPSR, IAPSR, EAPSR, PSR, MSP, PSP, PRIMASK, BASEPRI, BASEPRI_MAX, FAULTMASK, or CONTROL.

Operation

Use MRS in combination with MSR as part of a read-modify-write sequence for updating a PSR, for example to clear the Q flag.

In process swap code, the programmers model state of the process being swapped out must be saved, including relevant PSR contents. Similarly, the state of the process being swapped in must also be restored. These operations use MRS in the state-saving instruction sequence and MSR in the state-restoring instruction sequence.

Note BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction.

See “MSR”

Restrictions

Rd must not be SP and must not be PC.
Byte ordering scheme in which bytes of decreasing significance in a data word are stored at increasing addresses in memory. See also “Byte-invariant” , “Endianness” , “Little-endian LE ”

Memory in which a byte or halfword at a word-aligned address is the most significant byte or halfword within the word at that address, a byte at a halfword-aligned address is the most significant byte within the halfword at that address. See also “Little-endian memory”

Breakpoint

A breakpoint is a mechanism provided by debuggers to identify an instruction at which program execution is to be halted. Breakpoints are inserted by the programmer to enable inspection of register contents, memory locations, variable values at fixed points in the program execution to test that the program is operating correctly. Breakpoints are removed after the program is successfully tested.

SAM4E [DATASHEET]

Byte-invariant

In a byte-invariant system, the address of each byte of memory remains unchanged when switching between little-endian and big-endian operation. When a data item larger than a byte is loaded from or stored to memory, the bytes making up that data item are arranged into the correct order depending on the endianness of the memory access. An ARM byte-invariant implementation also supports unaligned halfword and word memory accesses. It expects multi-word accesses to be word-aligned.

Cache Condition field

A block of on-chip or off-chip fast access memory locations, situated between the processor and main memory, used for storing and retrieving copies of often used instructions, data, or instructions and data. This is done to greatly increase the average speed of memory accesses and so improve processor performance.

A four-bit field in an instruction that specifies a condition under which the instruction can execute.

Conditional execution Context Coprocessor

If the condition code flags indicate that the corresponding condition is true when the instruction starts executing, it executes normally. Otherwise, the instruction does nothing.

The environment that each process operates in for a multitasking operating system. In ARM processors, this is limited to mean the physical address range that it can access in memory and the associated memory access permissions.

A processor that supplements the main processor. Cortex-M4 does not support any coprocessors.

Debugger

Direct Memory Access DMA Doubleword

A debugging system that includes a program, used to detect, locate, and correct software faults, together with custom hardware that supports software debugging.

An operation that accesses main memory directly, without the processor performing any accesses to the data concerned.

A 64-bit data item. The contents are taken as being an unsigned integer unless otherwise stated.

Doubleword-aligned Endianness

A data item having a memory address that is divisible by eight.
Byte ordering. The scheme that determines the order that successive bytes of a data word are stored in memory. An aspect of the system’s memory mapping. See also “Little-endian LE ” and “Big-endian BE ”

SAM4E [DATASHEET]

Exception

An event that interrupts program execution. When an exception occurs, the processor suspends the normal program flow and starts execution at the address indicated by the corresponding exception vector. The indicated address contains the first instruction of the handler for the exception.

An exception can be an interrupt request, a fault, or a software-generated system exception. Faults include attempting an invalid memory access, attempting to execute an instruction in an invalid processor state, and attempting to execute an undefined instruction.

Exception service routine

See “Interrupt handler”

Exception vector Flat address mapping

See “Interrupt vector”

A system of organizing memory in which each physical address in the memory space is the same as the corresponding virtual address.

Halfword Illegal instruction Implementation-defined

A 16-bit data item.

An instruction that is architecturally Undefined.

The behavior is not architecturally defined, but is defined and documented by individual implementations.

Implementation-specific

The behavior is not architecturally defined, and does not have to be documented by individual implementations. Used when there are a number of implementation options available and the option chosen does not affect software compatibility.

Index register

In some load and store instruction descriptions, the value of this register is used as an offset to be added to or subtracted from the base register value to form the address that is sent to memory. Some addressing modes optionally enable the index register value to be shifted prior to the addition or subtraction.

See also “Base register”

Instruction cycle count Interrupt handler Interrupt vector

The number of cycles that an instruction occupies the Execute stage of the pipeline.

A program that control of the processor is passed to when an interrupt occurs.

One of a number of fixed addresses in low memory, or in high memory if high vectors are configured, that contains the first instruction of the corresponding interrupt handler.

SAM4E [DATASHEET]

Little-endian LE Little-endian memory
Byte ordering scheme in which bytes of increasing significance in a data word are stored at increasing addresses in memory. See also “Big-endian BE ” , “Byte-invariant” , “Endianness”

Memory in which a byte or halfword at a word-aligned address is the least significant byte or halfword within the word at that address, a byte at a halfword-aligned address is the least significant byte within the halfword at that address. See also “Big-endian memory”

Load/store architecture

A processor architecture where data-processing operations only operate on register contents, not directly on memory contents.

Memory Protection Unit MPU

Prefetching

Hardware that controls access permissions to blocks of memory. An MPU does not perform any address translation.

In pipelined processors, the process of fetching instructions from memory to fill up the pipeline before the preceding instructions have finished executing. Prefetching an instruction does not mean that the instruction has to be executed.

Preserved Read Region Reserved

Preserved by writing the same value back that has been previously read from the same field on the same processor.

Reads are defined as memory operations that have the semantics of a load. Reads include the Thumb instructions LDM, LDR, LDRSH, LDRH, LDRSB, LDRB, and POP.

A partition of memory space.

A field in a control register or instruction format is reserved if the field is to be defined by the implementation, or produces Unpredictable results if the contents of the field are not zero. These fields are reserved for use in future extensions of the architecture or are implementation-specific. All reserved bits not used by the implementation must be written as 0 and read as

Thread-safe Thumb instruction

In a multi-tasking environment, thread-safe functions use safeguard mechanisms when accessing shared resources, to ensure correct operation without the risk of shared access conflicts.

One or two halfwords that specify an operation for a processor to perform. Thumb instructions must be halfword-aligned.

SAM4E [DATASHEET]

Unaligned

Undefined Unpredictable Warm reset

WA WB Word Write-allocate WA Write-back WB

Write buffer Write-through WT

A data item stored at an address that is not divisible by the number of bytes that defines the data size is said to be unaligned. For example, a word stored at an address that is not divisible by four.

Indicates an instruction that generates an Undefined instruction exception.

One cannot rely on the behavior. Unpredictable behavior must not represent security holes. Unpredictable behavior must not halt or hang the processor, or any parts of the system.

Also known as a core reset. Initializes the majority of the processor excluding the debug controller and debug logic. This type of reset is useful if debugging features of a processor.

See “Write-allocate WA ”

See “Write-back WB ”

A 32-bit data item.

Writes are defined as operations that have the semantics of a store. Writes include the Thumb instructions STM, STR, STRH, STRB, and PUSH.

In a write-allocate cache, a cache miss on storing data causes a cache line to be allocated into the cache.

In a write-back cache, data is only written to main memory when it is forced out of the cache on line replacement following a cache miss. Otherwise, writes by the processor only update the cache. This is also known as copyback.

A block of high-speed memory, arranged as a FIFO buffer, between the data cache and main memory, whose purpose is to optimize stores to main memory.

In a write-through cache, data is written to main memory at the same time as the cache is updated.

SAM4E [DATASHEET]

Debug and Test Features

The SAM4 Series Microcontrollers feature a number of complementary debug and test capabilities. The Serial Wire/JTAG Debug Port SWJ-DP combining a Serial Wire Debug Port SW-DP and JTAG Debug JTAG-DP port is used for standard debugging functions, such as downloading code and single-stepping through programs. It also embeds a serial wire trace.

Embedded Characteristics

Debug access to all memory and registers in the system, including Cortex-M4 register bank when the core is running, halted, or held in reset.

Serial Wire Debug Port SW-DP and Serial Wire JTAG Debug Port SWJ-DP debug access Flash Patch and Breakpoint FPB unit for implementing breakpoints and code patches Data Watchpoint and Trace DWT unit for implementing watchpoints, data tracing, and system profiling Instrumentation Trace Macrocell ITM for support of printf style debugging IEEE1149.1 JTAG Boundary-can on All Digital Pins

SAM4E [DATASHEET]

Debug and Test Block Diagram
Ordering Information
Table Ordering Codes for SAM4E Devices
Ordering Code

Flash

MRL Kbytes

ATSAM4E16EA-CU

ATSAM4E16EA-CUR A

ATSAM4E16EA-AU

ATSAM4E16EA-AUR A

ATSAM4E16EA-AN

ATSAM4E16EA-ANR A

ATSAM4E16CA-CU
1024

ATSAM4E16CA-CUR A

ATSAM4E16CA-AU

ATSAM4E16CA-AUR A

ATSAM4E16CA-AN

ATSAM4E16CA-ANR A

ATSAM4E8EA-CU

ATSAM4E8EA-CUR

ATSAM4E8EA-AU

ATSAM4E8EA-AUR

ATSAM4E8EA-AN

ATSAM4E8EA-ANR

ATSAM4E8CA-CU

ATSAM4E8CA-CUR

ATSAM4E8CA-AU

ATSAM4E8CA-AUR

ATSAM4E8CA-AN

ATSAM4E8CA-ANR

Package LFBGA144 LQFP144 TFBGA100 LQFP100 LFBGA144 LQFP144 TFBGA100 LQFP100

Conditioning Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel Tray Reel

Package Type

Green

Temperature Operating Range

Industrial -40°C to 85°C

Industrial -40°C to 85°C

Industrial -40°C to 105°C

Industrial -40°C to 85°C

Industrial -40°C to 85°C

Industrial -40°C to 105°C

Industrial -40°C to 85°C

Industrial -40°C to 85°C
All devices are marked with the Atmel logo and the ordering code. Additional marking is as follows:

YYWW V

Errata

Watchdog Not Stopped in Wait Mode

When the Watchdog is enabled and the bit WAITMODE = 1 is used to enter wait mode, the watchdog is not halted. If the time spent in Wait Mode is longer than the Watchdog time-out, the device will be reset if Watchdog reset is enabled.

Problem Fix/Workaround When entering wait mode, the Wait For Event WFE instruction of the processor Cortex-M4 must be used with the SLEEPDEEP of the System Control Register SCB_SCR of the Cortex-M = Brownout Detector Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected In active mode or in wait mode, if the Brownout Detector is disabled SUPC_MR BODDIS=1 and power is lost on VDDCORE while VDDIO is powered, the device might not be properly reset and may behave unpredictably.

Problem Fix/Workaround When the Brownout Detector is disabled in active or in wait mode, VDDCORE always needs to be powered.

SAM4E [DATASHEET] 1363

SAM4E [DATASHEET] 1364

Change Request Ref.

Introduction

In “Features” - added information on Two-wire Interface in Peripherals section and Wake-on-LAN for EMAC - changed operating temperature range to 105°C Updated Table 1-1 “Configuration Summary” with TWI information In Section “Package and Pinout”, added the FFPI signals to Table 4-1 “SAM4E 100-ball TFBGA Pinout”,
rfo 9045

Table 4-2 “SAM4E 144-ball LFBGA Pinout”, Table 4-3 “SAM4E 100-lead LQFP Pinout” and Table 4-4 “SAM4E
144-lead LQFP Pinout”.

Updated Section “Low-power Modes”. Added information on WFE.
9073

In Section “General-purpose I/O Lines” on page 21, added information on GPIOs as analog input.
8992

Removed Section “Processor and Architecture”. Removed Sections 11-4 to Reordered introduction
sections.

Removed Note regarding PIOs and 144-pin package at bottom of Table 11-5, “Multiplexing on PIO Controller D 9018 PIOD ,” on page 40 and Table 11-6, “Multiplexing on PIO Controller E PIOE ,” on page

RSTC In Section “Reset Controller Status Register”, RSTTYP information corrected.
8847

RTT:

Added notes in Section “Functional Description”, Section “Real-time Timer Mode Register” and in Section “Real-time Timer Alarm Register”.
9026

RTC In Section “Alarm”, added new information and note. In Section “RTC Accurate Clock Calibration”, updated information on temperature range.
8900, 9027 9033

In Section “RTC Time Alarm Register” and Section “RTC Calendar Alarm Register”, added notes. 9027

WDT In Section “Description”, added information on slow clock at 32 kHz.
8429

In Section “Embedded Characteristics”, added that Watchdog Clock is independent from Processor Clock.

Moved note WDD, WDV from Section “Watchdog Timer Status Register” to Section “Watchdog rfo Timer Mode Register”.

EFC:

In Section “Lock Bit Protection”, added notes on FARG exceeding limits. Updated existing note in Section “GPNVM Bit”.

Added Section “Optimized Partial Programming”. Added note on programming limitations in Section “Write Commands”.
8854 8985

FFPI Removed information throughout on Serial Fast Flash Programming not available for device.
9007

SAM4E [DATASHEET] 1365
Ordering Information
Table 48-1 “Ordering Codes for SAM4E Devices” updated with new ordering codes for parts at 105°C and for rfo tape & reel

Errata Added Section “Errata on SAM4E Devices” that includes Section “Watchdog Not Stopped in Wait 9075 Mode” and Section “Unpredictable Behavior if BOD is Disabled, VDDCORE is Lost and VDDIO is Connected”

SAM4E [DATASHEET] 1367

Change Request Ref.

Introduction:

Updated the section structure and added references to 100-ball TFBGA and 100-lead LQFP packages in:
8580
- Section “Features”
- Table 1-1 “Configuration Summary”
- Figure 2-1 “SAM4E 100-pin Block Diagram”
- Section “100-ball TFBGA Package and Pinout”
- Section “100-lead LQFP Package and Pinout”
- Table 11-1 “PIO available according to Pin Count”

Added Analog Comparator ACC and Reinforced Safety Watchdog Timer RSWDT blocks in Figure 2-2 “SAM4E 144-pin Block Diagram”.
8605/rfo

Updated the description of power supply pins in Section “Power Supplies”.
8644

Updated Figure 11-3 “Power Management Controller Block Diagram”.

Removed RC80M references in Figure 10-1 “System Controller Block Diagram” and Figure 11-2 “Clock Generator Block Diagram”.
8724

Add data on consumption and wake-up time in Table 5-1 “Low-power Mode Configuration Summary”.

Removed “AT91SAM” from the document title and further on in the entire document where appropriate .

Replaced “Cortex ” references with in “Description” and further on in the entire document.

Section “Chip Identification”, replaced “Table SAM4E Chip ID Register” with a cross-reference to rfo the corresponding Table 14-1 “SAM4E Chip ID Registers” Section “Chip Identifier CHIPID ” .

Removed package dimension references in Section “Package and Pinout”.

Added a phrase on the flash write commands usage in Section “Flash Overview” the last paragraph . rfo

Updated package information in Section “Peripheral Signal Multiplexing on I/O Lines”:
- replaced “100/144 pin version” with “144 pin version” in Table 11-4 “Multiplexing on PIO Controller C PIOC ”
- removed “144 pin version” in Table 11-5 “Multiplexing on PIO Controller D PIOD ”

Updated Figure 7-1 “SAM4E Product Mapping”.
8825

Replaced GRX by GRX1 on line PD6 in Table 11-5 “Multiplexing on PIO Controller D PIOD ”.
8897

CHIPID:

Section “Chip Identifier CHIPID User Interface”, updated the ARCH bitfield table in “ARCH Architecture 8603 Identifier” removed rows with not relevant information 0x43, 0x88, 0x89, 0x8A, 0x93, 0x94, and 0x95 .

Section “Embedded Characteristics”, replaced ‘0x0011_0201’ with ‘0x0012_0201’ and ‘0x0011_0209’ with 8851 ‘0x0012_0209’ in Table 14-1 “SAM4E Chip ID Registers”.

Section “Chip ID Extension Register”, updated value in the Flash Size table and removed package references in the Product Number table.

RTT:

Section “Block Diagram”, replaced ‘CLKSRC’ source reference with ‘RTC1HZ’ in Figure 16-1 “Real-time 8574 Timer”.

Updated the 4th and the 8th paragraphs in Section “Functional Description” “Setting the RTC 1 HZ clock to and “The RTTINC bit in RTT_SR is set...” respectively .

Section “Real-time Timer Mode Register”, added notes in “RTTDIS Real-time Timer Disable” and “RTC1HZ Real-Time Clock 1Hz Clock Selection”.
Ordering Codes:
Added references to 100-ball TFBGA and 100-lead LQFP packages in Table 48-1 “Ordering Codes for SAM4E 8580 Devices”.

Initial release

Change Request Ref.

SAM4E [DATASHEET] 1373

SAM4E [DATASHEET] 1374

Table of Contents

Description1

Features 2

Configuration Summary 4

Block Diagram 5

Signal Description 7

Package and Pinout 11
100-ball TFBGA Package and Pinout 11 144-ball LFBGA Package and Pinout 12 100-lead LQFP Package and Pinout 13 144-lead LQFP Package and Pinout 14

Power Considerations 15

Power Supplies 15 Voltage Regulator 15 Typical Powering Schematics 15 Low-power Modes 16 Wake-up Sources 19 Fast Start-up 20

Input/Output Lines 21

General-purpose I/O Lines 21 System I/O Lines 22

Product Mapping 23

Memories 24

Embedded Memories 24 External Memories 28 Cortex-M Cache Controller CMCC 28

Real-time Event Management 29

Embedded Characteristics 29 Real-time Event Mapping List 30

System Controller 31

System Controller and Peripherals Mapping 32 Power-on-Reset, Brownout and Supply Monitor 32 Reset Controller 32

Peripherals 34

Peripheral Identifiers 34 Peripheral Signal Multiplexing on I/O Lines 36

ARM Cortex-M4 43

Description 43

SAM4E [DATASHEET]

Embedded Characteristics 44 Block Diagram 45 Cortex-M4 Models 46 Power Management 75 Cortex-M4 Instruction Set 77 Cortex-M4 Core Peripherals 188 Nested Vectored Interrupt Controller NVIC 189 System Control Block SCB 199 System Timer SysTick 225 Memory Protection Unit MPU 230 Floating Point Unit FPU 243 Glossary 252

Debug and Test Features 257

Description 257 Embedded Characteristics 257 Debug and Test Block Diagram 258 Application Examples 259 Debug and Test Pin Description 260 Functional Description 261

Chip Identifier CHIPID 267

Description 267 Embedded Characteristics 267 Power Management Controller PMC User Interface 268

Reset Controller RSTC 275

Embedded Characteristics 275 Block Diagram 275 Functional Description 275 Reset Controller RSTC User Interface 282

Real-time Timer RTT 287

Description 287 Embedded Characteristics 287 Block Diagram 287 Functional Description 288 Real-time Timer RTT User Interface 290

Reinforced Safety Watchdog Timer RSWDT 295

Description 295 Embedded Characteristics 295 Block Diagram 296 Functional Description 297 Reinforced Safety Watchdog Timer RSWDT User Interface 299

Real-time Clock RTC 303
Ordering Information 1361 Errata on SAM4E Devices 1363

Marking 1363 Errata 1363

SAM4E [DATASHEET] viii

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Datasheet ID: ATSAM4E8CA-AUR 519314