ATPL00B-AZU-Y

ATPL00B-AZU-Y Datasheet

Atmel ATPL00B

Part	Datasheet
ATPL00B-AZU-Y	ATPL00B-AZU-Y (pdf)

Related Parts	Information
ATPL00BSK-99	ATPL00BSK-99
ATPL00BDK-99	ATPL00BDK-99

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Atmel ATPL00B FSK Power Line Communications SoC DATASHEET Core ADD8051C3A enhanced 8051 core Speedups up to x5 vs. standard 8051 microcontroller 128Kbytes internal SRAM In-circuit serial flash programming Auto boot-loading program from serial flash Media Access Control Convolutional and block FEC channel coding, Viterbi decoding Hardware CRC error detection and FEC error correction By-pass mode to support earlier no-MAC FSK modem software Modem Power Line Carrier Modem for 50 and 60 Hz mains Carrier Frequency 132.5KHz Baud rate Selectable 600 to 4800 bps Half Duplex communication Receiver Sensitivity Up to 44dBuVrms Peripherals Three 2-wire UARTs Two SPI. SPI to serial flash and External RTC. Buffered SPI to external metering IC Programmable Watchdog Quad dimmer in/out Up to 20 I/O lines Package 144-lead LQFP, 16 x 16 mm, pitch mm Pb-free and RoHS compliant Typical Applications Automated Meter Reading AMR & Advanced Meter Management AMM Street lighting Home Automation 43028A-ATPL - 9/12 The ATPL00B is a Power Line Communications System on Chip that implements a full PLC node using FSK modulations and includes a hardwired Medium Access Controller ADD1210 . It has been developed to reduce the CPU computational load in PLC systems. Thus, the microcontroller is free to be used in the applications tasks. MAC functional capabilities of ATPL00B performed in ADD1210 Medium Access Controller involve the construction of message packets, adding convolutional or FEC Forward Error Correction codes to bytes and FCS Frame Check Sequence to packets. In reception, the MAC provides frame detection and Viterbi decoding or FCS and FEC correction. ATPL00B MAC design is versatile and allows users to create a wide range of datagram structures. The MAC shall be set in a bypass mode allowing direct connection between the microcontroller and the modem to support old FSK software that doesn‟t include the MAC. ATPL00B PLC modem ADD1310 is based on a Frequency-shift keying FSK Modulation Scheme supporting Minimum Shift Frequency MSK in the C-Band with carrier frequency of 132,5KHz. It shall work using a single power supply of 3.3V and a few external components, supporting several Analog Front End AFE configurations suitable for Home Automation purposes. It shall replace the traditional analog PLC modem and can use the same software libraries or a simplified version if the hardwired MAC is used. The PLC modem fits CENELEC C-band and EN50065-1 access rules, and has receiver sensitivity up to 44dBuVrms 158 uVrms . ATPL00B core ADD8051C3A includes all features of the standard 8051, with an average speed up to x5 and some additional features. The microcontroller includes some specific peripherals as 4 input / 4 output dimmers for power regulation phase angle control , and also capable of generating PulseWidth Modulation PWM control. A flash program loader allows downloading the microcontroller program in a standard SPI serial flash memory and executing it from internal SRAM. In the start-up process, the program is uploaded from serial flash to the internal 128Kbytes of SRAM before starting the execution. After that, the free space in the serial flash shall be used to store application data. ATPL00B includes an encryption engine for code protection. Using a larger flash, several programs may be stored at the same time and the microcontroller shall switch from one program to another. This feature could be used to reprogram the SoC using PLC downloading. Atmel ATPL00B [datasheet] 43028A-ATPL - 9/12 Table of Contents Block 6 Package and Pinout 7 144-Lead LQFP Package Outline 7 144-Lead LQFP Pinout 8 Pin 10 Processor and Architecture 17 ADD8051C3A Microcontroller Description 17 Core Pinout Description 18 Memory Organization 19 Program Memory 20 Extended 21 Data Memory 25 SFR Registers 26 Instruction Set 29 Program Status Word 29 Addressing Modes 29 Arithmetic 30 Logical Instructions 31 Data Transfer 33 Boolean Instructions 34 Jump 35 CPU 37 Reset 38 Power Saving Modes 40 Idle Mode 40 Power-Down Mode 40 Interrupts 41 Interrupt Enabling 41 Interrupt Priorities 41 Interrupt Handling 44 I/O Ports 45 I/O Configurations 46 Read-Modify-Write 47 Accessing External 47 Debug 48 Timers 49 Timer 0 and Timer 1 49 Timer Mode 50 Timer Mode 51 Timer Mode 51 Timer Mode 51 Timer 2 52 Capture mode 53 Auto-Reload mode 53 Clock-Out mode 54 Baud rate Generator mode 55 Watchdog timer 56 Standard Serial 58 Serial Port 58 Mode 0 shift register mode 58 Mode 1 8-bit 59 Modes 2 and 3 9-bit UART 59 Serial Port Timers 11, 12 and 14 60 Atmel ATPL00B [datasheet] 43028A-ATPL - 9/12 Serial Peripheral Interfaces SPI0 and SPI1 64 SPI description 64 SPI clock phase, polarity and 66 SPI0 write 68 SPI Modes 68 SPI1 buffer operation 70 Boot Loader 72 Pin Description 73 Flash Programming 74 In-System 74 SPI Flash programming 74 System startup 76 Encrypted firmware requirements 77 Supported Devices 77 Serial Number Device 77 Dimmer Peripheral 78 Ordering Information 150 Atmel ATPL00B [datasheet] 43028A-ATPL - 9/12 Block Diagram Figure ATPL00B 144-pin Block Diagram DEBUG D_INIT RSTA CLKA CLKB INT1 Reset Interface Clock Interface 11.059.200Hz XDATA SRAM RESET Clock DEBUG 8051C3A Core IDATA 128KB SRAM Power Management JTAG Bscan CODE SRAM P1.7 P3 1,2 , P3 3:5 P4 0:7 P5 0:5 TRIAC_ 3 :0 VNR INTA 3:0 INTB 3:0 INTC 3:0 INTD 3:0 GENERAL PURPOSE I/O DIMMER PERIPHERAL Vref1 Vref2 EMIT 12:0 ENABLE DC_COMP D_IN D_NIN REC 8:1 MEDIUM ACCESS CONTROL PLC MODEM BOOT LOADER SPI0 SPI1 UART0 UART1 UART2 TIMER0 TIMER1 TIMER2 T11, T12, T14 WATCHDOG VDD VSSO LDO_PD VDEO TDI TDO TCK TRST TMS /PROG SECURED SSN MISO, MOSI, CLK, SS MISO1, MOSI1, CLK1, SS1 Rx0, Tx0 Ordering Information Table Atmel ATPL00B Ordering Codes Atmel Ordering Code ATPL00B-AZU-Y Package 144 LQFP Package Type Pb-Free Temperature Range Industrial -40ºC to 85º Atmel Designator AT=Atmel Product Family PL=Power Line Communications Device Designator ATPL00B-AZU-Yxx Customer marking Shipping Carrier Option Y = Tray Package Device Grade or Wafer/Die Thickness U = Lead free Pb-free Industrial temperature range -40°C to +85°C Package Option AZ = 144LQFP Atmel ATPL00B [datasheet] 150 43028A-ATPL - 9/12 Date 09/27/2012 Comments Initial Release Atmel ATPL00B [datasheet] 151 43028A-ATPL - 9/12 Atmel Corporation 1600 Technology Drive San Jose, CA 95110 USA Tel +1 408 441-0311 Fax +1 408 487-2600 Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel +852 2245-6100 Fax +852 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel +49 89-31970-0 Fax +49 89-3194621 Atmel Japan G.K. 16F Shin-Osaki Kangyo Building 1-6-4 Osaki Shinagawa-ku, Tokyo 141-0032 JAPAN Tel +81 3 6417-0300 Fax +81 3 6417-0370 Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others. Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.

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Atmel ATPL00B

FSK Power Line Communications SoC

DATASHEET

Core ADD8051C3A enhanced 8051 core Speedups up to x5 vs. standard 8051 microcontroller
128Kbytes internal SRAM In-circuit serial flash programming Auto boot-loading program from serial flash Media Access Control

Convolutional and block FEC channel coding, Viterbi decoding Hardware CRC error detection and FEC error correction By-pass mode to support earlier no-MAC FSK modem software Modem Power Line Carrier Modem for 50 and 60 Hz mains Carrier Frequency 132.5KHz Baud rate Selectable 600 to 4800 bps Half Duplex communication Receiver Sensitivity Up to 44dBuVrms Peripherals Three 2-wire UARTs Two SPI. SPI to serial flash and External RTC. Buffered SPI to external metering IC Programmable Watchdog Quad dimmer in/out Up to 20 I/O lines Package 144-lead LQFP, 16 x 16 mm, pitch mm Pb-free and RoHS compliant Typical Applications Automated Meter Reading AMR & Advanced Meter Management AMM Street lighting Home Automation
43028A-ATPL - 9/12

The ATPL00B is a Power Line Communications System on Chip that implements a full PLC node using FSK modulations and includes a hardwired Medium Access Controller ADD1210 . It has been developed to reduce the CPU computational load in PLC systems. Thus, the microcontroller is free to be used in the applications tasks.

MAC functional capabilities of ATPL00B performed in ADD1210 Medium Access Controller involve the construction of message packets, adding convolutional or FEC Forward Error Correction codes to bytes and FCS Frame Check Sequence to packets. In reception, the MAC provides frame detection and Viterbi decoding or FCS and FEC correction.

ATPL00B MAC design is versatile and allows users to create a wide range of datagram structures. The MAC shall be set in a bypass mode allowing direct connection between the microcontroller and the modem to support old FSK software that doesn‟t include the MAC.

ATPL00B PLC modem ADD1310 is based on a Frequency-shift keying FSK Modulation Scheme supporting Minimum Shift Frequency MSK in the C-Band with carrier frequency of 132,5KHz. It shall work using a single power supply of 3.3V and a few external components, supporting several Analog Front End AFE configurations suitable for Home Automation purposes. It shall replace the traditional analog PLC modem and can use the same software libraries or a simplified version if the hardwired MAC is used. The PLC modem fits CENELEC C-band and EN50065-1 access rules, and has receiver sensitivity up to 44dBuVrms 158 uVrms .

ATPL00B core ADD8051C3A includes all features of the standard 8051, with an average speed up to x5 and some additional features.

The microcontroller includes some specific peripherals as 4 input / 4 output dimmers for power regulation phase angle control , and also capable of generating PulseWidth Modulation PWM control.

A flash program loader allows downloading the microcontroller program in a standard SPI serial flash memory and executing it from internal SRAM. In the start-up process, the program is uploaded from serial flash to the internal 128Kbytes of SRAM before starting the execution. After that, the free space in the serial flash shall be used to store application data. ATPL00B includes an encryption engine for code protection. Using a larger flash, several programs may be stored at the same time and the microcontroller shall switch from one program to another. This feature could be used to reprogram the SoC using PLC downloading.

Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12

Table of Contents

Block 6

Package and Pinout 7
144-Lead LQFP Package Outline 7 144-Lead LQFP Pinout 8

Pin 10

Processor and Architecture 17

ADD8051C3A Microcontroller Description 17 Core Pinout Description 18 Memory Organization 19

Program Memory 20 Extended 21 Data Memory 25 SFR Registers 26 Instruction Set 29 Program Status Word 29 Addressing Modes 29 Arithmetic 30 Logical Instructions 31 Data Transfer 33 Boolean Instructions 34 Jump 35 CPU 37 Reset 38 Power Saving Modes 40 Idle Mode 40 Power-Down Mode 40 Interrupts 41 Interrupt Enabling 41 Interrupt Priorities 41 Interrupt Handling 44 I/O Ports 45 I/O Configurations 46 Read-Modify-Write 47 Accessing External 47 Debug 48

Timers 49

Timer 0 and Timer 1 49 Timer Mode 50 Timer Mode 51 Timer Mode 51 Timer Mode 51

Timer 2 52 Capture mode 53 Auto-Reload mode 53 Clock-Out mode 54 Baud rate Generator mode 55

Watchdog timer 56

Standard Serial 58

Serial Port 58 Mode 0 shift register mode 58 Mode 1 8-bit 59 Modes 2 and 3 9-bit UART 59

Serial Port Timers 11, 12 and 14 60

Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12

Serial Peripheral Interfaces SPI0 and SPI1 64

SPI description 64 SPI clock phase, polarity and 66 SPI0 write 68

SPI Modes 68 SPI1 buffer operation 70

Boot Loader 72

Pin Description 73 Flash Programming 74

In-System 74 SPI Flash programming 74 System startup 76 Encrypted firmware requirements 77 Supported Devices 77

Serial Number Device 77

Dimmer Peripheral 78
Ordering Information 150

Atmel ATPL00B [datasheet]
43028A-ATPL - 9/12

Block Diagram

Figure ATPL00B 144-pin Block Diagram

DEBUG D_INIT

RSTA

CLKA CLKB

INT1

Reset Interface

Clock Interface
11.059.200Hz

XDATA SRAM

RESET Clock

DEBUG
8051C3A Core

IDATA
128KB SRAM

Power Management

JTAG Bscan

CODE SRAM

P1.7 P3 1,2 , P3 3:5

P4 0:7 P5 0:5

TRIAC_ 3 :0 VNR

INTA 3:0 INTB 3:0 INTC 3:0 INTD 3:0

GENERAL PURPOSE I/O

DIMMER

PERIPHERAL

Vref1 Vref2

EMIT 12:0 ENABLE

DC_COMP D_IN

D_NIN REC 8:1

MEDIUM ACCESS CONTROL

PLC MODEM

BOOT LOADER

SPI0 SPI1 UART0 UART1 UART2 TIMER0 TIMER1 TIMER2

T11, T12, T14

WATCHDOG

VDD VSSO LDO_PD VDEO

TDI TDO TCK TRST TMS
/PROG SECURED SSN MISO, MOSI, CLK, SS MISO1, MOSI1, CLK1, SS1 Rx0, Tx0
Ordering Information
Table Atmel ATPL00B Ordering Codes
Atmel Ordering Code ATPL00B-AZU-Y

Package 144 LQFP

Package Type Pb-Free

Temperature Range Industrial -40ºC to 85º

Atmel Designator

AT=Atmel

Product Family

PL=Power Line Communications

Device Designator

ATPL00B-AZU-Yxx

Customer marking

Shipping Carrier Option

Y = Tray

Package Device Grade or Wafer/Die Thickness

U = Lead free Pb-free Industrial temperature range -40°C to +85°C

Package Option

AZ = 144LQFP

Atmel ATPL00B [datasheet] 150
43028A-ATPL - 9/12

Date 09/27/2012

Comments Initial Release

Atmel ATPL00B [datasheet] 151
43028A-ATPL - 9/12

Atmel Corporation 1600 Technology Drive San Jose, CA 95110 USA Tel +1 408 441-0311 Fax +1 408 487-2600

Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel +852 2245-6100 Fax +852 2722-1369

Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel +49 89-31970-0 Fax +49 89-3194621

Atmel Japan G.K. 16F Shin-Osaki Kangyo Building 1-6-4 Osaki Shinagawa-ku, Tokyo 141-0032 JAPAN Tel +81 3 6417-0300 Fax +81 3 6417-0370

Atmel logo and combinations thereof, and others are registered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

Disclaimer The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS OF SALES LOCATED ON THE ATMEL WEBSITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDENTAL DAMAGES INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS AND PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and products descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life.

More datasheets: 2N5770_D27Z | 2N5770_D26Z | 2N5770_D75Z | 2N5770 | 2N5770_D74Z | M213404 SL005 | M213404 SL002 | M213404 SL001 | ATPL00BSK-99 | ATPL00BDK-99

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Datasheet ID: ATPL00B-AZU-Y 519269