ATMEGA8-16PU

ATMEGA8-16PU Datasheet

23 Programmable I/O Lines 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF<br>• Operating Voltages - 5.5V ATmega8L - 5.5V ATmega8<br>• Speed Grades 0 - 8 MHz ATmega8L 0 - 16 MHz ATmega8<br>• Power Consumption at 4 Mhz, 3V, 25°C Active mA Idle Mode mA Power-down Mode µA

Part	Datasheet
ATMEGA8-16PU	ATMEGA8-16PU (pdf)

Related Parts	Information
ATMEGA8L-8AU	ATMEGA8L-8AU
ATMEGA8L-8MU	ATMEGA8L-8MU
ATMEGA8L-8PU	ATMEGA8L-8PU

PDF Datasheet Preview
• High-performance, Low-power 8-bit Microcontroller • Advanced RISC Architecture 130 Powerful Instructions Most Single-clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16 MHz On-chip 2-cycle Multiplier • High Endurance Non-volatile Memory segments 8K Bytes of In-System Self-programmable Flash program memory 512 Bytes EEPROM 1K Byte Internal SRAM Write/Erase Cycles 10,000 Flash/100,000 EEPROM 1 3 Data retention 20 years at 85°C/100 years at 25°C 2 3 Optional Boot Code Section with Independent Lock Bits In-System Programming by On-chip Boot Program True Read-While-Write Operation Programming Lock for Software Security • Peripheral Features Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode Real Time Counter with Separate Oscillator Three PWM Channels 8-channel ADC in TQFP and QFN/MLF package Eight Channels 10-bit Accuracy 6-channel ADC in PDIP package Six Channels 10-bit Accuracy Byte-oriented Two-wire Serial Interface Programmable Serial USART Master/Slave SPI Serial Interface Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator • Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Five Sleep Modes Idle, ADC Noise Reduction, Power-save, Power-down, and Standby • I/O and Packages 23 Programmable I/O Lines 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF • Operating Voltages - 5.5V ATmega8L - 5.5V ATmega8 • Speed Grades 0 - 8 MHz ATmega8L 0 - 16 MHz ATmega8 • Power Consumption at 4 Mhz, 3V, 25°C Active mA Idle Mode mA Power-down Mode µA 8-bit with 8K Bytes In-System Programmable Flash ATmega8 ATmega8L Notes At 85°C. Guaranteed after last write cycle. Failure rate less than 1 ppm. Characterized through accelerated tests. Pin Configurations PDIP RESET PC6 1 RXD PD0 2 TXD PD1 3 INT0 PD2 4 INT1 PD3 5 XCK/T0 PD4 6 VCC 7 GND 8 XTAL1/TOSC1 PB6 9 XTAL2/TOSC2 PB7 10 T1 PD5 11 AIN0 PD6 12 AIN1 PD7 13 ICP1 PB0 14 28 PC5 ADC5/SCL 27 PC4 ADC4/SDA 26 PC3 ADC3 25 PC2 ADC2 24 PC1 ADC1 23 PC0 ADC0 22 GND 21 AREF 20 AVCC 19 PB5 SCK 18 PB4 MISO 17 PB3 MOSI/OC2 16 PB2 SS/OC1B 15 PB1 OC1A TQFP Top View 32 PD2 INT0 31 PD1 TXD 30 PD0 RXD 29 PC6 RESET 28 PC5 ADC5/SCL 27 PC4 ADC4/SDA 26 PC3 ADC3 25 PC2 ADC2 INT1 PD3 1 XCK/T0 PD4 2 GND 3 VCC 4 GND 5 VCC 6 XTAL1/TOSC1 PB6 7 XTAL2/TOSC2 PB7 8 24 PC1 ADC1 23 PC0 ADC0 22 ADC7 21 GND 20 AREF 19 ADC6 18 AVCC 17 PB5 SCK T1 PD5 9 AIN0 PD6 10 AIN1 PD7 11 ICP1 PB0 12 OC1A PB1 13 SS/OC1B PB2 14 MOSI/OC2 PB3 15 MISO PB4 16 MLF Top View 32 PD2 INT0 31 PD1 TXD 30 PD0 RXD 29 PC6 RESET 28 PC5 ADC5/SCL 27 PC4 ADC4/SDA 26 PC3 ADC3 25 PC2 ADC2 INT1 PD3 1 XCK/T0 PD4 2 GND 3 VCC 4 GND 5 VCC 6 XTAL1/TOSC1 PB6 7 XTAL2/TOSC2 PB7 8 2 ATmega8 L T1 PD5 9 AIN0 PD6 10 AIN1 PD7 11 ICP1 PB0 12 OC1A PB1 13 SS/OC1B PB2 14 MOSI/OC2 PB3 15 MISO PB4 16 24 PC1 ADC1 23 PC0 ADC0 22 ADC7 21 GND 20 AREF 19 ADC6 18 AVCC 17 PB5 SCK NOTE The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure good mechanical stability. If the center pad is left unconneted, the package might loosen from the PCB. Overview Block Diagram ATmega8 L The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed. Figure Block Diagram RESET VCC PC0 - PC6 PB0 - PB7 XTAL1 XTAL2 PORTC DRIVERS/BUFFERS Ordering Information Speed MHz Power Supply Ordering Code ATmega8L-8AC ATmega8L-8PC ATmega8L-8MC ATmega8L-8AI ATmega8L-8AU 2 ATmega8L-8PI ATmega8L-8PU 2 ATmega8L-8MI ATmega8L-8MU 2 ATmega8-16AC ATmega8-16PC ATmega8-16MC ATmega8-16AI ATmega8-16AU 2 ATmega8-16PI ATmega8-16PU 2 ATmega8-16MI ATmega8-16MU 2 Package 1 32A 28P3 32M1-A 32A 28P3 32M1-A 32M1-A 32A 28P3 32M1-A 32A 28P3 32M1-A 32M1-A Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances RoHS directive . Also Halide free and fully Green. 32A 28P3 32M1-A Package Type 32-lead, Thin mm Plastic Quad Flat Package TQFP 28-lead, Wide, Plastic Dual Inline Package PDIP 32-pad, 5 x 5 x body, Lead Pitch mm Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF Packaging Information PIN 1 e PIN 1 IDENTIFIER B E1 E A1 A2 L This package conforms to JEDEC reference MS-026, Variation ABA. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. Lead coplanarity is mm maximum. COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOTE Note 2 Note 2 2325 Orchard Parkway R San Jose, CA 95131 32A, 32-lead, 7 x 7 mm Body Size, mm Body Thickness, mm Lead Pitch, Thin Profile Plastic Quad Flat Package TQFP 14 ATmega8 L ATmega8 L 28P3 D PIN 1 SEATING PLANE A1 B2 4 PLACES 0º ~ 15º REF Note Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed mm COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE Note 1 Note 1 TITLE 2325 Orchard Parkway 28P3, 28-lead mm Wide Plastic Dual R San Jose, CA 95131 Inline Package PDIP 09/28/01 28P3 32M1-A Pin 1 ID SIDE VIEW TOP VIEW A2 Pin #1 Notch R BOTTOM VIEW Note JEDEC Standard MO-220, Fig. 2 Anvil Singulation , VHHD-2. Updated “Ordering Information” on page Added note to MLF package in “Pin Configurations” on page Updated “Internal Voltage Reference Characteristics” on page Updated “DC Characteristics” on page ADC4 and ADC5 support 10-bit accuracy. Document updated to reflect this. Updated features in “Analog-to-Digital Converter” on page Updated “ADC Characteristics” on page Removed reference to “External RC Oscillator application note” from “External RC Oscillator” on page Updated “Calibrated Internal RC Oscillator” on page Removed “Preliminary” and TBDs from the datasheet. Renamed ICP to ICP1 in the datasheet. Removed instructions CALL and JMP from the datasheet. Updated tRST in Table 15 on page 38, VBG in Table 16 on page 42, Table 100 on page 244 and Table 102 on page Replaced text “XTAL1 and XTAL2 should be left unconnected NC ” after Table 9 in “Calibrated Internal RC Oscillator” on page Added text regarding XTAL1/XTAL2 and CKOPT Fuse in “Timer/Counter Oscillator” on page Updated Watchdog Timer code examples in “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page Removed bit 4, ADHSM, from “Special Function IO Register SFIOR” on page Added note 2 to Figure 103 on page Updated item 4 in the “Serial Programming Algorithm” on page Added tWD_FUSE to Table 97 on page 239 and updated Read Calibration Byte, Byte 3, in Table 98 on page Updated Absolute Maximum Ratings* and DC Characteristics in “Electrical Characteristics” on page Updated VBOT values in Table 15 on page Updated “ADC Characteristics” on page Updated “ATmega8 Typical Characteristics” on page Updated “Erratas” on page Improved the description of “Asynchronous Timer Clock clkASY” on page Removed reference to the “Multipurpose Oscillator” application note and the “32 kHz Crystal Oscillator” application note, which do not exist. Corrected OCn waveforms in Figure 38 on page Various minor Timer 1 corrections. Various minor TWI corrections. Added note under “Filling the Temporary Buffer Page Loading ” on page 216 about writing to the EEPROM during an SPM Page load. Removed ADHSM completely. Added section “EEPROM Write during Power-down Sleep Mode” on page Removed XTAL1 and XTAL2 description on page 5 because they were already described as part of “Port B PB7..PB0 XTAL1/XTAL2/TOSC1/TOSC2” on page Improved the table under “SPI Timing Characteristics” on page 246 and removed the table under “SPI Serial Programming Characteristics” on page Corrected PC6 in “Alternate Functions of Port C” on page Corrected PB6 and PB7 in “Alternate Functions of Port B” on page Corrected Mbps to kbps under “Examples of Baud Rate Setting” on page Added information about PWM symmetry for Timer 2 in “Phase Correct PWM Mode” on page Added thick lines around accessible registers in Figure 76 on page Changed “will be ignored” to “must be written to zero” for unused Z-pointer bits under “Performing a Page Write” on page Added note for RSTDISBL Fuse in Table 87 on page Updated drawings in “Packaging Information” on page 20 ATmega8 L ATmega8 L Changed the Endurance on the Flash to 10,000 Write/Erase Cycles. Updated Table 103, “ADC Characteristics,” on page Changes in “Digital Input Enable and Sleep Modes” on page Addition of OCS2 in “MOSI/OC2 Port B, Bit 3” on page The following tables have been updated Table 51, “CPOL and CPHA Functionality,” on page 132, Table 59, “UCPOL Bit Settings,” on page 158, Table 72, “Analog Comparator Multiplexed Input 1 ,” on page 195, Table 73, “ADC Conversion Time,” on page 200, Table 75, “Input Channel Selections,” on page 206, and Table 84, “Explanation of Different Variables used in Figure 103 and the Mapping to the Z-pointer,” on page Changes in “Reading the Calibration Byte” on page Corrected Errors in Cross References. Updated Some Preliminary Test Limits and Characterization Data The following tables have been updated Table 15, “Reset Characteristics,” on page 38, Table 16, “Internal Voltage Reference Characteristics,” on page 42, DC Characteristics on page 242, Table , “ADC Characteristics,” on page Changes in External Clock Frequency Added the description at the end of “External Clock” on page Added period changing data in Table 99, “External Clock Drive,” on page Updated TWI Chapter More details regarding use of the TWI bit rate prescaler and a Table 65, “TWI Bit Rate Prescaler,” on page Updated Typical Start-up Times. The following tables has been updated Table 5, “Start-up Times for the Crystal Oscillator Clock Selection,” on page 28, Table 6, “Start-up Times for the Low-frequency Crystal Oscillator Clock Selection,” on page 28, Table 8, “Start-up Times for the External RC Oscillator Clock Selection,” on page 29, and Table 12, “Start-up Times for the External Clock Selection,” on page

PDF Datasheet Preview

• High-performance, Low-power 8-bit Microcontroller
• Advanced RISC Architecture
130 Powerful Instructions Most Single-clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16 MHz On-chip 2-cycle Multiplier
• High Endurance Non-volatile Memory segments 8K Bytes of In-System Self-programmable Flash program memory 512 Bytes EEPROM 1K Byte Internal SRAM Write/Erase Cycles 10,000 Flash/100,000 EEPROM 1 3 Data retention 20 years at 85°C/100 years at 25°C 2 3 Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program True Read-While-Write Operation Programming Lock for Software Security
• Peripheral Features Two 8-bit Timer/Counters with Separate Prescaler, one Compare Mode One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode Real Time Counter with Separate Oscillator Three PWM Channels 8-channel ADC in TQFP and QFN/MLF package

Eight Channels 10-bit Accuracy 6-channel ADC in PDIP package

Six Channels 10-bit Accuracy Byte-oriented Two-wire Serial Interface Programmable Serial USART Master/Slave SPI Serial Interface Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator
• Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated RC Oscillator External and Internal Interrupt Sources Five Sleep Modes Idle, ADC Noise Reduction, Power-save, Power-down, and

Standby
• I/O and Packages
23 Programmable I/O Lines 28-lead PDIP, 32-lead TQFP, and 32-pad QFN/MLF
• Operating Voltages - 5.5V ATmega8L - 5.5V ATmega8
• Speed Grades 0 - 8 MHz ATmega8L 0 - 16 MHz ATmega8
• Power Consumption at 4 Mhz, 3V, 25°C Active mA Idle Mode mA Power-down Mode µA
8-bit with 8K Bytes In-System Programmable Flash

ATmega8 ATmega8L

Notes At 85°C. Guaranteed after last write cycle. Failure rate less than 1 ppm. Characterized through accelerated tests.

Pin Configurations

PDIP

RESET PC6 1 RXD PD0 2 TXD PD1 3 INT0 PD2 4 INT1 PD3 5

XCK/T0 PD4 6 VCC 7 GND 8

XTAL1/TOSC1 PB6 9 XTAL2/TOSC2 PB7 10

T1 PD5 11 AIN0 PD6 12 AIN1 PD7 13 ICP1 PB0 14
28 PC5 ADC5/SCL 27 PC4 ADC4/SDA 26 PC3 ADC3 25 PC2 ADC2 24 PC1 ADC1 23 PC0 ADC0 22 GND 21 AREF 20 AVCC 19 PB5 SCK 18 PB4 MISO 17 PB3 MOSI/OC2 16 PB2 SS/OC1B 15 PB1 OC1A

TQFP Top View
32 PD2 INT0 31 PD1 TXD 30 PD0 RXD 29 PC6 RESET 28 PC5 ADC5/SCL 27 PC4 ADC4/SDA 26 PC3 ADC3 25 PC2 ADC2

INT1 PD3 1 XCK/T0 PD4 2

GND 3 VCC 4 GND 5 VCC 6 XTAL1/TOSC1 PB6 7 XTAL2/TOSC2 PB7 8
24 PC1 ADC1 23 PC0 ADC0 22 ADC7 21 GND 20 AREF 19 ADC6 18 AVCC 17 PB5 SCK

T1 PD5 9 AIN0 PD6 10 AIN1 PD7 11 ICP1 PB0 12 OC1A PB1 13 SS/OC1B PB2 14 MOSI/OC2 PB3 15 MISO PB4 16

MLF Top View
32 PD2 INT0 31 PD1 TXD 30 PD0 RXD 29 PC6 RESET 28 PC5 ADC5/SCL 27 PC4 ADC4/SDA 26 PC3 ADC3 25 PC2 ADC2

INT1 PD3 1 XCK/T0 PD4 2

GND 3 VCC 4 GND 5 VCC 6 XTAL1/TOSC1 PB6 7 XTAL2/TOSC2 PB7 8
2 ATmega8 L

T1 PD5 9 AIN0 PD6 10 AIN1 PD7 11 ICP1 PB0 12 OC1A PB1 13 SS/OC1B PB2 14 MOSI/OC2 PB3 15 MISO PB4 16
24 PC1 ADC1 23 PC0 ADC0 22 ADC7 21 GND 20 AREF 19 ADC6 18 AVCC 17 PB5 SCK

NOTE The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the PCB to ensure good mechanical stability. If the center pad is left unconneted, the package might loosen from the PCB.

Overview

Block Diagram

ATmega8 L

The ATmega8 is a low-power CMOS 8-bit microcontroller based on the AVR RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega8 achieves throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize power consumption versus processing speed.

Figure Block Diagram

RESET VCC

PC0 - PC6

PB0 - PB7

XTAL1 XTAL2

PORTC DRIVERS/BUFFERS
Ordering Information

Speed MHz

Power Supply
Ordering Code

ATmega8L-8AC ATmega8L-8PC ATmega8L-8MC

ATmega8L-8AI ATmega8L-8AU 2 ATmega8L-8PI ATmega8L-8PU 2 ATmega8L-8MI ATmega8L-8MU 2

ATmega8-16AC ATmega8-16PC ATmega8-16MC

ATmega8-16AI ATmega8-16AU 2 ATmega8-16PI ATmega8-16PU 2 ATmega8-16MI ATmega8-16MU 2

Package 1
32A 28P3 32M1-A
32A 28P3 32M1-A 32M1-A
32A 28P3 32M1-A
32A 28P3 32M1-A 32M1-A

Operation Range Commercial 0°C to 70°C

Industrial -40°C to 85°C

Commercial 0°C to 70°C

Industrial -40°C to 85°C
This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.

Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances RoHS directive . Also Halide free and fully Green.
32A 28P3 32M1-A

Package Type 32-lead, Thin mm Plastic Quad Flat Package TQFP 28-lead, Wide, Plastic Dual Inline Package PDIP 32-pad, 5 x 5 x body, Lead Pitch mm Quad Flat No-Lead/Micro Lead Frame Package QFN/MLF

Packaging Information

PIN 1 e

PIN 1 IDENTIFIER

B E1 E

A1 A2 L

This package conforms to JEDEC reference MS-026, Variation ABA. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL MIN

NOTE

Note 2 Note 2
2325 Orchard Parkway R San Jose, CA 95131
32A, 32-lead, 7 x 7 mm Body Size, mm Body Thickness, mm Lead Pitch, Thin Profile Plastic Quad Flat Package TQFP
14 ATmega8 L

ATmega8 L
28P3

D PIN 1

SEATING PLANE

A1 B2
4 PLACES
0º ~ 15º REF

Note Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed mm

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL MIN

NOM MAX NOTE

Note 1

Note 1

TITLE 2325 Orchard Parkway 28P3, 28-lead mm Wide Plastic Dual R San Jose, CA 95131 Inline Package PDIP
09/28/01
28P3
32M1-A

Pin 1 ID

SIDE VIEW

TOP VIEW A2

Pin #1 Notch R

BOTTOM VIEW

Note JEDEC Standard MO-220, Fig. 2 Anvil Singulation , VHHD-2.
Updated “Ordering Information” on page

Added note to MLF package in “Pin Configurations” on page Updated “Internal Voltage Reference Characteristics” on page Updated “DC Characteristics” on page ADC4 and ADC5 support 10-bit accuracy. Document updated to reflect this.

Updated features in “Analog-to-Digital Converter” on page Updated “ADC Characteristics” on page Removed reference to “External RC Oscillator application note” from “External RC Oscillator” on page

Updated “Calibrated Internal RC Oscillator” on page

Removed “Preliminary” and TBDs from the datasheet. Renamed ICP to ICP1 in the datasheet. Removed instructions CALL and JMP from the datasheet. Updated tRST in Table 15 on page 38, VBG in Table 16 on page 42, Table 100 on
page 244 and Table 102 on page Replaced text “XTAL1 and XTAL2 should be left unconnected NC ” after

Table 9 in “Calibrated Internal RC Oscillator” on page Added text regarding XTAL1/XTAL2 and CKOPT Fuse in “Timer/Counter Oscillator” on page Updated Watchdog Timer code examples in “Timed Sequences for Changing the Configuration of the Watchdog Timer” on page Removed bit 4, ADHSM, from “Special Function IO Register SFIOR” on page Added note 2 to Figure 103 on page Updated item 4 in the “Serial Programming Algorithm” on page Added tWD_FUSE to Table 97 on page 239 and updated Read Calibration Byte, Byte 3, in Table 98 on page Updated Absolute Maximum Ratings* and DC Characteristics in “Electrical Characteristics” on page

Updated VBOT values in Table 15 on page Updated “ADC Characteristics” on page

Updated “ATmega8 Typical Characteristics” on page

Updated “Erratas” on page

Improved the description of “Asynchronous Timer Clock clkASY” on page Removed reference to the “Multipurpose Oscillator” application note and the
“32 kHz Crystal Oscillator” application note, which do not exist.

Corrected OCn waveforms in Figure 38 on page

Various minor Timer 1 corrections.

Various minor TWI corrections.

Added note under “Filling the Temporary Buffer Page Loading ” on page 216 about writing to the EEPROM during an SPM Page load.

Removed ADHSM completely.

Added section “EEPROM Write during Power-down Sleep Mode” on page

Removed XTAL1 and XTAL2 description on page 5 because they were already described as part of “Port B PB7..PB0 XTAL1/XTAL2/TOSC1/TOSC2” on page

Improved the table under “SPI Timing Characteristics” on page 246 and removed the table under “SPI Serial Programming Characteristics” on page

Corrected PC6 in “Alternate Functions of Port C” on page

Corrected PB6 and PB7 in “Alternate Functions of Port B” on page

Corrected Mbps to kbps under “Examples of Baud Rate Setting” on page

Added information about PWM symmetry for Timer 2 in “Phase Correct PWM Mode” on page

Added thick lines around accessible registers in Figure 76 on page

Changed “will be ignored” to “must be written to zero” for unused Z-pointer bits under “Performing a Page Write” on page

Added note for RSTDISBL Fuse in Table 87 on page

Updated drawings in “Packaging Information” on page
20 ATmega8 L

ATmega8 L

Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.

Updated Table 103, “ADC Characteristics,” on page

Changes in “Digital Input Enable and Sleep Modes” on page

Addition of OCS2 in “MOSI/OC2 Port B, Bit 3” on page

The following tables have been updated Table 51, “CPOL and CPHA Functionality,” on page 132, Table 59, “UCPOL Bit Settings,” on page 158, Table 72, “Analog Comparator Multiplexed Input 1 ,” on page 195, Table 73, “ADC Conversion Time,” on page 200, Table 75, “Input Channel Selections,” on page 206, and Table 84, “Explanation of Different Variables used in Figure 103 and the Mapping to the Z-pointer,” on page

Changes in “Reading the Calibration Byte” on page

Corrected Errors in Cross References.

Updated Some Preliminary Test Limits and Characterization Data The following tables have been updated Table 15, “Reset Characteristics,” on page 38, Table 16, “Internal Voltage Reference Characteristics,” on page 42, DC Characteristics on page 242, Table , “ADC Characteristics,” on page

Changes in External Clock Frequency Added the description at the end of “External Clock” on page Added period changing data in Table 99, “External Clock Drive,” on page

Updated TWI Chapter More details regarding use of the TWI bit rate prescaler and a Table 65, “TWI Bit Rate Prescaler,” on page

Updated Typical Start-up Times. The following tables has been updated Table 5, “Start-up Times for the Crystal Oscillator Clock Selection,” on page 28, Table 6, “Start-up Times for the Low-frequency Crystal Oscillator Clock Selection,” on page 28, Table 8, “Start-up Times for the External RC Oscillator Clock Selection,” on page 29, and Table 12, “Start-up Times for the External Clock Selection,” on page

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Datasheet ID: ATMEGA8-16PU 519267