ATMEGA169-16MU

ATMEGA169-16MU Datasheet


In-System Programming by On-chip Boot Program True Read-While-Write Operation 512 bytes EEPROM Endurance 100,000 Write/Erase Cycles 1K byte Internal SRAM Programming Lock for Software Security<br>• JTAG IEEE std. compliant Interface Boundary-scan Capabilities According to the JTAG Standard Extensive On-chip Debug Support Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface<br>• Peripheral Features 4 x 25 Segment LCD Driver Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode Real Time Counter with Separate Oscillator Four PWM Channels 8-channel, 10-bit ADC Programmable Serial USART Master/Slave SPI Serial Interface Universal Serial Interface with Start Condition Detector Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator Interrupt and Wake-up on Pin Change<br>• Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated Oscillator External and Internal Interrupt Sources Five Sleep Modes Idle, ADC Noise Reduction, Power-save, Power-down, and Standby<br>• I/O and Packages 53 Programmable I/O Lines 64-lead TQFP and 64-pad MLF<br>• Speed Grade ATmega169V 0 - 4 MHz - 5.5V, 0 - 8 MHz - 5.5V ATmega169 0 - 8 MHz - 5.5V, 0 - 16 MHz - 5.5V<br>• Temperature range -40°C to 85°C Industrial<br>• Ultra-Low Power Consumption Active Mode 1 MHz, 1.8V 350µA 32 kHz, 1.8V 20µA including Oscillator 32 kHz, 1.8V 40µA including Oscillator and LCD Power-down Mode 0.1µA at 1.8V

Part Datasheet
ATMEGA169-16MU ATMEGA169-16MU ATMEGA169-16MU (pdf)
Related Parts Information
ATMEGA169V-8AU ATMEGA169V-8AU ATMEGA169V-8AU
ATMEGA169-16AU ATMEGA169-16AU ATMEGA169-16AU
ATMEGA169V-8MU ATMEGA169V-8MU ATMEGA169V-8MU
ATMEGA169-16MI ATMEGA169-16MI ATMEGA169-16MI
ATMEGA169-16AI ATMEGA169-16AI ATMEGA169-16AI
ATMEGA169V-8MI ATMEGA169V-8MI ATMEGA169V-8MI
ATMEGA169V-8AI ATMEGA169V-8AI ATMEGA169V-8AI
PDF Datasheet Preview
• High Performance, Low Power 8-Bit Microcontroller
• Advanced RISC Architecture
130 Powerful Instructions Most Single Clock Cycle Execution 32 x 8 General Purpose Working Registers Fully Static Operation Up to 16 MIPS Throughput at 16 MHz On-Chip 2-cycle Multiplier
• Non-volatile Program and Data Memories 16K bytes of In-System Self-Programmable Flash

Endurance 10,000 Write/Erase Cycles Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program True Read-While-Write Operation 512 bytes EEPROM Endurance 100,000 Write/Erase Cycles 1K byte Internal SRAM Programming Lock for Software Security
• JTAG IEEE std. compliant Interface Boundary-scan Capabilities According to the JTAG Standard Extensive On-chip Debug Support Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
• Peripheral Features 4 x 25 Segment LCD Driver Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode Real Time Counter with Separate Oscillator Four PWM Channels 8-channel, 10-bit ADC Programmable Serial USART Master/Slave SPI Serial Interface Universal Serial Interface with Start Condition Detector Programmable Watchdog Timer with Separate On-chip Oscillator On-chip Analog Comparator Interrupt and Wake-up on Pin Change
• Special Microcontroller Features Power-on Reset and Programmable Brown-out Detection Internal Calibrated Oscillator External and Internal Interrupt Sources Five Sleep Modes Idle, ADC Noise Reduction, Power-save, Power-down, and Standby
• I/O and Packages 53 Programmable I/O Lines 64-lead TQFP and 64-pad MLF
• Speed Grade ATmega169V 0 - 4 MHz - 5.5V, 0 - 8 MHz - 5.5V ATmega169 0 - 8 MHz - 5.5V, 0 - 16 MHz - 5.5V
• Temperature range -40°C to 85°C Industrial
• Ultra-Low Power Consumption Active Mode 1 MHz, 1.8V 350µA 32 kHz, 1.8V 20µA including Oscillator 32 kHz, 1.8V 40µA including Oscillator and LCD Power-down Mode 0.1µA at 1.8V
8-bit Microcontroller with 16K Bytes In-System Programmable Flash ATmega169V ATmega169 Preliminary Summary

Note This is a summary document. A complete document is available on our Web site at

Pin Configurations Figure Pinout ATmega169

LCDCAP 1 RXD/PCINT0 PE0 2 TXD/PCINT1 PE1 3 XCK/AIN0/PCINT2 PE2 4 AIN1/PCINT3 PE3 5 USCK/SCL/PCINT4 PE4 6 DI/SDA/PCINT5 PE5 7

DO/PCINT6 PE6 8 CLKO/PCINT7 PE7 9

SS/PCINT8 PB0 10 SCK/PCINT9 PB1 11 MOSI/PCINT10 PB2 12 MISO/PCINT11 PB3 13 OC0A/PCINT12 PB4 14 OC1A/PCINT13 PB5 15 OC1B/PCINT14 PB6 16

INDEX CORNER

ATmega169
64 AVCC 63 GND 62 AREF 61 PF0 ADC0 60 PF1 ADC1 59 PF2 ADC2 58 PF3 ADC3 57 PF4 ADC4/TCK 56 PF5 ADC5/TMS 55 PF6 ADC6/TDO 54 PF7 ADC7/TDI 53 GND 52 VCC 51 PA0 COM0 50 PA1 COM1 49 PA2 COM2
48 PA3 COM3 47 PA4 SEG0 46 PA5 SEG1 45 PA6 SEG2 44 PA7 SEG3 43 PG2 SEG4 42 PC7 SEG5 41 PC6 SEG6 40 PC5 SEG7 39 PC4 SEG8 38 PC3 SEG9 37 PC2 SEG10 36 PC1 SEG11 35 PC0 SEG12 34 PG1 SEG13 33 PG0 SEG14

OC2A/PCINT15 PB7 17 T1/SEG24 PG3 18 T0/SEG23 PG4 19 RESET 20 VCC 21 GND 22 TOSC2 XTAL2 23 TOSC1 XTAL1 24

ICP1/SEG22 PD0 25 INT0/SEG21 PD1 26

SEG20 PD2 27 SEG19 PD3 28 SEG18 PD4 29 SEG17 PD5 30 SEG16 PD6 31 SEG15 PD7 32

Disclaimer

Note:

The large center pad underneath the MLF packages is made of metal and internally connected to GND. It should be soldered or glued to the board to ensure good mechanical stability. If the center pad is left unconnected, the package might loosen from the board.

Typical values contained in this datasheet are based on simulations and characterization of other AVR microcontrollers manufactured on the same process technology. Min and Max values will be available after the device is characterized.
2 ATmega169/V

ATmega169/V

Overview

The ATmega169 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATmega169 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed.

Block Diagram

Figure Block Diagram

XTAL1 XTAL2

VCC GND

PF0 - PF7

PA0 - PA7

PC0 - PC7

PORTF DRIVERS

DATA REGISTER PORTF

DATA DIR. REG. PORTF

PORTA DRIVERS

PORTC DRIVERS

DATA REGISTER PORTA

DATA DIR. REG. PORTA

DATA REGISTER PORTC
8-BIT DATA BUS
Ordering Information

Speed MHz

Power Supply
- 5.5V
- 5.5V
Ordering Code

ATmega169V-8AI ATmega169V-8AJ 3 ATmega169V-8MI ATmega169V-8MJ 3

ATmega169-16AI ATmega169-16AJ 3 ATmega169-16MI ATmega169-16MJ 3

Package 1
64A 64M1
64A 64M1

Operation Range

Industrial -40°C to 85°C

Industrial -40°C to 85°C
This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information and minimum quantities.

See Figure 135 and Figure Pb-free alternative.
64A 64M1

Package Type 64-Lead, Thin mm Plastic Gull Wing Quad Flat Package TQFP 64-pad, 9 x 9 x mm body, lead pitch mm, Micro Lead Frame Package MLF
14 ATmega169/V

Packaging Information

ATmega169/V

PIN 1 e

PIN 1 IDENTIFIER

B E1 E

A1 A2 L

This package conforms to JEDEC reference MS-026, Variation AEB. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is mm per side. Dimensions D1 and E1 are maximum plastic body size dimensions including mold mismatch. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL MIN NOM MAX NOTE

D1 Note 2

E1 Note 2
10/5/2001
2325 Orchard Parkway

R San Jose, CA 95131
64A, 64-lead, 14 x 14 mm Body Size, mm Body Thickness, mm Lead Pitch, Thin Profile Plastic Quad Flat Package TQFP
64M1

Marked Pin# 1 ID

TOP VIEW

Pin #1 Corner

C SEATING PLANE A1

SIDE VIEW

BOTTOM VIEW

Notes JEDEC Standard MO-220, Fig. 1, VMMD.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 b D D2 E E2 e L

NOM BSC

NOTE

TITLE 2325 Orchard Parkway 64M1, 64-pad, 9 x 9 x mm Body, Lead Pitch mm R San Jose, CA 95131 Micro Lead Frame Package MLF
01/15/03
64M1
16 ATmega169/V

Errata

ATmega169/V

No known errata.
• High serial resistance in the glass can result in dim segments on the LCD
• IDCODE masks data from TDI input
page Removed old and added new “LCD Controller” on page Updated “Electrical Characteristics” on page Updated “ATmega169 Typical Characteristics” on page Updated “Ordering Information” on page

ATmega169L replaced by ATmega169V and ATmega169.

Updated “Calibrated Internal RC Oscillator” on page 27

Removed “Advance Information” from the datasheet. Removed AGND from Figure 2 on page 3 and added “System Clock

Prescaler” to Figure 11 on page Updated Table 16 on page 38, Table 17 on page 40, Table 19 on page 42
and Table 40 on page Renamed and updated “On-chip Debug System” to “JTAG Interface and

On-chip Debug System” on page Updated COM01:0 to COM0A1:0 in “Timer/Counter Control Register A

TCCR0A” on page 90 and COM21:0 to COM2A1:0 in “Timer/Counter Control Register TCCR2A” on page Updated “Test Access Port TAP” on page 228 regarding JTAGEN. Updated description for the JTD bit on page Added a note regarding JTAGEN fuse to Table 119 on page Updated Absolute Maximum Ratings* and DC Characteristics in “Electrical Characteristics” on page Updated “Errata” on page 17 and added a proposal for solving problems regarding the JTAG instruction IDCODE.
20 ATmega169/V

ATmega169/V

Updated typo in Figure 147, Figure 167, and Figure
Updated “ATmega169 Typical Characteristics” on page Updated typo in “Ordering Information” on page Updated Figure 45 on page 110, Table 18 on page 40, and “Version” on page

Renamed ICP to ICP1 in whole document. Removed note on “Crystal Oscillator Operating Modes” on page XTAL1/XTAL2 can be used as timer oscillator pins, described in chapter “Cal-
ibrated Internal RC Oscillator” on page Switching between prescaler settings in “Switching Time” on page Updated DC and ACD Characteristics in chapter “Electrical Characteristics”
on page 300 are updated. Removed TBD’s from Table 16 on page 38, Table 19 on page 42, Table 134 on page Updated Figure 22 on page 53, Figure 25 on page 58 and Figure 109 on page 240 regarding WRITE PINx REGISTER. Updated “Alternate Functions of Port F” on page 70 regarding JTAG. Replaced Timer0 Overflow with Timer/Counter0 Compare Match in “Universal Serial Interface USI” on page Also updated “Start Condition Detector” on page 186 and “USI Control Register USICR” on page Updated Features for “Analog to Digital Converter” on page 194 and Table 88 on page Added notes on Figure 117 on page 261 and Table 118 on page

Updated the section “Features” on page 1 with information regarding ATmega169 and ATmega169L.

Removed all references to the PG5 pin in Figure 1 on page 2, Figure 2 on page 3, “Port G PG4..PG0 ” on page 6, “Alternate Functions of Port G” on page 72, and “Register Description for I/O-Ports” on page

Updated Table 118, “Extended Fuse Byte,” on page Added Errata for “Datasheet Change Log for ATmega169” on page 20, includ-
ing “Significant Data Sheet Changes”. Updated the “Ordering Information” on page 14 to include the new speed
grade for ATmega169L and the new 16 MHz ATmega169.

Added TCK frequency limit in “Programming via the JTAG Interface” on page

Added Chip Erase as a first step in “Programming the Flash” on page 297 and “Programming the EEPROM” on page

Added the section “Unconnected Pins” on page

Added tips on how to disable the OCD system in “On-chip Debug System” on page

Corrected interrupt addresses. ADC and ANA_COMP had swapped places.

Improved the table in “SPI Timing Characteristics” on page 303 and removed the table in “SPI Serial Programming Characteristics” on page

Changed “will be ignored” to “must be written to zero” for unused Z-pointer bits in “Performing a Page Write” on page

Corrected “LCD Frame Complete” to “LCD Start of Frame” in the LCDCRA Register description.

Changed OUT to STS and IN to LDS in USI code examples, and corrected fSCKmax. The USI I/O Registers are in the extended I/O space, so IN and OUT cannot be used. LDS and STS take one more cycle when executed, so fSCKmax had to be changed accordingly.

Removed TOSKON and TOSCK from Table 103 on page 241, and g10 and g20 from Figure 114 on page 243 and Table 105 on page 244, because these signals do not exist in boundary scan.

Changed from 4 to 16 MIPS and MHz in the device Features list.

Corrected Port A to Port F in “AVCC” on page 6 under “Pin Descriptions” on page

Corrected Mbps to kbps in “Examples of Baud Rate Setting” on page

Corrected placing of falling and rising XCK edges in Table 78, “UCPOL Bit Settings,” on page

Removed reference to Multipurpose Oscillator Application Note, which does not exist.

Corrected Number of Calibrated RC Oscillator Cycles in Table 1 on page 19 from 8,448 to

Various minor Timer1 corrections.

Added information about PWM symmetry for Timer0 and Timer2.

Corrected the contents of DIDR0 and DIDR1.
22 ATmega169/V

ATmega169/V

Made all bit names in the LCDDR Registers unique by adding the COM number digit in front of the two digits already there, e.g. SEG304.

Changed Extended Standby to ADC Noise Reduction mode under “Asynchronous Operation of Timer/Counter2” on page

Added note about Port B having better driving capabilities than the other ports. As a consequence the table, “DC Characteristics” on page 300 was corrected as well.

Added note under “Filling the Temporary Buffer Page Loading ” on page 262 about writing to the EEPROM during an SPM page load.

Removed ADHSM completely.

Updated “Packaging Information” on page

Added “Errata” on page
Added Information for the 64-pad MLF Package in “Ordering Information” on page 14 and “Packaging Information” on page
Changed Temperature Range and Removed Industrial Ordering Codes in “Packaging Information” on page

Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.

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Datasheet ID: ATMEGA169-16MU 519264