AT91SAM9M10-CU

AT91SAM9M10-CU Datasheet

AT91SAM ARM-based Embedded MPU

Part	Datasheet
AT91SAM9M10-CU	AT91SAM9M10-CU (pdf)

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• 400 MHz ARM926EJ-S Processor 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU • Memories DDR2 Controller 4-bank DDR2/LPDDR, SDR/LPSDR External Bus Interface supporting 4-bank DDR2/LPDDR, SDR/LPSDR, Static Memories, SLC NAND Flash with ECC One 64-KByte internal SRAM, single-cycle access at system speed or processor speed through TCM interface One 64-KByte internal ROM, embedding bootstrap routine • Peripherals Multi-format Video Decoder LCD Controller supporting STN and TFT displays up to 1280*860 ITU-R BT. 601/656 Image Sensor Interface USB Device High Speed, USB Host High Speed and USB Host Full Speed with OnChip Transceiver 10/100 Mbps Ethernet MAC Controller Two High Speed Memory Card Hosts SDIO, SDCard, MMC AC'97 controller Two Master/Slave Serial Peripheral Interfaces Two Three-channel 16-bit Timer/Counters Two Synchronous Serial Controllers I2S mode Four-channel 16-bit PWM Controller Two-wire Interfaces Four USARTs with ISO7816, IrDA, Manchester and SPI modes 8-channel 10-bit ADC with 4-wire Touch Screen support • System 133 MHz twelve 32-bit layer AHB Bus Matrix 37 DMA Channels Boot from NAND Flash, SDCard, or serial DataFlash Reset Controller with on-chip Power-on Reset Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators Internal Low-power 32 kHz RC Oscillator One PLL for the system and one 480 MHz PLL optimized for USB High Speed Two Programmable External Clock Signals Advanced Interrupt Controller and Debug Unit Periodic Interval Timer, Watchdog Timer, Real Time Timer and Real Time Clock • I/O Five 32-bit Parallel Input/Output Controllers 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input • Package 324-ball TFBGA, pitch mm AT91SAM ARM-based Embedded MPU SAM9M10 The SAM9M10 is a multimedia enabled mid-range ARM926-based embedded MPU running at 400MHz, combining user interfaces, video playback and connectivity. It includes hardware video decoder, LCD Controller, resistive touchscreen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO. The hardware video decoder supports H.264, MPEG-4, MPEG-2, VC-1, H.263. The SAM9M10 also provides hardware image post-processing, such as image scaling, color conversion and image rotation. The SAM9M10 supports the latest generation of DDR2 and NAND Flash memory interfaces for program and data storage. An internal 133 MHz multi-layer bus architecture associated with 37 DMA channels, a dual external bus interface and distributed memory including a 64-KByte SRAM which can be configured as a tightly coupled memory TCM sustains the high bandwidth required by the processor and the high speed peripherals. The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory interface and peripheral I/Os. This feature completely eliminates the need for any external level shifters. In addition it supports ball pitch package for low cost PCB manufacturing. The SAM9M10 power management controller features efficient clock gating and a battery backup section minimizing power consumption in active and standby modes. The SAM9M10 device is particularly well suited for media-rich displays and control panels in home and commercial buildings, POS terminals, entertainment systems, internet appliances and medical. 2 SAM9M10 NTRST TTTTDDCMIOKS RTCK JTAGSEL BMS VHHBFHGSSDDPPAA,,HHFHSSDDMMAA Block Diagram Figure SAM9M10 Block Diagram TST PCK0-PCK1 FIQ IRQ DRXD DTXD PLLRCA XIN XOUT XIN32 XOUT32 SHDN WKUP VDDBU NRST VDDCORE System Controller JTAG / Boundary Scan HS Transceiver HS Transceiver DBGU PLLA PLLUTMI OSC12M RC OSC 32K SHDC 4 GPBR RTT POR RSTC PIOA PIOB PIOC PIOD PIOE In-Circuit Emulator ARM926EJ-S ICache DCache 32K bytes MMU 32Kbytes ITCM DTCM Bus Interface SRAM 64KB Data Ordering The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding. All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows the user to program the same component order as the sensor, reducing software treatments to restore the right format. Table Mode Default Mode1 Mode2 Mode3 Data Ordering in YCbCr Mode Byte 0 Byte 1 Byte 2 Cr i Cb i Y i+1 Y i+1 Byte 3 Y i+1 Y i+1 Cr i Cb i Table Mode RGB 8:8:8 RGB Format in Default Mode, RGB_CFG = 00, No Swap Byte Byte 0 Byte 1 Byte 2 Byte 3 R7 i+1 R6 i+1 R5 i+1 R4 i+1 D3 R3 i G3 i B3 i R3 i+1 D2 R2 i G2 i B2 i R2 i+1 D1 R1 i G1 i B1 i R1 i+1 D0 R0 i G0 i B0 i R0 i+1 884 SAM9M10 SAM9M10 Table RGB 5:6:5 RGB Format in Default Mode, RGB_CFG = 00, No Swap Byte 0 Byte 1 Byte 2 R4 i+1 R3 i+1 R2 i+1 R1 i+1 Byte 3 G2 i+1 G1 i+1 G0 i+1 B4 i+1 R0 i B3 i R0 i+1 B3 i+1 G5 i B2 i G5 i+1 B2 i+1 G4 i B1 i G4 i+1 B1 i+1 G3 i B0 i G3 i+1 B0 i+1 Table Mode RGB 5:6:5 RGB Format, RGB_CFG = 10 Mode 2 , No Swap Byte Byte 0 Byte 1 Byte 2 G2 i+1 G1 i+1 G0 i+1 R4 i+1 Byte 3 This block serializes the data read from memory. It reads words from the FIFO and outputs pixels 1 bit, 2 bits, 4 bits, 8 bits, 16 bits or 24 bits wide depending on the format specified in the PIXELSIZE field of the LCDCON2 register. It also adapts the memory-ordering format. Both bigendian and little-endian formats are supported. They are configured in the MEMOR field of the LCDCON2 register. The organization of the pixel data in the memory depends on the configuration and is shown in Table 45-5 and Table Note: For a color depth of 24 bits per pixel there are two different formats supported packed and unpacked. The packed format needs less memory but has some limitations when working in 2D addressing mode See “2D Memory Addressing” on page 1088 SAM9M10 SAM9M10 Table Little Endian Memory Organization Mem Addr Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pixel 1bpp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pixel 2bpp 15 Pixel 4bpp Pixel 8bpp Pixel 16bpp Pixel 24bpp packed Pixel 24bpp packed Pixel 24bpp packed Pixel 24bpp not used unpacked Table Big Endian Memory Organization Mem Addr Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Pixel 1bpp 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Pixel 2bpp 0 Pixel 4bpp Pixel 8bpp Pixel 16bpp Pixel 24bpp packed Pixel 24bpp packed • PIXELOFF DAM2D Addressing Pixel offset When 2D DMA addressing is enabled bit DMA2DEN is set in register DMACON , this field specifies the offset of the first pixel in each line within the memory word that contains this pixel. The offset is specified in number of bits in the range 0-31, so for example a value of 4 indicates that the first pixel in the screen starts at bit 4 of the 32-bit word pointed by register DMABADDR1. Bits 0 to 3 of that word are not used. This example is valid for little endian memory organization. When using big endian memory organization, this offset is considered from bit 31 downwards, or equivalently, a given value of this field always selects the pixel in the same relative position within the word, independently of the memory ordering configuration. Bit DMAUPDT in register DMACON must be written after writing any new value to this field in order to make the DMA controller use this new value. 1118 SAM9M10 SAM9M10 LCD Control Register 1 Name LCDCON1 Address:0x00500800 Access Read-write, except LINECNT Read-only Reset value 0x00002000 LINECNT CLKVAL LINECNT CLKVAL • BYPASS LCDDOTCK Divider 0 The divider is not bypassed. LCDDOTCK frequency defined by the CLKVAL field. 1 The LCDDOTCK divider is bypassed. LCDDOTCK frequency is equal to the LCDC Clock frequency. • CLKVAL Clock Divider 9-bit divider for pixel clock LCDDOTCK frequency. Pixel_clock = system_clock CLKVAL + 1 • LINECNT Line Counter Read-only Current Value of 11-bit line counter. Down count from LINEVAL to 8 0 BYPASS 1119 LCD Control Register 2 Name LCDCON2 Address:0x00500804 Access Read-write Reset value: MEMOR CLKMOD PIXELSIZE INVDVAL INVCLK IFWIDTH 26 18 10 INVLINE 2 SCANMOD INVFRAME INVVD DISTYPE • DISTYPE Display Type DISTYPE STN Monochrome STN Color TFT Reserved • SCANMOD Scan Mode 0 Single Scan 1 Dual Scan • IFWIDTH Interface width STN IFWIDTH 4-bit Only valid in single scan STN mono or color 8-bit Only valid in STN mono or Color 16-bit Only valid in dual scan STN mono or color Reserved 1120 SAM9M10 • MEMOR Memory Ordering Format 00 Big Endian 10 Little Endian 11 WinCE format SAM9M10 1121 LCD Timing Configuration Register 1 Name LCDTIM1 Address:0x00500808 Access Read-write Reset value: VHDLY • VFP Vertical Front Porch In TFT mode, these bits equal the number of idle lines at the end of the frame. In STN mode, these bits should be set to • VBP Vertical Back Porch In TFT mode, these bits equal the number of idle lines at the beginning of the frame. In STN mode, these bits should be set to • VPW Vertical Synchronization pulse width In TFT mode, these bits equal the vertical synchronization pulse width, given in number of lines. LCDVSYNC width is equal to VPW+1 lines. In STN mode, these bits should be set to • VHDLY Vertical to horizontal delay In TFT mode, this is the delay between LCDVSYNC rising or falling edge and LCDHSYNC rising edge. Delay is VHDLY+1 LCDDOTCK cycles. Bit 31 must be written to In STN mode, these bits should be set to 1122 SAM9M10 SAM9M10 LCD Timing Configuration Register 2 Name LCDTIM2 Address:0x0050080C Access Read-write Reset value: • HBP Horizontal Back Porch Number of idle LCDDOTCK cycles at the beginning of the line. Idle period is HBP+1 LCDDOTCK cycles. • HPW Horizontal synchronization pulse width of the LCDHSYNC pulse, given in LCDDOTCK cycles. Width is HPW+1 LCDDOTCK cycles. • HFP Horizontal Front Porch Number of idle LCDDOTCK cycles at the end of the line. Idle period is HFP+1 LCDDOTCK cycles. 1123 LCD Frame Configuration Register Name LCDFRMCFG Address:0x00500810 Access Read-write Reset value: LINESIZE LINESIZE LINEVAL LINEVAL • LINEVAL Vertical size of LCD module In single scan mode vertical size of LCD Module, in pixels, minus 1 In dual scan mode vertical display size of each LCD panel, in pixels, minus 1 • LINESIZE Horizontal size of LCD module, in pixels, minus 1 1124 SAM9M10 SAM9M10 LCD FIFO Register Name LCDFIFO Address:0x00500814 If post-processing is enabled, one or two additional image transfer operations will take place. If the decoded images are in display order i.e. no picture re-ordering has been made when encoding the sequence , and rotation is not used, PP will process the pictures in pipeline with the decoder. Otherwise, it will first have to read the decoded image that is to be displayed next from the memory 6 , and then write back the processed image 1148 SAM9M10 SAM9M10 Figure Multi-format Decoder and External Memory Data Flow in VLC Mode External Memory ARM Processor Core H.264 NAL Unit Stream Decoded Picture Buffer 6 2 AHB Bus Post-Processed 7 Picture Buffer Multiformat HW Decoder Core Decoder Data Flow, Software Performs Entropy Decoding RLC Mode In this case, the decoder software starts decoding the first picture by parsing the stream headers 1 , and by performing entropy decoding. Software then writes the following items to external memory: • Run-length-coded RLC data 2 • Differential motion vectors 3 • Intra 4x4 prediction modes in H.264 or separate DC coefficients in MPEG-4, if the stream is using data partitioning 4 • Macroblock control data 5 Last step for the software is to write the hardware control registers and to enable the hardware Hardware decodes the picture by buffering control data for several macroblocks at a time, and then reads appropriate amount of RLC data, differential motion vectors and intra modes depending on each macroblock type Hardware will also read the reference pictures previously decoded pictures as required Hardware writes decoded in-loop filtered, if H.264 output picture to memory one macroblock at a time When the picture has been fully decoded, hardware gives an interrupt and returns to initial state. If post-processing is enabled, one or two additional image transfer operations will take place. If the decoded images are in display order i.e. no picture re-ordering has been made when encoding the sequence , and rotation is not used, PP will process the pictures in pipeline with the decoder. Otherwise, it will first have to read the decoded image that is to be displayed next from the memory 13 , and then write back the processed image 1149 Figure Multi-format Decoder and External Memory Data Flow in RLC Mode External Memory H.264 NAL Unit Stream ARM Processor Core RLC Data Differential Motion Vectors Intra 4x4 Modes Macroblock Control Decoded Picture Buffer Post-Processed Picture Buffer 6 AHB Bus Multiformat HW Decoder Core 1150 SAM9M10 SAM9M10 Product Dependencies Power Management The Video Decoder requires a peripheral clock. The user has to enable UHP peripheral clock, bit 1 << AT91C_ID_VDEC in PMC_PCER register. Software can reset the hardware synchronically by writing separate decoder and post-processor enable bits to zero. These enable bits are located in the memory-mapped registers and they can be used for terminating or restarting the decoding or post-processing at any time. Interrupt The Video Decoder has an interrupt line connected to the Advanced Interrupt Controller AIC . Table Peripheral IDs Instance VDEC Handling Video Decoder interrupts requires programming the AIC before. 1151 Video Decoder VDEC User Interface The VDEC User interface is split into two interfaces. • One that concerns Post Processor and is common to all Decoder Modes, described by Video Post Processor Register Mapping. • One in which registers and fields depend on the Decoder Mode used. For best readability this document describes one Register Mapping for each Decoder Mode. The relations are given in Table Table Register Mapping vs. Decoder Mode Decoder Mode Refer to the following Register Mapping H264 Video Decoder Register Mapping H264 • FRAME_NUM Frame Number Current Frame Number, used to identify short-term reference frames. Used in reference picture reordering. • FRAME_NUM_LEN Frame Number length Bit length of frame_num in data stream. • W_BIPR Weight Prediction for B Slices H.264 weighted prediction specification for B slices. • W_PRED Weight Prediction H.264 weighted prediction enable for P slices. • DIRMV_PRED Derive Luma Method Specifies the method to use to derive luma motion vectors. • BW Black and White Enable 0 4:2:0 sampling format 1 4:0:0 sampling format • CABAC H.264 CABAC Enable 0 CABAC disable. 1 CABAC enable. 1166 SAM9M10 SAM9M10 Decoder Control Register 5 H.264 Control Name: VDEC_CTLR5 Address: 0x00900020 Access: Read-write CONS_INTRA FILT_CTRL RD_PIC T8X8FE REF_PIC_LEN REF_PIC_LEN IDREN IDR_PIC_ID IDR_PIC_ID • IDR_PIC_ID IDR Picture Identifies IDR instantaneous decoding refresh picture. • IDREN IDR Picture Enable IDR instantaneous decoding refresh picture flag. • REF_PIC_LEN Reference Picture Length of decoded reference picture marking bits. • T8X8FE 8x8 Transform Flag Enable 8x8 transform flag enable • RD_PIC Redundant Picture Present Specifies whether redundant picture count syntax elements are present in the slice header. • FILT_CTRL Extra Variables Controlling Characteristics of The Deblocking Filter Indicates whether extra variables controlling characteristics of the deblocking filter are present in the slice header. • CONS_INTRA Intra in Prediction 1 Specifies that intra prediction uses only neighboring intra macroblocks in prediction. 0 Also neighboring inter macroblocks are used in intra prediction process. 1167 Decoder Control Register 6 H.264 RLC Mode Name: VDEC_CTLR6 Address: 0x00900024 All devices are marked with the Atmel logo and the ordering code. Additional marking may be in one of the following formats: YYWW V where SAM9M10 1373 SAM9M10 Ordering Information Table AT91SAM9M10 Ordering Information Ordering Code Package AT91SAM9M10B-CU TFBGA324 AT91SAM9M10-CU TFBGA324 Package Type Green Temperature Operating Range Industrial 40°C to 85°C Industrial 40°C to 85°C 1374 SAM9M10 SAM9M10 SAM9M10 Errata Boot ROM Boot ROM NAND Flash boot does not support ECC Correction The boot ROM allows booting from block 0 of a NAND Flash connected on CS3. However, the boot ROM does not feature ECC correction on a NAND Flash. Most of the NAND Flash vendors do not guarantee anymore that block 0 is error free. Therefore we advise to locate the bootstrap program into another device supported by the boot ROM DataFlash, Serial Flash, SDCARD or EEPROM , and to implement a NAND Flash access with ECC. Problem Fix/Workaround None. EMAC EMAC Setup Timing Violation in RMII Mode A setup timing violation occurs when using the EMAC in RMII mode only with I/Os in a 1.8V range [1.65V:1.95V] and when the line load exceeds 20 pF. The RMII mode is fully functional with I/Os in a 3.3V range [3.0V:3.6V]. Problem Fix/Workaround None. Error Corrected Code Controller ECC ECC Computation with a 1 clock cycle long NRD/NWE pulse If the SMC is programmed with NRD/NWE pulse length equal to 1 clock cycle, ECC cannot compute the parity. Problem Fix/Workaround It is recommended to program SMC with a value superior to Uncomplete parity status when error in ECC parity When a single correctable error is detected in ECC value, the error is located in ECC Parity register's field which contains a 1 in the 24 least significant bits except when the error is located in the 12th or the 24th bit. In this case, these bits are always stuck at A Single correctable error is detected but it is impossible to correct it. Problem Fix/Workaround None. Unsupported ECC per 512 words 1 bit ECC per 512 words is not functional. Problem Fix/Workaround Perform the ECC computation by software. 1375 Unsupported hardware ECC on 16-bit Nand Flash Hardware ECC on 16-bit Nand Flash is not supported. Problem Fix/Workaround Perform the ECC by software. Pulse Width Modulation Controller PWM PWM Zero Period It is impossible to update a period equal to 0 by using the PWM_CUPD register. Problem Fix/Workaround None Static Memory Controller SMC SMC Delay Access In this document, the Access is “Read-write” in the Register Mapping Table SMC_DELAY1 to SMC_DELAY8 rows , and in the SMC DELAY I/O Register. The current access is “Write-only”. Problem Fix/Workaround None Serial Synchronous Controller SSC SSC Data sent without any frame synchro When SSC is configured with the following conditions: • RF is in input, • TD is synchronized on a receive START any condition START field = 2 to 7 • TF toggles at each start of data transfer • Transmit STTDLY = 0 • Check TD and TF after a receive START, The data is sent but there is not any toggle of the TF line Problem Fix/Workaround Transmit STTDLY must be different from SSC Unexpected delay on TD output When SSC is configured with the following conditions: Ordering Information Section “SAM9M10 Ordering Information”, a second ordering code added AT91SAM9M10B-C. An MRL column added too. Change Request Ref. 7899 7763 7981 7979 7981 7979 1383 Comments Introduction Product Line/Product naming convention changed - AT91SAM ARM-based MPU / SAM9M10 Section “Power Supplies”, replaced ground pin names by GNDIOM, GNDCORE, GNDANA, GNDIOP, GNDBU, GNDOSC, GNDUTMI. Reorganized text describing GND association to power supply pins Clock Generator Figure 25-2 and Figure 25-5, GND changed to GNDOSC. DDRSDRC “DDRSDRC Timing 1 Parameter Register” ,TXSNR field, “Number of cycles is between 0 and HSMCI Section “Description”, SDIO V1.1 changed to SDIO V2.0 PMC Section “Processor Clock Controller”, 2nd and 3rd paragraphs edited. RTC Section “Real Time Clock RTC User Interface”, typo in section title fixed. SPI WDRBT variable and conditional text shown, now appearing in Section “SPI Mode Register” TRNG KEY bitfield added to “TRNG Control Register” TWI Section “Embedded Characteristics”, PDC feature removed from the list. UDPHS Figure 38-3 “Board Schematic”, GND changed to GNDUTMI. UHPHS Figure 37-4 “Board Schematic to Interface UHP High-speed Device Controller”, GND changed to GNDUTMI. Electrical Characteristics Table 47-23, “Analog Inputs”, ’ Input Impedance’ changed in ‘Input Source Impedance’. In the footnote below Table 47-7, “Main Oscillator Characteristics”, gnd changed to gndosc. In the figure below, GNDPLL changed to GNDOSC. ‘pF’ value has to be written this way ‘Pf’ and ‘pf’ removed. Errata Section “ECC Computation with a 1 clock cycle long NRD/NWE pulse”, HECC changed to ECC. Section “UHPHS Packet Loss Issue in the UTMI Transceivers” added. Section “UHPHS/UDPHS USB does not start after power-up”, a clarifying “Or” added to choices in “Workaround”. Change Request Ref. rfo 7332 rfo 7332 7462 7384 7392 7569 7508 7531 7266 7332 7332 7519 7332 rfo 7384 7595 7352 1384 SAM9M10 SAM9M10 6355A Comments Bus Matrix “12-layer” Matrix instead of “11-layer” in Section “Bus Matrix ” DDRSDRC In Section “DDRSDRC Timing 2 Parameter Register”, - TRTP bitfield reset value 0 --> 2 changed. - 0 and 15’ cycles changed into ‘0 and 7’ in ”TRTP Read to Precharge”. - TXARD -->2 , TXARDS -->6 , and TRPA -->0 reset values changed. In Section “DDRSDRC Low-power Register”, UPD_MR bitfield added to the table at In Section “Self Refresh Mode”, UDP_EN bitfield replaced by UPD_MR. Electrical Characteristics - Section “DDRSDRC Timings” edited. - Figure below Table 47-7, “Main Oscillator Characteristics,” on page 1341 Table edited. - Ultra low power Mode value changed in Table 47-3, “Power Consumption for Different Modes” - Section “Maximum SPI Frequency” added. ERRATA - “Boot ROM” errata added. - “Static Memory Controller SMC ” errata added. - “Touch Screen TSADCC ” errata added. - “USB High Speed Host Port UHPHS and Device Port UDPHS ” errata added. - 3 “Error Corrected Code Controller ECC ” errata added “Uncomplete parity status when error in ECC parity” , “Unsupported ECC per 512 words” and “Unsupported hardware ECC on 16-bit Nand Flash” External Memories - DQM0-DQM3 added to Figure 20-4 “EBI Connections to Memory Devices”. - Table 20-5, row ‘A15’ edited. - Section “External Memories” reorganized. - On Figure 6-1 “SAM9M10 Memory Mapping”, ‘DDR2-LPDDR-SDRAM’ --> ‘DDRSDRC1’ and ‘DDR2LPDDR’ --> ‘DDRSDRC20’. - All ‘DDR2SDRC’ changed into ‘DDRSDRC’. Mechanical Characteristics - New Figure 48-1 “324-ball TFBGA Package Drawing” and Max. weight changed in Table 48-2 USART - LIN Mode condition now shown in Section “Universal Synchronous Asynchronous Receiver Transmitter USART ”. VDEC - DivX line removed from Section “Video Decoder VDEC ” First issue Change Request Ref. 7171 7146 6786 7089 49 SAM9M10 Ordering Information 1374 50 SAM9M10 Errata 1375 Headquarters Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131 USA Tel +1 408 441-0311 Fax +1 408 487-2600 International Atmel Asia Limited Unit 01-5 & 16, 19F BEA Tower, Millennium City 5 418 Kwun Tong Road Kwun Tong, Kowloon HONG KONG Tel +852 2245-6100 Fax +852 2722-1369 Atmel Munich GmbH Business Campus Parkring 4 D-85748 Garching b. Munich GERMANY Tel +49 89-31970-0 Fax +49 89-3194621 Atmel Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 JAPAN Tel 81 3-3523-3551 Fax 81 3-3523-7581 Product Contact Web Site Literature Requests Technical Support AT91SAM Support Atmel technical support Sales Contacts Disclaimer The information in this document is provided in connection with Atmel products. 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• 400 MHz ARM926EJ-S Processor 32 KBytes Data Cache, 32 KBytes Instruction Cache, MMU
• Memories DDR2 Controller 4-bank DDR2/LPDDR, SDR/LPSDR External Bus Interface supporting 4-bank DDR2/LPDDR, SDR/LPSDR, Static Memories, SLC NAND Flash with ECC One 64-KByte internal SRAM, single-cycle access at system speed or processor speed through TCM interface One 64-KByte internal ROM, embedding bootstrap routine
• Peripherals Multi-format Video Decoder LCD Controller supporting STN and TFT displays up to 1280*860 ITU-R BT. 601/656 Image Sensor Interface USB Device High Speed, USB Host High Speed and USB Host Full Speed with OnChip Transceiver 10/100 Mbps Ethernet MAC Controller Two High Speed Memory Card Hosts SDIO, SDCard, MMC AC'97 controller Two Master/Slave Serial Peripheral Interfaces Two Three-channel 16-bit Timer/Counters Two Synchronous Serial Controllers I2S mode Four-channel 16-bit PWM Controller Two-wire Interfaces Four USARTs with ISO7816, IrDA, Manchester and SPI modes 8-channel 10-bit ADC with 4-wire Touch Screen support
• System 133 MHz twelve 32-bit layer AHB Bus Matrix 37 DMA Channels Boot from NAND Flash, SDCard, or serial DataFlash Reset Controller with on-chip Power-on Reset Selectable 32768 Hz Low-power and 12 MHz Crystal Oscillators Internal Low-power 32 kHz RC Oscillator One PLL for the system and one 480 MHz PLL optimized for USB High Speed Two Programmable External Clock Signals Advanced Interrupt Controller and Debug Unit Periodic Interval Timer, Watchdog Timer, Real Time Timer and Real Time Clock
• I/O Five 32-bit Parallel Input/Output Controllers 160 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os with Schmitt trigger input
• Package 324-ball TFBGA, pitch mm

AT91SAM ARM-based Embedded MPU

SAM9M10

The SAM9M10 is a multimedia enabled mid-range ARM926-based embedded MPU running at 400MHz, combining user interfaces, video playback and connectivity. It includes hardware video decoder, LCD Controller, resistive touchscreen, camera interface, audio, Ethernet 10/100 and high speed USB and SDIO.

The hardware video decoder supports H.264, MPEG-4, MPEG-2, VC-1, H.263. The SAM9M10 also provides hardware image post-processing, such as image scaling, color conversion and image rotation.

The SAM9M10 supports the latest generation of DDR2 and NAND Flash memory interfaces for program and data storage. An internal 133 MHz multi-layer bus architecture associated with 37 DMA channels, a dual external bus interface and distributed memory including a 64-KByte SRAM which can be configured as a tightly coupled memory TCM sustains the high bandwidth required by the processor and the high speed peripherals.

The I/Os support 1.8V or 3.3V operation, which are independently configurable for the memory interface and peripheral I/Os. This feature completely eliminates the need for any external level shifters. In addition it supports ball pitch package for low cost PCB manufacturing.

The SAM9M10 power management controller features efficient clock gating and a battery backup section minimizing power consumption in active and standby modes.

The SAM9M10 device is particularly well suited for media-rich displays and control panels in home and commercial buildings, POS terminals, entertainment systems, internet appliances and medical.
2 SAM9M10

NTRST TTTTDDCMIOKS RTCK JTAGSEL BMS VHHBFHGSSDDPPAA,,HHFHSSDDMMAA

Block Diagram

Figure SAM9M10 Block Diagram

TST PCK0-PCK1

FIQ IRQ DRXD DTXD

PLLRCA

XIN XOUT

XIN32 XOUT32 SHDN WKUP VDDBU NRST VDDCORE

System Controller

JTAG / Boundary Scan

HS Transceiver

HS Transceiver

DBGU

PLLA PLLUTMI OSC12M

RC OSC 32K SHDC
4 GPBR RTT

POR RSTC

PIOA PIOB PIOC

PIOD PIOE

In-Circuit Emulator

ARM926EJ-S

ICache

DCache
32K bytes MMU 32Kbytes

ITCM DTCM Bus Interface

SRAM 64KB
Data Ordering The RGB color space format is required for viewing images on a display screen preview, and the YCbCr color space format is required for encoding.

All the sensors do not output the YCbCr or RGB components in the same order. The ISI allows the user to program the same component order as the sensor, reducing software treatments to restore the right format.

Table Mode Default Mode1 Mode2 Mode3
Data Ordering in YCbCr Mode

Byte 0

Byte 1

Byte 2 Cr i Cb i Y i+1 Y i+1

Byte 3 Y i+1 Y i+1 Cr i Cb i

Table Mode

RGB 8:8:8

RGB Format in Default Mode, RGB_CFG = 00, No Swap

Byte

Byte 0

Byte 1

Byte 2

Byte 3

R7 i+1 R6 i+1 R5 i+1 R4 i+1

D3 R3 i G3 i B3 i R3 i+1

D2 R2 i G2 i B2 i R2 i+1

D1 R1 i G1 i B1 i R1 i+1

D0 R0 i G0 i B0 i R0 i+1
884 SAM9M10

SAM9M10

Table RGB 5:6:5

RGB Format in Default Mode, RGB_CFG = 00, No Swap

Byte 0

Byte 1

Byte 2

R4 i+1 R3 i+1 R2 i+1 R1 i+1

Byte 3

G2 i+1 G1 i+1 G0 i+1 B4 i+1

R0 i B3 i R0 i+1 B3 i+1

G5 i B2 i G5 i+1 B2 i+1

G4 i B1 i G4 i+1 B1 i+1

G3 i B0 i G3 i+1 B0 i+1

Table Mode

RGB 5:6:5

RGB Format, RGB_CFG = 10 Mode 2 , No Swap

Byte

Byte 0

Byte 1

Byte 2

G2 i+1 G1 i+1 G0 i+1 R4 i+1

Byte 3
This block serializes the data read from memory. It reads words from the FIFO and outputs pixels 1 bit, 2 bits, 4 bits, 8 bits, 16 bits or 24 bits wide depending on the format specified in the PIXELSIZE field of the LCDCON2 register. It also adapts the memory-ordering format. Both bigendian and little-endian formats are supported. They are configured in the MEMOR field of the LCDCON2 register.

The organization of the pixel data in the memory depends on the configuration and is shown in Table 45-5 and Table

Note:

For a color depth of 24 bits per pixel there are two different formats supported packed and unpacked. The packed format needs less memory but has some limitations when working in 2D addressing mode See “2D Memory Addressing” on page
1088 SAM9M10

SAM9M10

Table Little Endian Memory Organization

Mem Addr

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Pixel 1bpp 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Pixel 2bpp 15

Pixel 4bpp

Pixel 8bpp

Pixel 16bpp

Pixel
24bpp
packed

Pixel
24bpp
packed

Pixel
24bpp
packed

Pixel
24bpp
not used
unpacked

Table Big Endian Memory Organization

Mem Addr

Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

Pixel 1bpp 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31

Pixel 2bpp 0

Pixel 4bpp

Pixel 8bpp

Pixel 16bpp

Pixel
24bpp
packed

Pixel
24bpp
packed
• PIXELOFF DAM2D Addressing Pixel offset When 2D DMA addressing is enabled bit DMA2DEN is set in register DMACON , this field specifies the offset of the first pixel in each line within the memory word that contains this pixel. The offset is specified in number of bits in the range 0-31, so for example a value of 4 indicates that the first pixel in the screen starts at bit 4 of the 32-bit word pointed by register DMABADDR1. Bits 0 to 3 of that word are not used. This example is valid for little endian memory organization. When using big endian memory organization, this offset is considered from bit 31 downwards, or equivalently, a given value of this field always selects the pixel in the same relative position within the word, independently of the memory ordering configuration. Bit DMAUPDT in register DMACON must be written after writing any new value to this field in order to make the DMA controller use this new value.
1118 SAM9M10

SAM9M10

LCD Control Register 1 Name LCDCON1

Address:0x00500800

Access Read-write, except LINECNT Read-only

Reset value 0x00002000

LINECNT

CLKVAL

LINECNT

CLKVAL
• BYPASS LCDDOTCK Divider 0 The divider is not bypassed. LCDDOTCK frequency defined by the CLKVAL field.
1 The LCDDOTCK divider is bypassed. LCDDOTCK frequency is equal to the LCDC Clock frequency.
• CLKVAL Clock Divider 9-bit divider for pixel clock LCDDOTCK frequency.

Pixel_clock = system_clock CLKVAL + 1
• LINECNT Line Counter Read-only Current Value of 11-bit line counter. Down count from LINEVAL to
8 0 BYPASS
1119

LCD Control Register 2 Name LCDCON2

Address:0x00500804

Access Read-write

Reset value:

MEMOR

CLKMOD

PIXELSIZE

INVDVAL

INVCLK

IFWIDTH
26 18 10 INVLINE 2 SCANMOD

INVFRAME

INVVD

DISTYPE
• DISTYPE Display Type

DISTYPE

STN Monochrome STN Color TFT Reserved
• SCANMOD Scan Mode 0 Single Scan
1 Dual Scan
• IFWIDTH Interface width STN

IFWIDTH
4-bit Only valid in single scan STN mono or color 8-bit Only valid in STN mono or Color 16-bit Only valid in dual scan STN mono or color Reserved
1120 SAM9M10
• MEMOR Memory Ordering Format 00 Big Endian 10 Little Endian 11 WinCE format

SAM9M10
1121

LCD Timing Configuration Register 1 Name LCDTIM1

Address:0x00500808

Access Read-write

Reset value:

VHDLY
• VFP Vertical Front Porch In TFT mode, these bits equal the number of idle lines at the end of the frame.

In STN mode, these bits should be set to
• VBP Vertical Back Porch In TFT mode, these bits equal the number of idle lines at the beginning of the frame.

In STN mode, these bits should be set to
• VPW Vertical Synchronization pulse width In TFT mode, these bits equal the vertical synchronization pulse width, given in number of lines. LCDVSYNC width is equal to VPW+1 lines.

In STN mode, these bits should be set to
• VHDLY Vertical to horizontal delay In TFT mode, this is the delay between LCDVSYNC rising or falling edge and LCDHSYNC rising edge. Delay is VHDLY+1 LCDDOTCK cycles. Bit 31 must be written to

In STN mode, these bits should be set to
1122 SAM9M10

SAM9M10

LCD Timing Configuration Register 2 Name LCDTIM2

Address:0x0050080C

Access Read-write

Reset value:
• HBP Horizontal Back Porch Number of idle LCDDOTCK cycles at the beginning of the line. Idle period is HBP+1 LCDDOTCK cycles.
• HPW Horizontal synchronization pulse width of the LCDHSYNC pulse, given in LCDDOTCK cycles. Width is HPW+1 LCDDOTCK cycles.
• HFP Horizontal Front Porch Number of idle LCDDOTCK cycles at the end of the line. Idle period is HFP+1 LCDDOTCK cycles.
1123

LCD Frame Configuration Register Name LCDFRMCFG

Address:0x00500810

Access Read-write

Reset value:

LINESIZE

LINESIZE

LINEVAL

LINEVAL
• LINEVAL Vertical size of LCD module In single scan mode vertical size of LCD Module, in pixels, minus 1

In dual scan mode vertical display size of each LCD panel, in pixels, minus 1
• LINESIZE Horizontal size of LCD module, in pixels, minus 1
1124 SAM9M10

SAM9M10

LCD FIFO Register Name LCDFIFO

Address:0x00500814
If post-processing is enabled, one or two additional image transfer operations will take place. If the decoded images are in display order i.e. no picture re-ordering has been made when encoding the sequence , and rotation is not used, PP will process the pictures in pipeline with the decoder. Otherwise, it will first have to read the decoded image that is to be displayed next from the memory 6 , and then write back the processed image
1148 SAM9M10

SAM9M10

Figure Multi-format Decoder and External Memory Data Flow in VLC Mode

External Memory

ARM Processor Core

H.264 NAL

Unit Stream

Decoded

Picture Buffer 6
2 AHB Bus

Post-Processed 7 Picture Buffer

Multiformat HW Decoder Core

Decoder Data Flow, Software Performs Entropy Decoding RLC Mode In this case, the decoder software starts decoding the first picture by parsing the stream headers 1 , and by performing entropy decoding. Software then writes the following items to external memory:
• Run-length-coded RLC data 2
• Differential motion vectors 3
• Intra 4x4 prediction modes in H.264 or separate DC coefficients in MPEG-4, if the stream is using data partitioning 4
• Macroblock control data 5

Last step for the software is to write the hardware control registers and to enable the hardware

Hardware decodes the picture by buffering control data for several macroblocks at a time, and then reads appropriate amount of RLC data, differential motion vectors and intra modes depending on each macroblock type Hardware will also read the reference pictures previously decoded pictures as required Hardware writes decoded in-loop filtered, if H.264 output picture to memory one macroblock at a time When the picture has been fully decoded, hardware gives an interrupt and returns to initial state.
If post-processing is enabled, one or two additional image transfer operations will take place. If the decoded images are in display order i.e. no picture re-ordering has been made when encoding the sequence , and rotation is not used, PP will process the pictures in pipeline with the decoder. Otherwise, it will first have to read the decoded image that is to be displayed next from the memory 13 , and then write back the processed image
1149

Figure Multi-format Decoder and External Memory Data Flow in RLC Mode

External Memory

H.264 NAL

Unit Stream

ARM Processor Core

RLC Data

Differential

Motion

Vectors

Intra 4x4

Modes

Macroblock

Control

Decoded

Picture Buffer

Post-Processed

Picture Buffer
6 AHB Bus

Multiformat HW Decoder Core
1150 SAM9M10

SAM9M10

Product Dependencies

Power Management The Video Decoder requires a peripheral clock. The user has to enable UHP peripheral clock, bit 1 << AT91C_ID_VDEC in PMC_PCER register.

Software can reset the hardware synchronically by writing separate decoder and post-processor enable bits to zero. These enable bits are located in the memory-mapped registers and they can be used for terminating or restarting the decoding or post-processing at any time.

Interrupt

The Video Decoder has an interrupt line connected to the Advanced Interrupt Controller AIC .

Table Peripheral IDs

Instance

VDEC

Handling Video Decoder interrupts requires programming the AIC before.
1151

Video Decoder VDEC User Interface

The VDEC User interface is split into two interfaces.
• One that concerns Post Processor and is common to all Decoder Modes, described by Video Post Processor Register Mapping.
• One in which registers and fields depend on the Decoder Mode used. For best readability this document describes one Register Mapping for each Decoder Mode. The relations are given in Table

Table Register Mapping vs. Decoder Mode

Decoder Mode Refer to the following Register Mapping

H264

Video Decoder Register Mapping H264
• FRAME_NUM Frame Number Current Frame Number, used to identify short-term reference frames. Used in reference picture reordering.
• FRAME_NUM_LEN Frame Number length Bit length of frame_num in data stream.
• W_BIPR Weight Prediction for B Slices H.264 weighted prediction specification for B slices.
• W_PRED Weight Prediction H.264 weighted prediction enable for P slices.
• DIRMV_PRED Derive Luma Method Specifies the method to use to derive luma motion vectors.
• BW Black and White Enable 0 4:2:0 sampling format
1 4:0:0 sampling format
• CABAC H.264 CABAC Enable 0 CABAC disable.
1 CABAC enable.
1166 SAM9M10

SAM9M10

Decoder Control Register 5 H.264 Control

Name:

VDEC_CTLR5

Address:
0x00900020

Access:

Read-write

CONS_INTRA

FILT_CTRL

RD_PIC

T8X8FE

REF_PIC_LEN

REF_PIC_LEN

IDREN

IDR_PIC_ID

IDR_PIC_ID
• IDR_PIC_ID IDR Picture Identifies IDR instantaneous decoding refresh picture.
• IDREN IDR Picture Enable IDR instantaneous decoding refresh picture flag.
• REF_PIC_LEN Reference Picture Length of decoded reference picture marking bits.
• T8X8FE 8x8 Transform Flag Enable 8x8 transform flag enable
• RD_PIC Redundant Picture Present Specifies whether redundant picture count syntax elements are present in the slice header.
• FILT_CTRL Extra Variables Controlling Characteristics of The Deblocking Filter Indicates whether extra variables controlling characteristics of the deblocking filter are present in the slice header.
• CONS_INTRA Intra in Prediction 1 Specifies that intra prediction uses only neighboring intra macroblocks in prediction.
0 Also neighboring inter macroblocks are used in intra prediction process.
1167

Decoder Control Register 6 H.264 RLC Mode

Name:

VDEC_CTLR6

Address:
0x00900024
All devices are marked with the Atmel logo and the ordering code. Additional marking may be in one of the following formats:

YYWW V
where

SAM9M10
1373
SAM9M10 Ordering Information
Table AT91SAM9M10 Ordering Information
Ordering Code

Package

AT91SAM9M10B-CU

TFBGA324

AT91SAM9M10-CU

TFBGA324

Package Type Green

Temperature Operating Range Industrial 40°C to 85°C Industrial 40°C to 85°C
1374 SAM9M10

SAM9M10

SAM9M10 Errata

Boot ROM

Boot ROM NAND Flash boot does not support ECC Correction The boot ROM allows booting from block 0 of a NAND Flash connected on CS3. However, the boot ROM does not feature ECC correction on a NAND Flash.

Most of the NAND Flash vendors do not guarantee anymore that block 0 is error free. Therefore we advise to locate the bootstrap program into another device supported by the boot ROM DataFlash, Serial Flash, SDCARD or EEPROM , and to implement a NAND Flash access with ECC.

Problem Fix/Workaround None.

EMAC

EMAC Setup Timing Violation in RMII Mode A setup timing violation occurs when using the EMAC in RMII mode only with I/Os in a 1.8V range [1.65V:1.95V] and when the line load exceeds 20 pF. The RMII mode is fully functional with I/Os in a 3.3V range [3.0V:3.6V].

Problem Fix/Workaround None.

Error Corrected Code Controller ECC

ECC Computation with a 1 clock cycle long NRD/NWE pulse If the SMC is programmed with NRD/NWE pulse length equal to 1 clock cycle, ECC cannot compute the parity.

Problem Fix/Workaround It is recommended to program SMC with a value superior to

Uncomplete parity status when error in ECC parity When a single correctable error is detected in ECC value, the error is located in ECC Parity register's field which contains a 1 in the 24 least significant bits except when the error is located in the 12th or the 24th bit. In this case, these bits are always stuck at

A Single correctable error is detected but it is impossible to correct it.

Problem Fix/Workaround None.

Unsupported ECC per 512 words 1 bit ECC per 512 words is not functional.

Problem Fix/Workaround Perform the ECC computation by software.
1375

Unsupported hardware ECC on 16-bit Nand Flash Hardware ECC on 16-bit Nand Flash is not supported.

Problem Fix/Workaround Perform the ECC by software.

Pulse Width Modulation Controller PWM

PWM Zero Period It is impossible to update a period equal to 0 by using the PWM_CUPD register.

Problem Fix/Workaround None

Static Memory Controller SMC

SMC Delay Access In this document, the Access is “Read-write” in the Register Mapping Table SMC_DELAY1 to SMC_DELAY8 rows , and in the SMC DELAY I/O Register.

The current access is “Write-only”.

Problem Fix/Workaround None

Serial Synchronous Controller SSC

SSC Data sent without any frame synchro When SSC is configured with the following conditions:
• RF is in input,
• TD is synchronized on a receive START any condition START field = 2 to 7
• TF toggles at each start of data transfer
• Transmit STTDLY = 0
• Check TD and TF after a receive START, The data is sent but there is not any toggle of the TF line

Problem Fix/Workaround Transmit STTDLY must be different from

SSC Unexpected delay on TD output When SSC is configured with the following conditions:
Ordering Information Section “SAM9M10 Ordering Information”, a second ordering code added AT91SAM9M10B-C. An MRL column added too.

Change Request Ref.
7899
7763 7981 7979
7981
7979
1383

Comments

Introduction Product Line/Product naming convention changed - AT91SAM ARM-based MPU / SAM9M10 Section “Power Supplies”, replaced ground pin names by GNDIOM, GNDCORE, GNDANA, GNDIOP, GNDBU, GNDOSC, GNDUTMI. Reorganized text describing GND association to power supply pins

Clock Generator Figure 25-2 and Figure 25-5, GND changed to GNDOSC.

DDRSDRC “DDRSDRC Timing 1 Parameter Register” ,TXSNR field, “Number of cycles is between 0 and

HSMCI Section “Description”, SDIO V1.1 changed to SDIO V2.0

PMC Section “Processor Clock Controller”, 2nd and 3rd paragraphs edited.

RTC Section “Real Time Clock RTC User Interface”, typo in section title fixed.

SPI WDRBT variable and conditional text shown, now appearing in Section “SPI Mode Register”

TRNG KEY bitfield added to “TRNG Control Register”

TWI Section “Embedded Characteristics”, PDC feature removed from the list.

UDPHS Figure 38-3 “Board Schematic”, GND changed to GNDUTMI.

UHPHS Figure 37-4 “Board Schematic to Interface UHP High-speed Device Controller”, GND changed to GNDUTMI.

Electrical Characteristics Table 47-23, “Analog Inputs”, ’ Input Impedance’ changed in ‘Input Source Impedance’. In the footnote below Table 47-7, “Main Oscillator Characteristics”, gnd changed to gndosc. In the figure below, GNDPLL changed to GNDOSC. ‘pF’ value has to be written this way ‘Pf’ and ‘pf’ removed.

Errata Section “ECC Computation with a 1 clock cycle long NRD/NWE pulse”, HECC changed to ECC. Section “UHPHS Packet Loss Issue in the UTMI Transceivers” added. Section “UHPHS/UDPHS USB does not start after power-up”, a clarifying “Or” added to choices in “Workaround”.

Change Request Ref. rfo 7332 rfo 7332
7462
7384 7392 7569 7508 7531 7266 7332
7332
7519 7332 rfo 7384 7595 7352
1384 SAM9M10

SAM9M10
6355A

Comments

Bus Matrix “12-layer” Matrix instead of “11-layer” in Section “Bus Matrix ”

DDRSDRC In Section “DDRSDRC Timing 2 Parameter Register”, - TRTP bitfield reset value 0 --> 2 changed. - 0 and 15’ cycles changed into ‘0 and 7’ in ”TRTP Read to Precharge”. - TXARD -->2 , TXARDS -->6 , and TRPA -->0 reset values changed. In Section “DDRSDRC Low-power Register”, UPD_MR bitfield added to the table at In Section “Self Refresh Mode”, UDP_EN bitfield replaced by UPD_MR.

Electrical Characteristics - Section “DDRSDRC Timings” edited. - Figure below Table 47-7, “Main Oscillator Characteristics,” on page 1341 Table edited. - Ultra low power Mode value changed in Table 47-3, “Power Consumption for Different Modes” - Section “Maximum SPI Frequency” added.

ERRATA - “Boot ROM” errata added. - “Static Memory Controller SMC ” errata added. - “Touch Screen TSADCC ” errata added. - “USB High Speed Host Port UHPHS and Device Port UDPHS ” errata added. - 3 “Error Corrected Code Controller ECC ” errata added “Uncomplete parity status when error in ECC parity” , “Unsupported ECC per 512 words” and “Unsupported hardware ECC on 16-bit Nand Flash”

External Memories - DQM0-DQM3 added to Figure 20-4 “EBI Connections to Memory Devices”. - Table 20-5, row ‘A15’ edited. - Section “External Memories” reorganized. - On Figure 6-1 “SAM9M10 Memory Mapping”, ‘DDR2-LPDDR-SDRAM’ --> ‘DDRSDRC1’ and ‘DDR2LPDDR’ --> ‘DDRSDRC20’. - All ‘DDR2SDRC’ changed into ‘DDRSDRC’.

Mechanical Characteristics - New Figure 48-1 “324-ball TFBGA Package Drawing” and Max. weight changed in Table 48-2

USART - LIN Mode condition now shown in Section “Universal Synchronous Asynchronous Receiver Transmitter USART ”.

VDEC - DivX line removed from Section “Video Decoder VDEC ”

First issue

Change Request Ref. 7171
7146 6786 7089
49 SAM9M10 Ordering Information 1374 50 SAM9M10 Errata 1375

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Datasheet ID: AT91SAM9M10-CU 519128