AT91R40807-33AC

AT91R40807-33AC Datasheet


AT91 Microcontrollers

Part Datasheet
AT91R40807-33AC AT91R40807-33AC AT91R40807-33AC (pdf)
Related Parts Information
AT91R40807-33AU AT91R40807-33AU AT91R40807-33AU
AT91R40807-33AI AT91R40807-33AI AT91R40807-33AI
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• Incorporates the ARM7TDMI ARM Thumb Processor Core High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set Leader in MIPS/Watt Embedded ICE In-circuit Emulation
• 136K Bytes On-chip SRAM 32-bit Data Bus Single-clock Cycle Access
• Fully-programmable External Bus Interface EBI Maximum External Address Space of 64M Bytes Up to 8 Chip Selects Software-programmable 8/16-bit External Databus
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
• 32 Programmable I/O Lines
• 3-channel 16-bit Timer/Counter
3 External Clock Inputs 2 Multi-purpose I/O Pins per Channel
• 2 USARTs 2 Dedicated Peripheral Data Controller PDC Channels per USART
• Programmable Watchdog Timer
• Advanced Power-saving Features CPU and Peripheral Can Be Deactivated Individually
• Fully Static Operation 0 Hz to 33 MHz Internal Frequency Range at 3.0V, 85°C
• 1.8V to 3.6V Operating Range
• -40°C to +85°C Temperature Range
• Available in a 100-lead TQFP Package

AT91 Microcontrollers

AT91R40807 Summary

The AT91R40807 microcontroller is a member of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. This processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications.

The AT91R40807 microcontroller features a direct connection to off-chip memory, including Flash, through the fully-programmable External Bus Interface EBI . An eight-level priority vectored interrupt controller, in conjunction with the Peripheral Data Controller, significantly improves the real-time performance of the device.

The device is manufactured using Atmel’s high-density CMOS technology. By combining the ARM7TDMI processor core with a large on-chip high-speed SRAM and a wide range of peripheral functions on a monolithic chip, the AT91R40807 is a powerful microcontroller that offers a flexible and high-performance solution to many computeintensive embedded control applications.

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Pin Configuration

Figure AT91R40807 Pinout Top View

P10/IRQ1

P11/IRQ2

P12/FIQ

P13/SCK0

P14/TXD0

P15/RXD0

P20/SCK1

P21/TXD1/NTRI

P22/RXD1

NWR1/NUB

NRST

NWDOVF

MCKI

P24/BMS

P25/MCKO

NRD/NOE

NWR0/NWE

NWAIT

NCS0

NCS1

P26/NCS2

P27/NCS3
100-lead TQFP

P9/IRQ0

P8/TIOB2

P7/TIOA2
Product overview Ordering information Packaging information Soldering profile

Document Title ARM7TDMI Thumb Datasheet AT91x40 Series Datasheet AT91R40807 Electrical Characteristics

AT91R40807 Summary Datasheet this document

Product Overview

Power Supply Input/Output Considerations

Master Clock

Reset

NRST Pin

Watchdog Reset

Emulation Functions

Tri-state Mode

The AT91R40807 microcontroller has a unique type of power supply pin VDD. The VDD pin supplies the I/O pads and the device core. The supported voltage range on VDD is 1.8V to 3.6V.

The AT91R40807 accepts voltage levels up to the power supply limit on the pads.

After the reset, the peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase the inputs to the AT91R40807 microcontroller be held at valid logic levels to minimize the power consumption.

The AT91R40807 microcontroller has a fully static design and work on the Master Clock MCK , provided on the MCKI pin from an external source.

The Master Clock is also provided as an output of the device on the pin MCKO, which is multiplexed with a general-purpose I/O line. While NRST is active, MCKO remains low. After the reset, the MCKO is valid and outputs an image of the MCK signal. The PIO controller must be programmed to use this pin as standard I/O line.

Reset restores the default states of the user interface registers defined in the user interface of each peripheral , and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter the ARM7TDMI registers do not have defined reset states.

NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchronized internally to the MCK. The signal presented on MCKI must be active within the specification for a minimum of 10 clock cycles up to the rising edge of NRST to ensure correct operation.

The first processor fetch occurs 80 clock cycles after the rising edge of NRST.

The watchdog can be programmed to generate an internal reset. In this case, the reset has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot mode and Tri-state mode are not updated. If the NRST pin is asserted and the Watchdog triggers the internal reset, the NRST pin has priority.

The AT91R40807 provides a Tri-state mode, which is used for debug purposes. This enables the connection of an emulator probe to an application board without having to desolder the device from the target board. In Tri-state mode, all the output pin drivers of the AT91R40807 microcontroller are disabled.

To enter Tri-state mode, the pin NTRI must be held low during the last 10 clock cycles before the rising edge of NRST. For normal operation the pin NTRI must be held high during reset, by a resistor of up to 400K Ohm.

NTRI is multiplexed with I/O line P21 and USART 1 serial data transmit line TXD1.

Standard RS232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1 is connected to a device not including this pull-up, the user must make sure that a highlevel is tied on NTRI while NRST is asserted.
8 AT91R40807

JTAG/ICE Debug

Memory Controller

Internal Memories

Boot Mode Select

AT91R40807

ARM Standard Embedded In-circuit Emulation is supported via the JTAG/ICE port. The pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be connected to a host computer via the external ICE interface.

In ICE Debug mode, the ARM7TDMI core responds with a non-JTAG chip ID that identifies the microcontroller. This is not fully IEEE1149.1 compliant.

The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the internal 32-bit address bus and defines three address spaces
• Internal memories in the four lowest megabytes
• Middle space reserved for the external devices memory or peripherals controlled
by the EBI
• Internal peripherals in the four highest megabytes

In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only.

The AT91R40807 microcontroller integrates 8K bytes of primary internal SRAM. All internal memories are 32 bits wide and single-clock cycle accessible. Byte 8-bit , halfword 16-bit or word 32-bit accesses are supported and are executed within one cycle. Fetching Thumb or ARM instructions is supported and internal memory can store twice as many Thumb instructions as ARM ones.

The primary SRAM bank is mapped at address 0x0 after the remap command , allowing ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software. The rest of the bank can be used for stack allocation to speed up context saving and restoring or as data and program storage for critical algorithms.

The AT91R40807 also integrates an extended memory bank of 128K bytes at address 0x0010 Placing the SRAM on-chip and using the 32-bit data bus bandwidth maximizes the microcontroller performance and minimizes the system power consumption. The 32-bit bus increases the effectiveness of the use of the ARM instruction set, and the ability of processing data that is wider than 16-bit, thus making optimal use of the ARM7TDMI advanced performance.

Being able to dynamically update application software in the 128-Kbyte SRAM adds an extra dimension to the AT91R40807. This 128-Kbyte SRAM can also be used to validate the code to be stored in the on-chip ROM memory prior to mass production of the AT91M40807. At system boot, the code is downloaded from external nonvolatile memory to this on-chip extended SRAM. In order to prevent accidental write to the extended SRAM during the ROM emulation, a write detection feature has been implemented.

The AT91R40807 microcontroller ROM version AT91M40807 integrates 128K bytes of internal ROM at address 0x0010 The ROM version offers a reduced-cost option for high-volume applications in which the software is stable.

The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI executes the instruction stored at this address. This means that this address must be mapped in nonvolatile memory after the reset.
Ordering Information
Table Ordering Information Ordering Code AT91R40807-33AI

Package TQFP 100

Operation Range

Industrial -40°C to 85°C
14 AT91R40807

Packaging Information

Figure 100-lead Thin Quad Flat Pack Package Drawing
aaa PIN 1

AT91R40807

R1 L1

Table Common Dimensions mm
11°
12°
13°
11°
12°
13°

Tolerances of form and position

Table Lead Count Dimensions mm

D1/E1

Count BSC

Max e BSC ccc

Table Device and 100-lead TQFP Package Maximum Weight
16 AT91R40807

Soldering Profile

AT91R40807

Table 8 gives the recommended soldering profile from J-STD-20.

Table Soldering Profile

Average Ramp-up Rate 183°C to Peak Preheat Temperature 125°C ±25°C Temperature Maintained Above 183°C Time within 5°C of Actual Peak Temperature Peak Temperature Range

Ramp-down Rate Time 25°C to Peak Temperature

Convection or IR/Convection 3°C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec.
220 +5/-0°C or 235 +5/-0°C 6°C/sec. 6 min. max

VPR 10°C/sec.
60 sec. 215 to 219°C or 235 +5/-0°C 10°C/sec.

Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235°C, not 220°C IR reflow .

Recommended package reflow conditions depend on package thickness and volume. See Table

Table Recommended Package Reflow Conditions 1, 2, 3

Parameter

Temperature

Convection
235 +5/-0°C
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Datasheet ID: AT91R40807-33AC 519125