AT91F40816-33CI

AT91F40816-33CI Datasheet

• 1M Words 16-bit Flash Memory 16 Mbits Single Voltage Read/Write, 110 ns Access Time Sector Erase Architecture Fast Word Program Time of 20 µs Fast Sector Erase Time of 200 ms Dual-plane Organization Allows Concurrent Read and Program/Erase Suspend Capability Low-power Operation 25 mA Active - 10 µA Standby Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection Reset Input for Device Initialization Sector Program Unlock Command Factory-programmed AT91 Flash Uploader Software

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AT91F40816-33CI	AT91F40816-33CI (pdf)

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• Incorporates the ARM7TDMI Processor Core High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set Leader in MIPS/Watt Embedded ICE In-circuit Emulation • 8K Bytes On-chip SRAM 32-bit Data Bus, Single-clock Cycle Access • 1M Words 16-bit Flash Memory 16 Mbits Single Voltage Read/Write, 110 ns Access Time Sector Erase Architecture Fast Word Program Time of 20 µs Fast Sector Erase Time of 200 ms Dual-plane Organization Allows Concurrent Read and Program/Erase Suspend Capability Low-power Operation 25 mA Active - 10 µA Standby Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection Reset Input for Device Initialization Sector Program Unlock Command Factory-programmed AT91 Flash Uploader Software • Fully-programmable External Bus Interface EBI Maximum External Address Space of 64M Bytes 8 Chip Selects, Software-programmable 8/16-bit External Data Bus • 8-level Priority, Individually Maskable, Vectored Interrupt Controller 4 External Interrupts, Including a High-priority Low-latency Interrupt Request • 32 Programmable I/O Lines • 3-channel 16-bit Timer/Counter 3 External Clock Inputs 2 Multi-purpose I/O Pins per Channel • 2 USARTs 2 Dedicated Peripheral Data Controller PDC Channels per USART • Programmable Watchdog Timer • Advanced Power-saving Features CPU and Peripherals Can Be Deactivated Individually • Fully Static Operation 0 Hz to 40 MHz Internal Frequency Range at 3.0V, 85°C • 2.7V to 3.6V Operating Range • -40°C to 85°C Temperature Range • Available in a 120-ball BGA Package AT91 Microcontrollers AT91F40816 The AT91F40816 is a member of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. The processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The eight-level priority-vectored interrupt controller, together with the Peripheral Data Controller, significantly enhance real-time device performance. By combining the microcontroller, featuring on-chip SRAM and a wide range of peripheral functions, with 16 Mbits of Flash memory in a single compact 120-ball BGA package, the Atmel AT91F40816 provides a powerful, flexible and cost-effective solution to many compute-intensive embedded control applications and offers significant board size reductions. The Flash memory may be programmed via the JTAG/ICE interface or the factory-programmed Flash Uploader using a single device supply, making the AT91F40816 ideal for in-system programmable applications. Pin Configuration Figure AT91F40816 Pinout Top View P26 NCS0 NCS2 MCKI MCKO P22 RXD1 P21/TXD1 NTRI P27 NCS1 NWAIT TDI NCS3 VDD GND VDD SCK1 P24 NWODVF NWR1 P13 NUB SCK0 RXD0 VDD P23 NRST FIQ IRQ2 TXD0 P10 IRQ1 P9 IRQ0 P8 TIOB2 GND P30/A22 CS5 TCLK2 TIOB1 TIOA2 GND P29/A21 P31/A23 CS6 CS4 TCLK0 TIOA1 TCLK1 GND VDD TIOB0 NCSF NRD NOE GND VDD TIOA0 GND D15 Product overview Ordering information Packaging information Soldering profile Document Title ARM7TDMI Thumb Datasheet AT91x40 Series Datasheet AT91M40800 Electrical Characteristics AT91F40816 Summary Datasheet this document 8 AT91F40816 Product Overview Power Supply Input/Output Considerations Master Clock Reset NRST Pin Watchdog Reset Emulation Functions Tri-state Mode AT91F40816 The AT91F40816 has a single type of power supply pin, VDD. The VDD pin supplies the I/O pads and the core. The supported voltage range on VDD is 2.7V to 3.6V. The AT91F40816 I/O pads are 5V-tolerant except for the EBI Data Bus D0 - D15 . This enables the PIO pads to interface with external 5V devices without any additional components. After the reset, the microcontroller peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase, the inputs to the microcontroller be held at valid logic levels to minimize the power consumption. The AT91F40816 has a fully static design and works on the Master Clock MCK , provided on the MCKI pin from an external source. The Master Clock is also provided as an output of the device on the pin MCKO, which is multiplexed with a general-purpose I/O line. While NRST is active, MCKO remains low. After the reset, the MCKO is valid and outputs an image of the MCK signal. The PIO Controller must be programmed to use this pin as standard I/O line. Reset restores the default states of the user interface registers defined in the user interface of each peripheral , and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter the ARM7TDMI registers do not have defined reset states. NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchronized internally to the MCK. The signal presented on MCKI must be active within the specification for a minimum of 10 clock cycles up to the rising edge of NRST, to ensure correct operation. The first processor fetch occurs 80 clock cycles after the rising edge of NRST. The watchdog can be programmed to generate an internal reset. In this case, the reset has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot mode and Tri-state mode are not updated. If the NRST pin is asserted and the watchdog triggers the internal reset, the NRST pin has priority. The AT91F40816 provides a Tri-state mode, which is used for debug purposes in order to connect an emulator probe to an application board. In Tri-state mode, all the output pin drivers of the microcontroller are disabled. This feature can also be used to program the embedded Flash within a standard NVM programmer. To enter Tri-state mode, the pin NTRI must be held low during the last 10 clock cycles before the rising edge of NRST. For normal operation, the pin NTRI must be held high during reset, by a resistor of up to 400K Ohm. NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1. Standard RS232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1 is connected to a device not including this pull-up, the user must make sure that a high level is tied on NTRI while NRST is asserted. JTAG/ICE Debug ARM standard embedded In-circuit emulation is supported via the JTAG/ICE port. The pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be connected to a host computer via the external ICE interface. In ICE Debug mode, the ARM7TDMI core responds with a non-JTAG chip ID that identifies the microcontroller. This is not fully IEEE1149.1 compliant. Memory Controller The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the internal 32-bit address bus and defines three address spaces • Internal memories in the four lowest megabytes • Middle space reserved for the external devices memory or peripherals controlled by the EBI • Internal peripherals in the four highest megabytes In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only. Internal Memories The AT91F40816 integrates 8K bytes of primary internal SRAM that is 32 bits wide and singleclock cycle accessible. This SRAM is mapped at address 0x0 after the remap command , allowing ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software. The rest of the SRAM can be used for stack allocation to speed up context saving and restoring , or as data and program storage for critical algorithms. Byte 8-bit , half-word 16-bit or word 32-bit accesses are supported and are executed within one cycle. Fetching Thumb or ARM instructions is supported and internal memory can store twice as many Thumb instructions as ARM ones. The AT91F40816 also integrates a 2-Mbyte Flash memory that is accessed via the External Bus Interface. All data, address and control lines, except for the Chip Select signal, are connected within the device. Byte and half-word accesses are supported. Boot Mode Select The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI executes the instruction stored at this address. This means that this address must be mapped in nonvolatile memory after the reset. The input level on the BMS pin during the last 10 clock cycles before the rising edge of the NRST selects the type of boot memory see Table If the embedded Flash memory is to be used as boot memory, the BMS input must be pulled down externally. The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like any standard PIO line. Table Boot Mode Select Boot Memory External 8-bit memory on NCS0 External 16-bit memory on NCS0 Remap Command The ARM vectors Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the software, the AT91F40816 uses a remap command that enables switching between the boot memory and the internal primary SRAM addresses. The remap command is accessible through the EBI User Interface by writing one in RCB of Ordering Information Table Ordering Information Ordering Code AT91F40816-33CI Package BGA 120 AT91F40816 Temperature Operating Range Industrial -40°C to 85°C Packaging Information Figure 120-ball Grid Array Package Drawing 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 A B C D E TOP VIEW F G H J K 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 K J H G F BOTTOM VIEW E D C B A SIDE VIEW −+ −+ −+ All dimensions in millimeters Table Thermal Resistance Data Parameter Condition Package Junction-to- 120-BGA ambient thermal Still Air resistance Junction-to-case thermal resistance 120-BGA Table Device and 120-ball BGA Package Maximum Weight 18 AT91F40816 −+ −+ −+ Units °C/W Soldering Profile AT91F40816 Table 7 gives the recommended soldering profile from J-STD-20. Table Soldering Profile Average Ramp-up Rate 183°C to Peak Preheat Temperature 125°C ±25°C Temperature Maintained Above 183°C Time within 5°C of Actual Peak Temperature Peak Temperature Range Ramp-down Rate Time 25°C to Peak Temperature Convection or IR/Convection 3°C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec. 220 +5/-0°C or 235 +5/-0°C 6°C/sec. 6 min. max VPR 10°C/sec. 60 sec. 215 to 219°C or 235 +5/-0°C 10°C/sec. Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235°C, not 220°C IR reflow . Recommended package reflow conditions depend on package thickness and volume. See Table Table Recommended Package Reflow Conditions 1, 2, 3

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• Incorporates the ARM7TDMI Processor Core High-performance 32-bit RISC Architecture High-density 16-bit Instruction Set Leader in MIPS/Watt Embedded ICE In-circuit Emulation
• 8K Bytes On-chip SRAM 32-bit Data Bus, Single-clock Cycle Access
• 1M Words 16-bit Flash Memory 16 Mbits Single Voltage Read/Write, 110 ns Access Time Sector Erase Architecture Fast Word Program Time of 20 µs Fast Sector Erase Time of 200 ms Dual-plane Organization Allows Concurrent Read and Program/Erase Suspend Capability Low-power Operation 25 mA Active - 10 µA Standby Data Polling, Toggle Bit and Ready/Busy End of Program Cycle Detection Reset Input for Device Initialization Sector Program Unlock Command Factory-programmed AT91 Flash Uploader Software
• Fully-programmable External Bus Interface EBI Maximum External Address Space of 64M Bytes 8 Chip Selects, Software-programmable 8/16-bit External Data Bus
• 8-level Priority, Individually Maskable, Vectored Interrupt Controller 4 External Interrupts, Including a High-priority Low-latency Interrupt Request
• 32 Programmable I/O Lines
• 3-channel 16-bit Timer/Counter
3 External Clock Inputs 2 Multi-purpose I/O Pins per Channel
• 2 USARTs 2 Dedicated Peripheral Data Controller PDC Channels per USART
• Programmable Watchdog Timer
• Advanced Power-saving Features CPU and Peripherals Can Be Deactivated Individually
• Fully Static Operation 0 Hz to 40 MHz Internal Frequency Range at 3.0V, 85°C
• 2.7V to 3.6V Operating Range
• -40°C to 85°C Temperature Range
• Available in a 120-ball BGA Package

AT91 Microcontrollers

AT91F40816

The AT91F40816 is a member of the Atmel AT91 16/32-bit microcontroller family, which is based on the ARM7TDMI processor core. The processor has a high-performance 32-bit RISC architecture with a high-density 16-bit instruction set and very low power consumption. In addition, a large number of internally banked registers result in very fast exception handling, making the device ideal for real-time control applications. The eight-level priority-vectored interrupt controller, together with the Peripheral Data Controller, significantly enhance real-time device performance.

By combining the microcontroller, featuring on-chip SRAM and a wide range of peripheral functions, with 16 Mbits of Flash memory in a single compact 120-ball BGA package, the Atmel AT91F40816 provides a powerful, flexible and cost-effective solution to many compute-intensive embedded control applications and offers significant board size reductions.

The Flash memory may be programmed via the JTAG/ICE interface or the factory-programmed Flash Uploader using a single device supply, making the AT91F40816 ideal for in-system programmable applications.

Pin Configuration

Figure AT91F40816 Pinout Top View

P26 NCS0 NCS2

MCKI

MCKO

P22 RXD1

P21/TXD1 NTRI

P27 NCS1 NWAIT TDI NCS3

VDD GND VDD

SCK1

P24 NWODVF NWR1 P13

NUB SCK0

RXD0

VDD P23 NRST

FIQ IRQ2 TXD0

P10 IRQ1

P9 IRQ0

P8 TIOB2

GND P30/A22 CS5

TCLK2 TIOB1 TIOA2

GND P29/A21 P31/A23 CS6 CS4

TCLK0 TIOA1 TCLK1

GND VDD

TIOB0

NCSF

NRD NOE

GND VDD

TIOA0

GND D15
Product overview Ordering information Packaging information Soldering profile

Document Title ARM7TDMI Thumb Datasheet AT91x40 Series Datasheet AT91M40800 Electrical Characteristics

AT91F40816 Summary Datasheet this document
8 AT91F40816

Product Overview

Power Supply Input/Output Considerations

Master Clock

Reset

NRST Pin

Watchdog Reset

Emulation Functions

Tri-state Mode

AT91F40816

The AT91F40816 has a single type of power supply pin, VDD. The VDD pin supplies the I/O pads and the core. The supported voltage range on VDD is 2.7V to 3.6V.

The AT91F40816 I/O pads are 5V-tolerant except for the EBI Data Bus D0 - D15 . This enables the PIO pads to interface with external 5V devices without any additional components. After the reset, the microcontroller peripheral I/Os are initialized as inputs to provide the user with maximum flexibility. It is recommended that in any application phase, the inputs to the microcontroller be held at valid logic levels to minimize the power consumption.

The AT91F40816 has a fully static design and works on the Master Clock MCK , provided on the MCKI pin from an external source. The Master Clock is also provided as an output of the device on the pin MCKO, which is multiplexed with a general-purpose I/O line. While NRST is active, MCKO remains low. After the reset, the MCKO is valid and outputs an image of the MCK signal. The PIO Controller must be programmed to use this pin as standard I/O line.

Reset restores the default states of the user interface registers defined in the user interface of each peripheral , and forces the ARM7TDMI to perform the next instruction fetch from address zero. Except for the program counter the ARM7TDMI registers do not have defined reset states.

NRST is active low-level input. It is asserted asynchronously, but exit from reset is synchronized internally to the MCK. The signal presented on MCKI must be active within the specification for a minimum of 10 clock cycles up to the rising edge of NRST, to ensure correct operation. The first processor fetch occurs 80 clock cycles after the rising edge of NRST.

The watchdog can be programmed to generate an internal reset. In this case, the reset has the same effect as the NRST pin assertion, but the pins BMS and NTRI are not sampled. Boot mode and Tri-state mode are not updated. If the NRST pin is asserted and the watchdog triggers the internal reset, the NRST pin has priority.

The AT91F40816 provides a Tri-state mode, which is used for debug purposes in order to connect an emulator probe to an application board. In Tri-state mode, all the output pin drivers of the microcontroller are disabled. This feature can also be used to program the embedded Flash within a standard NVM programmer. To enter Tri-state mode, the pin NTRI must be held low during the last 10 clock cycles before the rising edge of NRST. For normal operation, the pin NTRI must be held high during reset, by a resistor of up to 400K Ohm. NTRI is multiplexed with I/O line P21 and USART1 serial data transmit line TXD1.

Standard RS232 drivers generally contain internal 400K Ohm pull-up resistors. If TXD1 is connected to a device not including this pull-up, the user must make sure that a high level is tied on NTRI while NRST is asserted.

JTAG/ICE Debug

ARM standard embedded In-circuit emulation is supported via the JTAG/ICE port. The pins TDI, TDO, TCK and TMS are dedicated to this debug function and can be connected to a host computer via the external ICE interface.

In ICE Debug mode, the ARM7TDMI core responds with a non-JTAG chip ID that identifies the microcontroller. This is not fully IEEE1149.1 compliant.

Memory Controller

The ARM7TDMI processor address space is 4G bytes. The memory controller decodes the internal 32-bit address bus and defines three address spaces
• Internal memories in the four lowest megabytes
• Middle space reserved for the external devices memory or peripherals controlled by the

EBI
• Internal peripherals in the four highest megabytes

In any of these address spaces, the ARM7TDMI operates in Little-Endian mode only.

Internal Memories

The AT91F40816 integrates 8K bytes of primary internal SRAM that is 32 bits wide and singleclock cycle accessible. This SRAM is mapped at address 0x0 after the remap command , allowing ARM7TDMI exception vectors between 0x0 and 0x20 to be modified by the software. The rest of the SRAM can be used for stack allocation to speed up context saving and restoring , or as data and program storage for critical algorithms. Byte 8-bit , half-word 16-bit or word 32-bit accesses are supported and are executed within one cycle. Fetching Thumb or ARM instructions is supported and internal memory can store twice as many Thumb instructions as ARM ones.

The AT91F40816 also integrates a 2-Mbyte Flash memory that is accessed via the External Bus Interface. All data, address and control lines, except for the Chip Select signal, are connected within the device. Byte and half-word accesses are supported.

Boot Mode Select

The ARM reset vector is at address 0x0. After the NRST line is released, the ARM7TDMI executes the instruction stored at this address. This means that this address must be mapped in nonvolatile memory after the reset.

The input level on the BMS pin during the last 10 clock cycles before the rising edge of the NRST selects the type of boot memory see Table If the embedded Flash memory is to be used as boot memory, the BMS input must be pulled down externally.

The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like any standard PIO line.

Table Boot Mode Select

Boot Memory

External 8-bit memory on NCS0

External 16-bit memory on NCS0

Remap Command

The ARM vectors Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction, Interrupt, Fast Interrupt are mapped from address 0x0 to address 0x20. In order to allow these vectors to be redefined dynamically by the software, the AT91F40816 uses a remap command that enables switching between the boot memory and the internal primary SRAM addresses. The remap command is accessible through the EBI User Interface by writing one in RCB of
Ordering Information
Table Ordering Information
Ordering Code AT91F40816-33CI

Package BGA 120

AT91F40816

Temperature Operating Range

Industrial -40°C to 85°C

Packaging Information

Figure 120-ball Grid Array Package Drawing
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

A B C D E TOP VIEW F G H J K
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

K J H G F BOTTOM VIEW E D C B A

SIDE VIEW
−+ −+ −+

All dimensions in millimeters

Table Thermal Resistance Data

Parameter

Condition

Package

Junction-to-
120-BGA
ambient thermal

Still Air
resistance

Junction-to-case thermal resistance
120-BGA

Table Device and 120-ball BGA Package Maximum Weight
18 AT91F40816
−+ −+ −+

Units °C/W

Soldering Profile

AT91F40816

Table 7 gives the recommended soldering profile from J-STD-20.

Table Soldering Profile

Average Ramp-up Rate 183°C to Peak Preheat Temperature 125°C ±25°C Temperature Maintained Above 183°C Time within 5°C of Actual Peak Temperature Peak Temperature Range

Ramp-down Rate Time 25°C to Peak Temperature

Convection or IR/Convection 3°C/sec. max. 120 sec. max 60 sec. to 150 sec. 10 sec. to 20 sec. 220 +5/-0°C or 235 +5/-0°C 6°C/sec. 6 min. max

VPR 10°C/sec.
60 sec. 215 to 219°C or 235 +5/-0°C 10°C/sec.

Small packages may be subject to higher temperatures if they are reflowed in boards with larger components. In this case, small packages may have to withstand temperatures of up to 235°C, not 220°C IR reflow .

Recommended package reflow conditions depend on package thickness and volume. See Table

Table Recommended Package Reflow Conditions 1, 2, 3

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Datasheet ID: AT91F40816-33CI 519111