The AT28HC64B is a high-performance electrically-erasable and programmable readonly memory EEPROM . Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 100 µA.
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AT28HC64B-70TC (pdf) |
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AT28HC64B-12JC |
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AT28HC64B-90PC |
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AT28HC64B-70PC |
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PDF Datasheet Preview |
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• Fast Read Access Time 55 ns • Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes • Fast Write Cycle Times Page Write Cycle Time 10 ms Maximum Standard 2 ms Maximum Option 1 to 64-byte Page Write Operation • Low Power Dissipation 40 mA Active Current 100 µA CMOS Standby Current • Hardware and Software Data Protection • DATA Polling and Toggle Bit for End of Write Detection • High Reliability CMOS Technology Endurance 100,000 Cycles Data Retention 10 Years • Single 5 V ±10% Supply • CMOS and TTL Compatible Inputs and Outputs • JEDEC Approved Byte-wide Pinout • Commercial and Industrial Temperature Ranges • Green Pb/Halide-free Packaging Option 64K 8K x 8 High Speed Parallel EEPROM with Page Write and Software Data Protection The AT28HC64B is a high-performance electrically-erasable and programmable readonly memory EEPROM . Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 55 ns with power dissipation of just 220 mW. When the device is deselected, the CMOS standby current is less than 100 µA. The AT28HC64B is accessed like a Static RAM for the read or write cycle without the need for external components. The device contains a 64-byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin. Atmel’s AT28HC64B has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking. AT28HC64B AT28HC64B Pin Configurations Pin Name A0 - A12 CE OE WE I/O0 - I/O7 NC DC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect 28-lead PDIP/SOIC Top View NC 1 A12 2 A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O0 11 I/O1 12 I/O2 13 GND 14 28 VCC 27 WE 26 NC 25 A8 24 A9 23 A11 22 OE 21 A10 20 CE 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3 32-lead PLCC Top View 28-lead TSOP Top View OE 1 A11 2 A9 3 A8 4 NC 5 WE 6 VCC 7 NC 8 A12 9 A7 10 A6 11 A5 12 A4 13 A3 14 28 A10 27 CE 26 I/O7 25 I/O6 24 I/O5 23 I/O4 22 I/O3 21 GND 20 I/O2 19 I/O1 18 I/O0 17 A0 16 A1 15 A2 4 A7 3 A12 2 NC 1 DC 32 VCC 31 WE 30 NC A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 I/O0 13 29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 21 I/O6 I/O1 14 I/O2 15 GND 16 DC 17 I/O3 18 I/O4 19 I/O5 20 Note PLCC package pins 1 and 17 are Don’t Connect. Block Diagram AT28HC64B VCC GND OE WE CE ADDRESS INPUTS OE, CE and WE LOGIC Y DECODER X DECODER DATA INPUTS/OUTPUTS I/O0 - I/O7 DATA LATCH INPUT/OUTPUT BUFFERS Y-GATING CELL MATRIX IDENTIFICATION Parameter Write Cycle Time Write Cycle Time Option Available Contact Atmel Sales Office for Ordering Part Number Address Setup Time Address Hold Time Data Setup Time Data Hold Time Write Pulse Width Byte Load Cycle Time Write Pulse Width High Page Mode Write Waveforms 1 2 CE WE A0 -A12 DATA tAS tAH VALID ADD VALID DATA tWP tDH tWPH 0 50 0 100 50 tBLC AT28HC64B Units Notes A6 through A12 must specify the same page address during each high to low transition of WE or CE . OE must be high only when WE and CE are both low. Chip Erase Waveforms tS = tH = 5 µs min. tW = 10 ms min. VH = V Software Data Protection Enable Algorithm 1 LOAD DATA AA TO ADDRESS 1555 LOAD DATA 55 TO ADDRESS 0AAA LOAD DATA A0 TO ADDRESS 1555 WRITES ENABLED 2 LOAD DATA XX TO ANY ADDRESS 4 LOAD LAST BYTE TO LAST ADDRESS ENTER DATA PROTECT STATE Data Format I/O7 - I/O0 Hex Address Format A12 - A0 Hex . Write Protect state will be activated at end of write even if no other data is loaded. Write Protect state will be deactivated at end of write period even if no other data is loaded. 1 to 64 bytes of data are loaded. Software Data Protection Disable Algorithm 1 LOAD DATA AA TO ADDRESS 1555 LOAD DATA 55 TO ADDRESS 0AAA LOAD DATA 80 TO ADDRESS 1555 LOAD DATA AA TO ADDRESS 1555 Ordering Information 1 Standard Package tACC ICC mA Active Standby Ordering Code AT28HC64B-55JC AT28HC64B-55PC AT28HC64B-55SC AT28HC64B-70JC AT28HC64B-70PC AT28HC64B-70SC AT28HC64B-70TC AT28HC64B-70JI AT28HC64B-70PI AT28HC64B-70SI AT28HC64B-70TI AT28HC64B-90JC AT28HC64B-90PC AT28HC64B-90SC AT28HC64B-90TC AT28HC64B-90JI AT28HC64B-90PI AT28HC64B-90SI AT28HC64B-90TI AT28HC64B-12JC AT28HC64B-12PC AT28HC64B-12SC AT28HC64B-12TC AT28HC64B-12JI AT28HC64B-12PI AT28HC64B-12SI AT28HC64B-12TI Note See “Valid Part Numbers” on page Green Package Option Pb/Halide-free tACC ICC mA Active Standby Ordering Code AT28HC64B-90JU AT28HC64B-90PU AT28HC64B-90SU AT28HC64B-90TU Package 32J 28P6 28S 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T 32J 28P6 28S 28T Package 32J 28P6 28S 28T 32J 28P6 28S 28T W Package Type 32-lead, Plastic J-leaded Chip Carrier PLCC 28-lead, Wide, Plastic Dual Inline Package PDIP 28-lead, Wide, Plastic Gull Wing Small Outline SOIC 28-lead, Plastic Thin Small Outline Package TSOP Die AT28HC64B Operation Range Commercial 0°C to 70°C Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C Commercial 0°C to 70°C Industrial -40°C to 85°C Operation Range Industrial -40°C to 85°C Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28HC64B PC, SC AT28HC64B JI, PC, PI, SC, SI, TC, TI AT28HC64B JI, JU, PC, PI, PU, SC, SI, SU, TC, TI, TU AT28HC64B JI, PC, PI, SC, SI, TC, TI AT28HC64B Die Products Reference Section Parallel EEPROM Die Products 14 AT28HC64B Packaging Information 32J PLCC AT28HC64B PIN NO. 1 IDENTIFIER e D1 D B1 E2 A2 A1 A 0.51 0.020 MAX 3X COMMON DIMENSIONS Unit of Measure = mm This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum. |
More datasheets: SB180E-G | SB140E-G | CS61535A-IL1ZR | CS61535A-IL1Z | AT28HC64B-90TC | AT28HC64B-90JC | AT28HC64B-12SC | AT28HC64B-90SC | AT28HC64B-12JC | AT28HC64B-90PC |
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