AT28C040-25FC

AT28C040-25FC Datasheet

The AT28C040 is a high-performance electrically erasable and programmable read

Part	Datasheet
AT28C040-25FC	AT28C040-25FC (pdf)

Related Parts	Information
AT28C040-20BI	AT28C040-20BI
AT28C040-25BI	AT28C040-25BI
AT28C040-25FI	AT28C040-25FI
AT28C040-25LC	AT28C040-25LC
AT28C040-25LI	AT28C040-25LI
AT28C040-25BC	AT28C040-25BC
AT28C040-20FC	AT28C040-20FC
AT28C040-20BC	AT28C040-20BC
AT28C040-20LC	AT28C040-20LC

PDF Datasheet Preview
• Read Access Time - 200 ns • Automatic Page Write Operation Internal Address and Data Latches for 256 Bytes Internal Control Timer • Fast Write Cycle Time Page Write Cycle Time - 10 ms Maximum 1 to 256 Byte Page Write Operation • Low Power Dissipation 80 mA Active Current • Hardware and Software Data Protection • DATA Polling for End of Write Detection • High Reliability CMOS Technology Endurance 10,000 Cycles Data Retention 10 Years • Single 5V ± 10% Supply • CMOS and TTL Compatible Inputs and Outputs • JEDEC Approved Byte-Wide Pinout The AT28C040 is a high-performance electrically erasable and programmable read only memory EEPROM . Its 4 megabits of memory is organized as 524,288 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 440 mW. continued Pin Configurations Pin Name A0 - A18 CE OE WE I/O0 - I/O7 NC Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect LCC Top View SIDE BRAZE, FLATPACK Top View 6 A15 5 A16 4 A18 3 NC 2 NC 1 NC 44 VCC 43 WE 42 NC 41 A17 40 A14 A12 7 A7 8 A6 9 A5 10 NC 11 NC 12 NC 13 A4 14 A3 15 A2 16 A1 17 39 A13 38 A8 37 A9 36 A11 35 NC 34 NC 33 NC 32 NC 31 OE 30 A10 29 CE A18 1 A16 2 A15 3 A12 4 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GND 16 32 VCC 31 WE 30 A17 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3 4-Megabit 512K x 8 Paged Parallel EEPROMs AT28C040 A0 18 I/O0 19 I/O1 20 I/O2 21 VSS 22 NC 23 I/O3 24 I/O4 25 I/O5 26 I/O6 27 I/O7 28 The AT28C040 is accessed like a static RAM for the read or write cycle without the need for external components. The device contains a 256-byte page register to allow writing of up to 256 bytes simultaneously. During a write cycle, the address and 1 to 256 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA POLLING of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin. Atmel's AT28C040 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 256 bytes of EEPROM for device identification or tracking. Block Diagram Absolute Maximum Ratings* Temperature Under Bias -55°C to +125°C Storage Temperature -65°C to +150°C All Input Voltages including NC pins with Respect to Ground ...................................-0.6V to +6.25V All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. AT28C040 AT28C040 Device Operation READ The AT28C040 is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their systems. BYTE WRITE A low pulse on the WE or CE input with CE or WE low respectively and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation. PAGE WRITE The page write operation of the AT28C040 allows 1 to 256 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write the first byte written can then be followed by 1 to 255 additional bytes. Each successive byte must be written within 150 µs tBLC of the previous byte. If the tBLC limit is exceeded, the AT28C040 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A8 - A18 inputs. For each WE high to low transition during the page write operation, A8 - A18 must be the same. The A0 to A7 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written unnecessary cycling of other bytes within the page does not occur. DATA POLLING The AT28C040 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle. TOGGLE BIT In addition to DATA Polling, the AT28C040 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle. Ordering Information 1 tACC ICC mA Active Standby Note See Valid Part Numbers. Ordering Code AT28C040-20BC AT28C040-20FC AT28C040-20LC AT28C040-20BI AT28C040-20FI AT28C040-20LI AT28C040-20BI SL703 AT28C040-20FI SL703 AT28C040-20LI SL703 AT28C040-25BC AT28C040-25FC AT28C040-25LC AT28C040-25BI AT28C040-25FI AT28C040-25LI AT28C040-25BI SL703 AT28C040-25FI SL703 AT28C040-25LI SL703 Package 32B 32F 44L 32B 32F 44L 32B 32F 44L 32B 32F 44L 32B 32F 44L 32B 32F 44L Valid Part Numbers The following table lists standard Atmel products that can be ordered. Device Numbers Speed Package and Temperature Combinations AT28C040 BC, BI, FC, FI, LC, LI, BI SL703, FI SL703, LI SL703 AT28C040 BC, BI, FC, FI, LC, LI, BI SL703, FI SL703, LI SL703 Die Products Reference Section Parallel EEPROM Die Products Operation Range Commercial 0° to 70°C Industrial -40° to 85°C Extended See DC and AC Operating Range Table Commercial 0° to 70°C Industrial -40° to 85°C Extended See DC and AC Operating Range Table 32B 32F 44L Blank Package Type 32-Lead, Wide, Ceramic Side Braze Dual Inline Side Braze 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package Flatpack 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier LCC Options Standard Device Endurance = 10K Write Cycles Write Time = 10 ms AT28C040 Packaging Information 32B, 32-Lead, Wide, Ceramic Side Braze Dual Inline Side Braze Dimensions in Inches and Millimeters 44L, 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier LCC Dimensions in Inches and Millimeters MIL-STD-1835 C-5 AT28C040

PDF Datasheet Preview

• Read Access Time - 200 ns
• Automatic Page Write Operation

Internal Address and Data Latches for 256 Bytes Internal Control Timer
• Fast Write Cycle Time Page Write Cycle Time - 10 ms Maximum 1 to 256 Byte Page Write Operation
• Low Power Dissipation 80 mA Active Current
• Hardware and Software Data Protection
• DATA Polling for End of Write Detection
• High Reliability CMOS Technology Endurance 10,000 Cycles Data Retention 10 Years
• Single 5V ± 10% Supply
• CMOS and TTL Compatible Inputs and Outputs
• JEDEC Approved Byte-Wide Pinout

The AT28C040 is a high-performance electrically erasable and programmable read
only memory EEPROM . Its 4 megabits of memory is organized as 524,288 words by
8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device
offers access times to 200 ns with power dissipation of just 440 mW.
continued

Pin Configurations

Pin Name A0 - A18 CE OE WE I/O0 - I/O7 NC

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect

LCC Top View

SIDE BRAZE, FLATPACK Top View
6 A15 5 A16 4 A18 3 NC 2 NC 1 NC 44 VCC 43 WE 42 NC 41 A17 40 A14

A12 7 A7 8 A6 9 A5 10 NC 11 NC 12 NC 13 A4 14 A3 15 A2 16 A1 17
39 A13 38 A8 37 A9 36 A11 35 NC 34 NC 33 NC 32 NC 31 OE 30 A10 29 CE

A18 1 A16 2 A15 3 A12 4

A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 I/O0 13 I/O1 14 I/O2 15 GND 16
32 VCC 31 WE 30 A17 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 I/O7 20 I/O6 19 I/O5 18 I/O4 17 I/O3
4-Megabit 512K x 8 Paged Parallel EEPROMs AT28C040

A0 18 I/O0 19 I/O1 20 I/O2 21 VSS 22 NC 23 I/O3 24 I/O4 25 I/O5 26 I/O6 27 I/O7 28

The AT28C040 is accessed like a static RAM for the read or write cycle without the need for external components. The device contains a 256-byte page register to allow writing of up to 256 bytes simultaneously. During a write cycle, the address and 1 to 256 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by

DATA POLLING of I/O7. Once the end of a write cycle has been detected, a new access for a read or write can begin.

Atmel's AT28C040 has additional features to ensure high quality and manufacturability. The device utilizes internal error correction for extended endurance and improved data retention characteristics. An optional software data protection mechanism is available to guard against inadvertent writes. The device also includes an extra 256 bytes of EEPROM for device identification or tracking.

Block Diagram

Absolute Maximum Ratings*

Temperature Under Bias -55°C to +125°C

Storage Temperature -65°C to +150°C

All Input Voltages including NC pins with Respect to Ground ...................................-0.6V to +6.25V

All Output Voltages with Respect to Ground .............................-0.6V to VCC + 0.6V

Voltage on OE and A9 with Respect to Ground ...................................-0.6V to +13.5V
*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

AT28C040

AT28C040

Device Operation

READ The AT28C040 is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dualline control gives designers flexibility in preventing bus contention in their systems.

BYTE WRITE A low pulse on the WE or CE input with CE or WE low respectively and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation.

PAGE WRITE The page write operation of the AT28C040 allows 1 to 256 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write the first byte written can then be followed by 1 to 255 additional bytes. Each successive byte must be written within 150 µs tBLC of the previous byte. If the tBLC limit is exceeded, the AT28C040 will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A8 - A18 inputs. For each WE high to low transition during the page write operation, A8 - A18 must be the same.

The A0 to A7 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written unnecessary cycling of other bytes within the page does not occur.

DATA POLLING The AT28C040 features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle.

TOGGLE BIT In addition to DATA Polling, the AT28C040 provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.
Ordering Information 1
tACC

ICC mA

Active Standby

Note See Valid Part Numbers.
Ordering Code

AT28C040-20BC AT28C040-20FC AT28C040-20LC

AT28C040-20BI AT28C040-20FI AT28C040-20LI

AT28C040-20BI SL703 AT28C040-20FI SL703 AT28C040-20LI SL703

AT28C040-25BC AT28C040-25FC AT28C040-25LC

AT28C040-25BI AT28C040-25FI AT28C040-25LI

AT28C040-25BI SL703 AT28C040-25FI SL703 AT28C040-25LI SL703

Package
32B 32F 44L
32B 32F 44L
32B 32F 44L
32B 32F 44L
32B 32F 44L
32B 32F 44L

Valid Part Numbers

The following table lists standard Atmel products that can be ordered.

Device Numbers

Speed Package and Temperature Combinations

AT28C040

BC, BI, FC, FI, LC, LI, BI SL703, FI SL703, LI SL703

AT28C040

BC, BI, FC, FI, LC, LI, BI SL703, FI SL703, LI SL703

Die Products

Reference Section Parallel EEPROM Die Products

Operation Range Commercial 0° to 70°C

Industrial -40° to 85°C

Extended See DC and AC Operating

Range Table Commercial 0° to 70°C

Industrial -40° to 85°C

Extended See DC and AC Operating

Range Table
32B 32F 44L

Blank

Package Type 32-Lead, Wide, Ceramic Side Braze Dual Inline Side Braze 32-Lead, Non-Windowed, Ceramic Bottom-Brazed Flat Package Flatpack 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier LCC

Options Standard Device Endurance = 10K Write Cycles Write Time = 10 ms

AT28C040

Packaging Information
32B, 32-Lead, Wide, Ceramic Side Braze Dual Inline Side Braze Dimensions in Inches and Millimeters
44L, 44-Pad, Non-Windowed, Ceramic Leadless Chip Carrier LCC Dimensions in Inches and Millimeters *

MIL-STD-1835 C-5

AT28C040

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Datasheet ID: AT28C040-25FC 518967