CYW43241XFKWBGT
CYW43241XFKWBGT Datasheet
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CYW43241XFKWBGT |
CYW43241XFKWBGT (pdf) |
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| Not Recommended for New Designs The following document contains information on Cypress products. Although the document is marked with the name “Broadcom”, the company that originally developed the specification, Cypress will continue to offer these products to new and existing customers. CONTINUITY OF ORDERING PART NUMBERS Cypress continues to support existing part numbers. To order these products, please use only the Ordering Part Numbers listed in this document. FOR MORE INFORMATION Please visit our website at or contact your local sales office for additional information about Cypress products and services. OUR CUSTOMERS Cypress is for true innovators in companies both large and small. ABOUT CYPRESS Founded in 1982, Cypress is the leader in advanced embedded system solutions for the world’s most innovative automotive, industrial, home automation and appliances, consumer electronics and medical products. Cypress’s programmable systems-on-chip, general-purpose microcontrollers, analog ICs, wireless and USB-based connectivity solutions and reliable, high-performance memories help engineers design differentiated products and get them to market first. Cypress is committed to providing customers with the best support and engineering resources on the planet enabling innovators and out-of-the-box thinkers to disrupt markets and create new product categories in record time. To learn more, go to • San Jose, CA 95134-1709 • 408-943-2600 Not Recommended for New Designs Advance Data Sheet BCM43241 Single-Chip IEEE a/b/g/n 2x2 MAC/Baseband/Radio with Integrated Bluetooth + HS and FM Receiver The BCM43241 single-chip device provides the highest level of integration for a mobile or handheld wireless system, with integrated IEEE a/b/g and 2x2 IEEE 802.11n MAC/ baseband/radio, Bluetooth + HS, and FM radio receiver. The BCM43241 takes advantage of the high throughput and extended range of the Broadcom second-generation MIMO solution. With MIMO, the information is sent and received over two or more antennas, simultaneously using the same frequency band, thus providing greater range and higher throughput, while maintaining compatibility with legacy IEEE 802.11a/b/g devices. This is accomplished through a combination of enhanced MAC and PHY implementations including spatial multiplexing modes in the transmitter and receiver, and advanced digital signal processing techniques to improve receive sensitivity. The BCM43241 architecture with its fully integrated dual-band radio transceiver supports 2 x 2 antennas. It also supports 20 and 40 MHz channels allowing for PHY Layer throughput up to 300 Mbps. Using advanced design techniques and process technology to reduce active and idle power, the BCM43241 is designed to address the needs of highly mobile devices that require minimal power consumption and compact size. It includes a power management unit that simplifies the system power topology and allows for operation directly from a mobile platform battery while maximizing battery life. The BCM43241 also includes power saving schemes such as single-core listen OCL , single-core demodulation of SISO/STBC packets, and Dynamic ML. The BCM43241 implements the highly sophisticated Enhanced Collaborative Coexistence radio coexistence algorithms and hardware mechanisms, allowing for an extremely collaborative Bluetooth coexistence scheme along with coexistence support for external radios such as GPS, WiMAX, or Ultra Wideband radio technologies, as well as cellular radios and a single shared GHz antenna for Bluetooth and WLAN. As a result, enhanced overall quality for simultaneous voice, video, and data transmission on a handheld system is achieved. For the WLAN section, two alternative host interface options are included an SDIO v3.0 interface, which can operate in 4 bit, 1 bit, or gSPI modes, and a HighSpeed Inter-Chip HSIC interface a USB derivative for short-distance on-board connections . An independent, high-speed UART is provided for the Bluetooth host interface. WLAN Host I/F SDIO / SPI HSIC BT Host I/F UART PCM FM Host I/F UART VIO BCM43241 5G WLAN 2G WLAN 5G WLAN T/R Switch T/R Switch T/R Switch 2G WLAN Tx 2G WL/BT Rx BT Tx 3PST Switch FM Rx Ant1 Diplexer Ant0 Diplexer Figure 1 Functional Block Diagram 5300 California Avenue • Irvine, CA 92617 • Phone 949-926-5000 • Fax 949-926-5203 43241-DS103-R May 21, 2012 Not Recommended for New Designs BCM43241 Advance Data Sheet IEEE 802.11x Key Features • Single-band GHz IEEE b/g/n or dual-band GHz and 5 GHz IEEE a/ b/g/n • Hardware support for virtual simultaneous dual band operation with sub 1 ms band switching time • Dual-stream IEEE 802.11n support for 20 MHz and 40 MHz channels provides PHY layer rates up to 300 Mbps for typical upperlayer throughput in excess of 200 Mbps • Supports the IEEE 802.11n STBC space-time block coding in both TX and RX for improved range and power efficiency • Contains integrated GHz and 5 GHz Power Amplifiers as well as 11 RF control signals available to control external RF switches or LNAs Updated • “Ordering Information” on page Initial release BROADCOM May 21, 2012 • 43241-DS103-R Page 5 Not Recommended for New Designs BCM43241 Advance Data Sheet Table of Contents Table of Contents About This Purpose and Audience Acronyms and Document Conventions Technical Section 1 Overview 17 Features Standards Mobile Device Usage Model Section 2 Power Supplies and Power Management 23 Power Supply BCM43241 PMU WLAN Power PMU Sequencing Power-off Shutdown Power-Up/Power-Down/Reset Section 3 Frequency References 28 Crystal Interface and Clock Generation TCXO Frequency Selection External kHz Low-Power Section 4 Bluetooth + FM Subsystem 33 Features Bluetooth Transmit Digital Demodulator and Bit Power Amplifier Receiver Digital Demodulator and Bit Receiver Signal Strength Local Oscillator BROADCOM May 21, 2012 • 43241-DS103-R Page 6 Not Recommended for New Designs BCM43241 Advance Data Sheet Table of Contents Section 5 Bluetooth Baseband 37 Bluetooth Low Energy Link Control Test Mode Bluetooth Power Management Unit RF Power Management Host Controller Power BBC Power Management FM Power Management Wideband Speech Packet Loss Concealment Audio Rate-Matching Algorithms Codec Multiple Simultaneous A2DP Audio Stream FM Over Bluetooth Burst Buffer Operation Adaptive Frequency Advanced Bluetooth/WLAN Coexistence Fast Connection Interlaced Page and Inquiry Scans Section 6 Music and Audio 45 MP3 Decoder AAC/AAC+ Decoder Section 7 Microprocessor and Memory Unit for 46 RAM, ROM, and Patch Reset Section 8 Bluetooth Peripheral Transport Unit 47 PCM Interface Slot Frame Synchronization Data Wideband Speech Support Multiplexed Bluetooth and FM Over Burst PCM BROADCOM May 21, 2012 • 43241-DS103-R Page 7 Not Recommended for New Designs BCM43241 Advance Data Sheet Table of Contents PCM Interface Timing Short Frame Sync, Master Mode Short Frame Sync, Slave Mode Long Frame Sync, Master Mode Long Frame Sync, Slave Mode Short Frame Sync, Burst Mode Long Frame Sync, Burst Mode UART Interface I2S Interface Section 25 Ordering Information 166 Section 26 Pin List 167 Not Recommended for New Designs BROADCOM May 21, 2012 • 43241-DS103-R Page 11 BCM43241 Advance Data Sheet List of Figures Not Recommended for New Designs List of Figures Figure 1 Functional Block Figure 2 BCM43241 Block Diagram Figure 3 Mobile Phone Block System Figure 4 Typical Power Figure 5 Recommended Oscillator Configuration Figure 6 Recommended Circuit to Use with an External Dedicated Figure 7 Recommended Circuit to Use with an External Shared Figure 8 Start-up Signaling Figure 9 CVSD Decoder Output Waveform Without PLC Figure 10 CVSD Decoder Output Waveform After Applying PLC Figure 11 Functional Multiplex Data Figure 12 PCM Timing Diagram Short Frame Sync, Master Figure 13 PCM Timing Diagram Short Frame Sync, Slave Figure 14 PCM Timing Diagram Long Frame Sync, Master Figure 15 PCM Timing Diagram Long Frame Sync, Slave Figure 16 PCM Burst Mode Timing Receive Only, Short Frame Sync Figure 17 PCM Burst Mode Timing Receive Only, Long Frame Sync Figure 18 UART Timing Figure 19 I2S Transmitter Figure 20 I2S Receiver Figure 21 Example Blend/Switch Usage Figure 22 Example Blend/Switch Separation Figure 23 Example Soft Mute Characteristic Figure 24 Signal Connections to SDIO Host SD 4-Bit Mode Figure 25 Signal Connections to SDIO Host SD 1-Bit Mode Figure 26 Signal Connections to SDIO Host gSPI Mode Figure 27 gSPI Write Protocol Figure 28 gSPI Read Protocol Figure 29 gSPI Command Figure 30 gSPI Signal Timing Without Figure 31 gSPI Signal Timing with Status Response Delay = 0 Figure 32 WLAN Bootup Sequence Figure 33 HSIC Device Block Figure 34 WLAN MAC Architecture Figure 35 WLAN PHY Block Diagram BROADCOM May 21, 2012 • 43241-DS103-R Page 12 Not Recommended for New Designs BCM43241 Advance Data Sheet List of Figures Figure 36 STBC Receive Block Diagram Figure 37 Radio Functional Block Figure 38 208-Ball FCFBGA Ball Map Top Figure 39 RF Port Location for Bluetooth Testing Figure 40 Port Figure 41 SDIO Bus Timing Default Figure 42 SDIO Bus Timing High-Speed Mode Figure 43 SDIO Clock Timing SDR Figure 44 SDIO Bus Input Timing SDR Modes Figure 45 SDIO Bus Output Timing SDR Modes up to 100 Figure 46 SDIO Bus Output Timing SDR Modes 100 MHz to 208 MHz Figure 47 Consideration for Variable Data Window SDR 104 Mode Figure 48 SDIO Clock Timing DDR50 Figure 49 SDIO Data Timing DDR50 Figure 50 gSPI Timing Figure 51 WLAN = ON, Bluetooth = Figure 52 WLAN = OFF, Bluetooth = Figure 53 WLAN = ON, Bluetooth = Figure 54 WLAN = OFF, Bluetooth = Figure 55 208-Ball FCFBGA Package Mechanical Information BROADCOM May 21, 2012 • 43241-DS103-R Page 13 BCM43241 Advance Data Sheet List of Tables Not Recommended for New Designs List of Tables Table 1 Power-Up/Power-Down/Reset Control Table 2 Crystal Oscillator and External Clock Requirements and Performance Table 3 External kHz Sleep Clock Table 4 Power Control Pin Description Table 5 PCM Interface Timing Specifications Short Frame Sync, Master Table 6 PCM Interface Timing Specifications Short Frame Sync, Slave Mode Table 7 PCM Interface Timing Specifications Long Frame Sync, Master Table 8 PCM Interface Timing Specifications Long Frame Sync, Slave Mode Table 9 PCM Burst Mode Receive Only, Short Frame Sync Table 10 PCM Burst Mode Receive Only, Long Frame Sync Table 11 Example of Common Baud Table 12 UART Timing Specifications Table 13 Timing for I2S Transmitters and Table 14 SDIO Pin Table 15 gSPI Status Field Table 16 gSPI Table 17 FCFBGA Signal Descriptions Table 18 WLAN GPIO Functions and Strapping Options Advance Information Table 19 OTP Table 20 WLAN GPIO Functions and Strapping Options Advance Information Table 21 GPIO Multiplexing Matrix Table 22 Multiplexed GPIO Table 23 I/O States Table 24 Absolute Maximum Table 25 Environmental Table 26 ESD Table 27 Recommended Operating Conditions and DC Characteristics Table 28 Bluetooth Receiver RF Specifications Table 29 Bluetooth Transmitter RF Specifications Table 30 Local Oscillator Table 31 BLE RF Specifications Table 32 FM Receiver Specifications Table 33 GHz Band General RF Table 34 WLAN GHz Receiver Performance Specifications Table 35 WLAN GHz Transmitter Performance BROADCOM May 21, 2012 • 43241-DS103-R Page 14 Not Recommended for New Designs BCM43241 Advance Data Sheet List of Tables Table 36 WLAN 5 GHz Receiver Performance Specifications 131 Table 37 WLAN 5 GHz Transmitter Performance Table 38 General Spurious Emissions Table 39 Core Buck Switching Regulator CBUCK Specifications Table 40 LDO3P3 Specifications Table 41 CLDO Specifications Table 42 LNLDO2 Specifications Table 43 LNLDO1 Specifications Table 44 BCM43241 WLAN Current Consumption GHz Table 45 BCM43241 WLAN Current Consumption 5 GHz Table 46 BT Current Consumption Table 47 BLE Current Consumption Table 48 FM Current Consumption Table 49 SDIO Bus Timing Parameters Default Table 50 SDIO Bus Timing Parameters High-Speed Table 51 SDIO Bus Clock Timing Parameters SDR Table 52 SDIO Bus Input Timing Parameters SDR Modes Table 53 SDIO Bus Output Timing Parameters SDR Modes up to 100 MHz Table 54 SDIO Bus Output Timing Parameters SDR Modes 100 MHz to 208 MHz Table 55 SDIO Bus Clock Timing Parameters DDR50 Table 56 SDIO Bus Timing Parameters DDR50 Mode Table 57 gSPI Timing Parameters Table 58 HSIC Timing Parameters Table 59 JTAG Timing Table 60 Package JEDEC Thermal Characteristics Table 61 208-Pin FCFBGA Package Pin List By Pin Table 62 208-Pin FCFBGA Package Pin List By Pin Name BROADCOM May 21, 2012 • 43241-DS103-R Page 15 Not Recommended for New Designs BCM43241 Advance Data Sheet About This Document About This Document Purpose and Audience This data sheet provides details about the functional, operational, and electrical characteristics of the Broadcom BCM43241. It is intended for hardware design, application, and OEM engineers. Acronyms and Abbreviations In most cases, acronyms and abbreviations are defined on first use. For a comprehensive list of acronyms and other terms used in Broadcom documents, go to: Document Conventions Ordering Information Section 25 Ordering Information Part Number BCM43241FKFFBG BCM43241GKFFBG BCM43241XKFFBG BCM43241DKFFBG BCM43241ZKFFBG Package FCFBGA mm x mm, mm pitch FCFBGA mm x mm, mm pitch FCFBGA mm x mm, mm pitch FCFBGA mm x mm, mm pitch FCFBGA mm x mm, mm pitch Description Single-band GHz WLAN + BT + FM Rx Single-band GHz WLAN + BT Dual-band GHz and 5 GHz WLAN + BT + FM Dual-band WLAN + BT Dual-band WLAN Operating Ambient Temperature to +85°C to +85°C to +85°C to +85°C to +85°C BROADCOM May 21, 2012 • 43241-DS103-R Page 166 BCM43241 Advance Data Sheet Pin List Not Recommended for New Designs Section 26 Pin List This section presents the pin list for the BCM43241 device • Table 61 “208-Pin FCFBGA Package Pin List By Pin Number,” on page 167 • Table 62 “208-Pin FCFBGA Package Pin List By Pin Name,” on page 170 Table 61 208-Pin FCFBGA Package Pin List By Pin Number Name BT_UART_TXD BT_LPO_IN BT_PCM_CLK BT_PCM_OUT RF_SW_CTRL_7 RF_SW_CTRL_5 RF_SW_CTRL_1 GMODE_EXT_LNA_PU_CORE0 GMODE_PA_EN_CORE0 A10 GPIO_7 A11 GPIO_6 A12 GPIO_3/TMS A13 GPIO_0/WL_HOST_WAKE A14 GPIO_1/WL_DEV_WAKE A15 SR_VLX A16 SR_VLX |
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