AT28BV64B-20JI

AT28BV64B-20JI Datasheet


The AT28BV64B is a high-performance electrically erasable programmable read onlymemory EEPROM . Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 20 µA.

Part Datasheet
AT28BV64B-20JI AT28BV64B-20JI AT28BV64B-20JI (pdf)
Related Parts Information
AT28BV64B-20PI AT28BV64B-20PI AT28BV64B-20PI
AT28BV64B-20TI AT28BV64B-20TI AT28BV64B-20TI
AT28BV64B-20SI AT28BV64B-20SI AT28BV64B-20SI
PDF Datasheet Preview
• Single 2.7V to 3.6V Supply
• Hardware and Software Data Protection
• Low Power Dissipation
15 mA Active Current 20 µA CMOS Standby Current
• Fast Read Access Time 200 ns
• Automatic Page Write Operation Internal Address and Data Latches for 64 Bytes Internal Control Timer
• Fast Write Cycle Times Page Write Cycle Time 10 ms Maximum 1 to 64 Byte Page Write Operation
• DATA Polling for End of Write Detection
• High-reliability CMOS Technology Endurance 100,000 Cycles Data Retention 10 Years
• JEDEC Approved Byte-wide Pinout
• Industrial Temperature Ranges
• Green Pb/Halide-free Packaging Option

The AT28BV64B is a high-performance electrically erasable programmable read onlymemory EEPROM . Its 64K of memory is organized as 8,192 words by 8 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the device offers access times to 200 ns with power dissipation of just 54 mW. When the device is deselected, the CMOS standby current is less than 20 µA.

The AT28BV64B is accessed like a static RAM for the read or write cycle without the need for external components. The device contains a 64 byte page register to allow writing of up to 64 bytes simultaneously. During a write cycle, the addresses and 1 to 64 bytes of data are internally latched, freeing the address and data bus for other operations. Following the initiation of a write cycle, the device will automatically write the latched data using an internal control timer. The end of a write cycle can be detected by DATA polling of I/O7. Once the end of a write cycle has been detected a new access for a read or write can begin.

Atmel’s AT28BV64B has additional features to ensure high quality and manufacturability. A software data protection mechanism guards against inadvertent writes. The device also includes an extra 64 bytes of EEPROM for device identification or tracking.
64K 8K x 8 Battery-Voltage Parallel EEPROM with Page Write and Software Data Protection

AT28BV64B

Pin Configurations

Pin Name A0 - A12 CE OE WE I/O0 - I/O7 NC DC

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect Don’t Connect
28-lead PDIP/SOIC Top View

NC 1 A12 2

A7 3 A6 4 A5 5 A4 6 A3 7 A2 8 A1 9 A0 10 I/O0 11 I/O1 12 I/O2 13 GND 14
28 VCC 27 WE 26 NC 25 A8 24 A9 23 A11 22 OE 21 A10 20 CE 19 I/O7 18 I/O6 17 I/O5 16 I/O4 15 I/O3
32-lead PLCC Top View
4 A7 3 A12 2 NC 1 DC 32 VCC 31 WE 30 NC

A6 5 A5 6 A4 7 A3 8 A2 9 A1 10 A0 11 NC 12 I/O0 13
29 A8 28 A9 27 A11 26 NC 25 OE 24 A10 23 CE 22 I/O7 21 I/O6

I/O1 14 I/O2 15 GND 16 DC 17 I/O3 18 I/O4 19 I/O5 20

Note PLCC package pins 1 and 17 are Don’t Connect.
28-lead TSOP Top View

OE 1 A11 2

A9 3 A8 4 NC 5 WE 6 VCC 7 NC 8 A12 9 A7 10 A6 11 A5 12 A4 13 A3 14
28 A10 27 CE 26 I/O7 25 I/O6 24 I/O5 23 I/O4 22 I/O3 21 GND 20 I/O2 19 I/O1 18 I/O0 17 A0 16 A1 15 A2
2 AT28BV64B

Block Diagram

AT28BV64B

Device Operation

Read

The AT28BV64B is accessed like a static RAM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state when either CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention in their systems.

Byte Write Page Write

A low pulse on the WE or CE input with CE or WE low respectively and OE high initiates a write cycle. The address is latched on the falling edge of CE or WE, whichever occurs last. The data is latched by the first rising edge of CE or WE. Once a byte write has been started, it will automatically time itself to completion. Once a programming operation has been initiated and for the duration of tWC, a read operation will effectively be a polling operation.

The page write operation of the AT28BV64B allows 1 to 64 bytes of data to be written into the device during a single internal programming period. A page write operation is initiated in the same manner as a byte write the first byte written can then be followed by 1 to 63 additional bytes. Each successive byte must be written within 100 µs tBLC of the previous byte. If the tBLC limit is exceeded, the AT28BV64B will cease accepting data and commence the internal programming operation. All bytes during a page write operation must reside on the same page as defined by the state of the A6 to A12 inputs. For each WE high to low transition during the page write operation, A6 to A12 must be the same.

The A0 to A5 inputs specify which bytes within the page are to be written. The bytes may be loaded in any order and may be altered within the same load period. Only bytes which are specified for writing will be written unnecessary cycling of other bytes within the page does not occur.

DATA Polling

The AT28BV64B features DATA Polling to indicate the end of a write cycle. During a byte or page write cycle an attempted read of the last byte written will result in the complement of the written data to be presented on I/O7. Once the write cycle has been completed, true data is valid on all outputs, and the next write cycle may begin. DATA Polling may begin at anytime during the write cycle.

Toggle Bit

In addition to DATA Polling, the AT28BV64B provides another method for determining the end of a write cycle. During the write operation, successive attempts to read data from the device will result in I/O6 toggling between one and zero. Once the write has completed, I/O6 will stop toggling and valid data will be read. Reading the toggle bit may begin at any time during the write cycle.

Data Protection

If precautions are not taken, inadvertent writes may occur during transitions of the host system power supply. has incorporated both hardware and software features that will protect the memory against inadvertent writes.

Hardware Protection
Ordering Information 1

Standard Package
tACC

ICC mA

Active

Standby

Note See “Valid Part Numbers” below.
Ordering Code

AT28BV64B-20JI AT28BV64B-20PI AT28BV64B-20SI AT28BV64B-20TI

Green Package Option Pb/Halide-free
tACC

ICC mA

Active

Standby
Ordering Code

AT28BV64B-20JU

AT28BV64B-20TU

AT28BV64B-20SU

Package 32J 28P6 28S 28T

Package 32J 28T 28S
32J 28P6 28S 28T

Package Type 32-lead, Plastic J-leaded Chip Carrier PLCC 28-lead, Wide, Plastic Dual Inline Package PDIP 28-lead, Wide, Plastic Gull Wing Small Outline SOIC 28-lead, Plastic Thin Small Outline Package TSOP

Valid Part Numbers

The following table lists standard Atmel products that can be ordered.

Device Numbers

Speed

Package and Temperature Combinations

AT28BV64B

JI, JU, PI, SI, SU, TI, TU

Operation Range Industrial
-40° C to 85° C

Operation Range Industrial
-40° C to 85° C
12 AT28BV64B

Packaging Information
32J PLCC

AT28BV64B

PIN NO. 1 IDENTIFIER
e D1 D

B1 E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2
10/04/01

TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
28P6 PDIP

D PIN 1

SEATING PLANE
0º ~ 15º REF

This package conforms to JEDEC reference MS-011, Variation AB. Dimensions D and E1 do not include mold Flash or Protrusion.
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Datasheet ID: AT28BV64B-20JI 518964