CY7C1425AV18-167BZXC

CY7C1425AV18-167BZXC Datasheet

CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18

Part	Datasheet
CY7C1425AV18-167BZXC	CY7C1425AV18-167BZXC (pdf)

Related Parts	Information
CY7C1414AV18-200BZC	CY7C1414AV18-200BZC
CY7C1414AV18-250BZC	CY7C1414AV18-250BZC
CY7C1414AV18-200BZI	CY7C1414AV18-200BZI
CY7C1412AV18-250BZXC	CY7C1412AV18-250BZXC
CY7C1414AV18-167BZI	CY7C1414AV18-167BZI
CY7C1414AV18-167BZCT	CY7C1414AV18-167BZCT
CY7C1414AV18-167BZC	CY7C1414AV18-167BZC
CY7C1425AV18-200BZC	CY7C1425AV18-200BZC
CY7C1412AV18-200BZC	CY7C1412AV18-200BZC
CY7C1412AV18-200BZI	CY7C1412AV18-200BZI
CY7C1412AV18-250BZC	CY7C1412AV18-250BZC
CY7C1414AV18-200BZXC	CY7C1414AV18-200BZXC
CY7C1425AV18-250BZXC	CY7C1425AV18-250BZXC
CY7C1412AV18-167BZXI	CY7C1412AV18-167BZXI
CY7C1425AV18-200BZXC	CY7C1425AV18-200BZXC
CY7C1412AV18-200BZXC	CY7C1412AV18-200BZXC
CY7C1412AV18-167BZC	CY7C1412AV18-167BZC

PDF Datasheet Preview
CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 36-Mbit QDR-II SRAM 2-Word Burst Architecture Functional Description • Separate Independent Read and Write data ports Supports concurrent transactions • 250-MHz clock for high bandwidth • 2-Word Burst on all accesses • Double Data Rate DDR interfaces on both Read and Write ports data transferred at 500 MHz 250 MHz • Two input clocks K and K for precise DDR timing SRAM uses rising edges only • Two input clocks for output data C and C to minimize clock-skew and flight-time mismatches • Echo clocks CQ and CQ simplify data capture in high-speed systems • Single multiplexed address input bus latches address inputs for both Read and Write ports • Separate Port Selects for depth expansion • Synchronous internally self-timed writes • Available in x8, x9, x18, and x36 configurations • Full data coherency, providing most current data • Core VDD = 1.8V ±0.1V I/O VDDQ = 1.4V to VDD • Available in 165-ball FBGA package 15 x 17 x mm • Offered in both lead-free and non lead-free packages • Variable drive HSTL output buffers • JTAG compatible test access port • Delay Lock Loop DLL for accurate data placement Configurations CY7C1410AV18 4M x 8 CY7C1425AV18 4M x 9 CY7C1412AV18 2M x 18 CY7C1414AV18 1M x 36 The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR -II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate DDR interfaces. Each address location is associated with two 8-bit words CY7C1410AV18 or 9-bit words CY7C1425AV18 or 18-bit words CY7C1412AV18 or 36-bit words CY7C1414AV18 that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.” Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently. All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry. Selection Guide Maximum Operating Frequency Maximum Operating Current 250 MHz 250 1065 200 MHz 200 870 167 MHz 167 740 Unit MHz mA Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 [+] Feedback Logic Block Diagram CY7C1410AV18 D[7:0] 8 A 20:0 21 K DOFF Address Register CLK Gen. VREF WPS NWS[1:0] Control Logic Write Reg Write Reg 2M x 8 Array 2M x 8 Array Read Data Reg. 16 8 Write Add. Decode Read Add. Decode CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 Address Register 21 A 20:0 Control Logic Ordering Information Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 167 CY7C1410AV18-167BZC 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1425AV18-167BZC CY7C1412AV18-167BZC CY7C1414AV18-167BZC CY7C1410AV18-167BZXC 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1425AV18-167BZXC CY7C1412AV18-167BZXC CY7C1414AV18-167BZXC CY7C1410AV18-167BZI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1425AV18-167BZI CY7C1412AV18-167BZI CY7C1414AV18-167BZI CY7C1410AV18-167BZXI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1425AV18-167BZXI CY7C1412AV18-167BZXI CY7C1414AV18-167BZXI 200 CY7C1410AV18-200BZC 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Commercial CY7C1425AV18-200BZC CY7C1412AV18-200BZC CY7C1414AV18-200BZC CY7C1410AV18-200BZXC 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1425AV18-200BZXC CY7C1412AV18-200BZXC CY7C1414AV18-200BZXC CY7C1410AV18-200BZI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1425AV18-200BZI CY7C1412AV18-200BZI CY7C1414AV18-200BZI CY7C1410AV18-200BZXI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1425AV18-200BZXI CY7C1412AV18-200BZXI CY7C1414AV18-200BZXI 250 CY7C1410AV18-250BZC 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Ordering Information continued Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered. Speed MHz Ordering Code Package Diagram Package Type Operating Range 250 CY7C1410AV18-250BZI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Industrial CY7C1425AV18-250BZI CY7C1412AV18-250BZI CY7C1414AV18-250BZI CY7C1410AV18-250BZXI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Lead-Free CY7C1425AV18-250BZXI CY7C1412AV18-250BZXI CY7C1414AV18-250BZXI Package Diagram 165-ball FBGA 15 x 17 x mm 51-85195 ! " # % & ' * + , 0 2 ! " # % & ' * + , 0 2 51-85195-*A QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC, and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders. Page 24 of 25 Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18 Document History Page Document Title 36-Mbit QDR-II SRAM 2-Word Burst Architecture Document Number 38-05615 Orig. of ECN No. Issue Date Change Description of Change 247331 See ECN SYT New Data Sheet 326519 See ECN SYT Removed CY7C1425AV18 from the title Included 300 MHz Speed grade Replaced TBDs with their respective values for IDD and ISB1 Added Industrial temperature grade Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 17.2°C/W and ΘJC = 3.2°C/W Replaced TBDs in the Capacitance Table to their respective values for the 165 FBGA Package Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS TRI-STATE on Page 16 Added lead-free Product Information Updated the Ordering Information by Shading and Unshading MPNs as per availability 413953 See ECN NXR Converted from preliminary to final. Added CY7C1425AV18 part number to title. Removed 300-MHz speed Bin. Changed address of Cypress Semiconductor Corporation on Page# 1 from “3901 North First Street” to “198 Champion Court” Changed C, C Description in Feature Section and Pin Description. Added Power-up sequence and Wave form on page# 19 Added foot notes # 13, 14, 15 on page# 19 Replaced Three-state with Tri-state. Changed the description of IX from Input Load Current to Input Leakage Current on page# 20 Modified the IDD and ISB values. Modified test condition in Footnote # 20 on page# 20 from VDDQ < VDD to VDDQ < VDD. Replaced Package Name column with Package Diagram in the Ordering Information table. Updated Ordering Information Table. 468029 See ECN NXR Modified the ZQ Definition from Alternately, this pin can be connected directly to VDD to Alternately, this pin can be connected directly to VDDQ. Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD. Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table Modified Power-Up waveform Changed the Maximum rating of Ambient Temperature with Power Applied from to +85°C to +125°C Added additional notes in the AC parameter section Changed the tSC and tHC value for 250 MHz from ns to ns, for 200 MHz from ns to ns, and for 167 MHz from ns to ns. Modified AC Switching Waveform. Corrected the typo In the AC Switching Characteristics Table. Updated the Ordering Information Table. Page 25 of 25 [+] Feedback

PDF Datasheet Preview

CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18
36-Mbit QDR-II SRAM 2-Word Burst Architecture

Functional Description
• Separate Independent Read and Write data ports Supports concurrent transactions
• 250-MHz clock for high bandwidth
• 2-Word Burst on all accesses
• Double Data Rate DDR interfaces on both Read and

Write ports data transferred at 500 MHz 250 MHz
• Two input clocks K and K for precise DDR timing

SRAM uses rising edges only
• Two input clocks for output data C and C to minimize
clock-skew and flight-time mismatches
• Echo clocks CQ and CQ simplify data capture in
high-speed systems
• Single multiplexed address input bus latches address
inputs for both Read and Write ports
• Separate Port Selects for depth expansion
• Synchronous internally self-timed writes
• Available in x8, x9, x18, and x36 configurations
• Full data coherency, providing most current data
• Core VDD = 1.8V ±0.1V I/O VDDQ = 1.4V to VDD
• Available in 165-ball FBGA package 15 x 17 x mm
• Offered in both lead-free and non lead-free packages
• Variable drive HSTL output buffers
• JTAG compatible test access port
• Delay Lock Loop DLL for accurate data placement

Configurations

CY7C1410AV18 4M x 8 CY7C1425AV18 4M x 9 CY7C1412AV18 2M x 18 CY7C1414AV18 1M x 36

The CY7C1410AV18, CY7C1425AV18, CY7C1412AV18, and CY7C1414AV18 are 1.8V Synchronous Pipelined SRAMs, equipped with QDR -II architecture. QDR-II architecture consists of two separate ports to access the memory array. The Read port has dedicated Data Outputs to support Read operations and the Write Port has dedicated Data Inputs to support Write operations. QDR-II architecture has separate data inputs and data outputs to completely eliminate the need to “turn-around” the data bus required with common I/O devices. Access to each port is accomplished through a common address bus. The Read address is latched on the rising edge of the K clock and the Write address is latched on the rising edge of the K clock. Accesses to the QDR-II Read and Write ports are completely independent of one another. In order to maximize data throughput, both Read and Write ports are equipped with Double Data Rate DDR interfaces. Each address location is associated with two 8-bit words CY7C1410AV18 or 9-bit words CY7C1425AV18 or 18-bit words CY7C1412AV18 or 36-bit words CY7C1414AV18 that burst sequentially into or out of the device. Since data can be transferred into and out of the device on every rising edge of both input clocks K and K and C and C , memory bandwidth is maximized while simplifying system design by eliminating bus “turn-arounds.”

Depth expansion is accomplished with Port Selects for each port. Port selects allow each port to operate independently.

All synchronous inputs pass through input registers controlled by the K or K input clocks. All data outputs pass through output registers controlled by the C or C or K or K in a single clock domain input clocks. Writes are conducted with on-chip synchronous self-timed write circuitry.

Selection Guide

Maximum Operating Frequency Maximum Operating Current
250 MHz 250 1065
200 MHz 200 870
167 MHz 167 740

Unit MHz mA

Cypress Semiconductor Corporation
• 198 Champion Court
• San Jose, CA 95134-1709
• 408-943-2600
[+] Feedback

Logic Block Diagram CY7C1410AV18

D[7:0] 8

A 20:0 21

K DOFF

Address Register

CLK Gen.

VREF WPS

NWS[1:0]

Control Logic

Write Reg

Write Reg
2M x 8 Array 2M x 8 Array

Read Data Reg. 16 8

Write Add. Decode Read Add. Decode

CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18

Address Register
21 A 20:0

Control Logic
Ordering Information

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
167 CY7C1410AV18-167BZC 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1425AV18-167BZC

CY7C1412AV18-167BZC

CY7C1414AV18-167BZC

CY7C1410AV18-167BZXC 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1425AV18-167BZXC

CY7C1412AV18-167BZXC

CY7C1414AV18-167BZXC

CY7C1410AV18-167BZI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1425AV18-167BZI

CY7C1412AV18-167BZI

CY7C1414AV18-167BZI

CY7C1410AV18-167BZXI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1425AV18-167BZXI

CY7C1412AV18-167BZXI

CY7C1414AV18-167BZXI
200 CY7C1410AV18-200BZC 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm

Commercial

CY7C1425AV18-200BZC

CY7C1412AV18-200BZC

CY7C1414AV18-200BZC

CY7C1410AV18-200BZXC 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1425AV18-200BZXC

CY7C1412AV18-200BZXC

CY7C1414AV18-200BZXC

CY7C1410AV18-200BZI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1425AV18-200BZI

CY7C1412AV18-200BZI

CY7C1414AV18-200BZI

CY7C1410AV18-200BZXI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1425AV18-200BZXI

CY7C1412AV18-200BZXI

CY7C1414AV18-200BZXI
250 CY7C1410AV18-250BZC 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm
Ordering Information continued

Not all of the speed, package and temperature ranges are available. Please contact your local sales representative or visit for actual products offered.

Speed MHz
Ordering Code

Package Diagram

Package Type

Operating Range
250 CY7C1410AV18-250BZI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm

Industrial

CY7C1425AV18-250BZI

CY7C1412AV18-250BZI

CY7C1414AV18-250BZI

CY7C1410AV18-250BZXI 51-85195 165-ball Fine Pitch Ball Grid Array 15 x 17 x mm Lead-Free

CY7C1425AV18-250BZXI

CY7C1412AV18-250BZXI

CY7C1414AV18-250BZXI

Package Diagram
165-ball FBGA 15 x 17 x mm 51-85195
! " # % & ' * + , 0 2
! " # % & ' * + , 0 2
51-85195-*A

QDR RAMs and Quad Data Rate RAMs comprise a new family of products developed by Cypress, Hitachi, IDT, NEC, and Samsung technology. All product and company names mentioned in this document are the trademarks of their respective holders.

Page 24 of 25

Cypress Semiconductor Corporation, The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
[+] Feedback

CY7C1410AV18 CY7C1425AV18 CY7C1412AV18 CY7C1414AV18

Document History Page

Document Title 36-Mbit QDR-II SRAM 2-Word Burst Architecture Document Number 38-05615

Orig. of ECN No. Issue Date Change

Description of Change
247331 See ECN SYT New Data Sheet
326519 See ECN SYT Removed CY7C1425AV18 from the title

Included 300 MHz Speed grade

Replaced TBDs with their respective values for IDD and ISB1 Added Industrial temperature grade

Replaced the TBDs on the Thermal Characteristics Table to ΘJA = 17.2°C/W and ΘJC = 3.2°C/W Replaced TBDs in the Capacitance Table to their respective values for the
165 FBGA Package

Changed typo of bit # 47 to bit # 108 under the EXTEST OUTPUT BUS

TRI-STATE on Page 16

Added lead-free Product Information
Updated the Ordering Information by Shading and Unshading MPNs as per
availability
413953 See ECN NXR Converted from preliminary to final.

Added CY7C1425AV18 part number to title.

Removed 300-MHz speed Bin.

Changed address of Cypress Semiconductor Corporation on Page# 1 from
“3901 North First Street” to “198 Champion Court”

Changed C, C Description in Feature Section and Pin Description.

Added Power-up sequence and Wave form on page# 19

Added foot notes # 13, 14, 15 on page# 19

Replaced Three-state with Tri-state.

Changed the description of IX from Input Load Current to Input Leakage Current on page# 20
Modified the IDD and ISB values. Modified test condition in Footnote # 20 on page# 20 from VDDQ < VDD to VDDQ < VDD. Replaced Package Name column with Package Diagram in the Ordering

Information table.
Updated Ordering Information Table.
468029 See ECN NXR Modified the ZQ Definition from Alternately, this pin can be connected directly
to VDD to Alternately, this pin can be connected directly to VDDQ. Included Maximum Ratings for Supply Voltage on VDDQ Relative to GND Changed the Maximum Ratings for DC Input Voltage from VDDQ to VDD. Changed tTH and tTL from 40 ns to 20 ns, changed tTMSS, tTDIS, tCS, tTMSH, tTDIH, tCH from 10 ns to 5 ns and changed tTDOV from 20 ns to 10 ns in TAP AC Switching Characteristics table

Modified Power-Up waveform

Changed the Maximum rating of Ambient Temperature with Power Applied
from to +85°C to +125°C

Added additional notes in the AC parameter section

Changed the tSC and tHC value for 250 MHz from ns to ns, for 200 MHz from ns to ns, and for 167 MHz from ns to ns.

Modified AC Switching Waveform.

Corrected the typo In the AC Switching Characteristics Table.
Updated the Ordering Information Table.

Page 25 of 25 [+] Feedback

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived CY7C1425AV18-167BZXC Datasheet file may be downloaded here without warranties.

Datasheet ID: CY7C1425AV18-167BZXC 508030