• Compatible With JEDEC Standard AT27C040<br>• Low Power 3.3-volt CMOS Operation
Part | Datasheet |
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AT27LV040A-90TU | AT27LV040A-90TU (pdf) |
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• Fast Read Access Time 90 ns • Dual Voltage Range Operation Low Voltage Power Supply Range, 3.0V to 3.6V or Standard 5V ± 10% Supply Range • Compatible With JEDEC Standard AT27C040 • Low Power 3.3-volt CMOS Operation 20 µA Max Less than 1 µA Typical Standby for VCC = 3.6V 36 mW Max Active at 5 MHz for VCC = 3.6V • JEDEC Standard Packages 32-lead PLCC 32-lead TSOP 32-lead VSOP • High Reliability CMOS Technology 2,000V ESD Protection 200 mA Latchup Immunity • Rapid Programming Algorithm 100 µs/Byte Typical • CMOS and TTL Compatible Inputs and Outputs JEDEC Standard for LVTTL • Integrated Product Identification Code • Industrial Temperature Range • Green Pb/Halide-free Packaging Option 4-Megabit 512K x 8 Low Voltage OTP EPROM AT27LV040A The AT27LV040A is a high-performance, low-power, low-voltage, 4,194,304-bit onetime programmable read-only memory OTP EPROM organized as 512K by 8 bits. It requires only one supply in the range of to 3.6V in normal read mode operation, making it ideal for fast, portable systems using battery power. Atmel’s innovative design techniques provide fast speeds that rival 5V parts while keeping the low power consumption of a 3V supply. At VCC = 3.0V, any byte can be accessed in less than 90 ns. With a typical power dissipation of only 18 mW at 5 MHz and VCC = 3.3V, the AT27LV040A consumes less than one half the power of a standard 5V EPROM. Standby mode supply current is typically less than 1 µA at 3.3V. The AT27LV040A is available in industry-standard JEDEC-approved one-time programmable OTP plastic PLCC, TSOP, and VSOP packages. All devices feature twoline control CE, OE to give designers the flexibility to prevent bus contention. The AT27LV040A operating with VCC at 3.0V produces TTL level outputs that are compatible with standard TTL logic devices operating at VCC = 5.0V. The device is also capable of standard 5-volt operation making it ideally suited for dual supply range systems or card products that are pluggable in both 3-volt and 5-volt hosts. Atmel’s AT27LV040A has additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages. The AT27LV040A programs exactly the same way as a standard 5V AT27C040 and uses the same programming equipment. Pin Configurations Pin Name A0 - A18 O0 - O7 CE OE 32-lead TSOP/VSOP Type 1 Top View Function Addresses Outputs Chip Enable Output Enable 32-lead PLCC Top View A11 1 A9 2 A8 3 A13 4 A14 5 A17 6 A18 7 VCC 8 VPP 9 A16 10 A15 11 A12 12 A7 13 A6 14 A5 15 A4 16 32 OE 31 A10 30 CE 29 O7 28 O6 27 O5 26 O4 25 O3 24 GND 23 02 22 01 21 O0 20 A0 19 A1 18 A2 17 A3 4 A12 3 A15 2 A16 1 VPP 32 VCC 31 A18 30 A17 A7 5 A6 6 A5 7 A4 8 A3 9 A2 10 A1 11 A0 12 O0 13 29 A14 28 A13 27 A8 26 A9 25 A11 24 OE 23 A10 22 CE 21 O7 O1 14 O2 15 GND 16 O3 17 O4 18 O5 19 O6 20 2 AT27LV040A AT27LV040A System Considerations Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array. Block Diagram Absolute Maximum Ratings* Temperature Under Bias.................................. -40°C to +85°C Storage Temperature -65°C to +125°C Voltage on Any Pin with Respect to Ground to +7.0V 1 Voltage on A9 with Respect to Ground to +14.0V 1 VPP Supply Voltage with Respect to Ground to +14.0V 1 *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability Note: Minimum voltage is -0.6V DC which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is VCC + 0.75V DC which may be exceeded if certain precautions are observed consult application notes and which may overshoot to +7.0V for pulses of less than 20 ns. Operating Modes Ordering Information Standard Package ICC mA tACC VCC = 3.6V Active Standby Ordering Code AT27LV040A-90JI AT27LV040A-90TI AT27LV040A-90VI Package 32J 32T 32V 1 Note: Not recommended for new designs. Use Green package option. Green Package Option Pb/Halide-free ICC mA tACC VCC = 3.6V Active Standby Ordering Code AT27LV040A-90JU AT27LV040A-90TU Note The 32-lead VSOP package is not recommended for new designs. Package 32J 32T AT27LV040A Operation Range Industrial -40°C to 85°C Operation Range Industrial -40°C to 85°C Package Type 32-lead, Plastic J-leaded Chip Carrier PLCC 32-lead, Plastic Thin Small Outline Package TSOP 32-lead, Plastic Thin Small Outline Package VSOP Packaging Information 32J PLCC PIN NO. 1 IDENTIFIER e D1 D B1 E2 A2 A1 A 0.51 0.020 MAX 3X COMMON DIMENSIONS Unit of Measure = mm This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum. SYMBOL MIN NOM MAX NOTE Note 2 Note 2 10/04/01 TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131 12 AT27LV040A 32T TSOP PIN 1 AT27LV040A 0º ~ 8º c Pin 1 Identifier SEATING PLANE GAGE PLANE This package conforms to JEDEC reference MO-142, Variation BD. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum. COMMON DIMENSIONS Unit of Measure = mm SYMBOL A A1 A2 D D1 E L L1 b c e |
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