AT27C2048-90PU

AT27C2048-90PU Datasheet

100 µA Maximum Standby 35 mA Maximum Active at 5 MHz • JEDEC Standard Packages 40-lead PDIP 44-lead PLCC 40-lead VSOP • Direct Upgrade from 512-Kbit and 1-Mbit AT27C516 and AT27C1024 EPROMs • 5V ± 10% Power Supply • High Reliability CMOS Technology 2,000V ESD Protection 200 mA Latchup Immunity • Rapid Programming Algorithm 50 µs/Word Typical • CMOS and TTL Compatible Inputs and Outputs • Integrated Product Identification Code • Industrial Temperature Range

Part	Datasheet
AT27C2048-90PU	AT27C2048-90PU (pdf)

Related Parts	Information
AT27C2048-55PU	AT27C2048-55PU

PDF Datasheet Preview
• Fast Read Access Time 55 ns • Low Power CMOS Operation 100 µA Maximum Standby 35 mA Maximum Active at 5 MHz • JEDEC Standard Packages 40-lead PDIP 44-lead PLCC 40-lead VSOP • Direct Upgrade from 512-Kbit and 1-Mbit AT27C516 and AT27C1024 EPROMs • 5V ± 10% Power Supply • High Reliability CMOS Technology 2,000V ESD Protection 200 mA Latchup Immunity • Rapid Programming Algorithm 50 µs/Word Typical • CMOS and TTL Compatible Inputs and Outputs • Integrated Product Identification Code • Industrial Temperature Range 2-Megabit 128K x 16 OTP EPROM AT27C2048 The AT27C2048 is a low-power, high-performance 2,097,152-bit one-time programmable read-only memory OTP EPROM organized 128K by 16 bits. It requires a single 5V power supply in normal read mode operation. Any word can be accessed in less than 55 ns, eliminating the need for speed-reducing WAIT states. The by-16 organization makes this part ideal for high-performance 16 and 32 bit microprocessor systems. In read mode, the AT27C2048 typically consumes 15 mA. Standby mode supply current is typically less than 10 µA. The AT27C2048 is available in industry-standard JEDEC-approved one-time programmable OTP plastic PDIP, PLCC, and VSOP packages. The device features two-line control CE, OE to eliminate bus contention in high-speed systems. With high density 128K word storage capability, the AT27C2048 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media. Atmel’s AT27C2048 has additional features that ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 50 µs/word. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages. Pin Configurations Pin Name Function A0 - A16 Addresses O0 - O15 Outputs Chip Enable Output Enable Program Strobe No Connect Don’t Connect Note Both GND pins must be connected. 40-lead PDIP Top View VPP 1 CE 2 O15 3 O14 4 O13 5 O12 6 O11 7 O10 8 O9 9 O8 10 GND 11 O7 12 O6 13 O5 14 O4 15 O3 16 O2 17 O1 18 O0 19 OE 20 40 VCC 39 PGM 38 A16 37 A15 36 A14 35 A13 34 A12 33 A11 32 A10 31 A9 30 GND 29 A8 28 A7 27 A6 26 A5 25 A4 24 A3 23 A2 22 A1 21 A0 40-lead VSOP Type 1 Top View A9 1 A10 2 A11 3 A12 4 A13 5 A14 6 A15 7 A16 8 PGM 9 VCC 10 VPP 11 CE 12 O15 13 O14 14 O13 15 O12 16 O11 17 O10 18 O9 19 O8 20 40 GND 39 A8 38 A7 37 A6 36 A5 35 A4 34 A3 33 A2 32 A1 31 A0 30 OE 29 O0 28 O1 27 O2 26 O3 25 O4 24 O5 23 O6 22 O7 21 GND 44-lead PLCC Top View 6 O13 5 O14 4 O15 3 CE 2 VPP 1 DC 44 VCC 43 PGM 42 A16 41 A15 40 A14 O12 7 O11 8 O10 9 O9 10 O8 11 GND 12 NC 13 O7 14 O6 15 O5 16 O4 17 39 A13 38 A12 37 A11 36 A10 35 A9 34 GND 33 NC 32 A8 31 A7 30 A6 29 A5 O3 18 O2 19 O1 20 O0 21 OE 22 DC 23 A0 24 A1 25 A2 26 A3 27 A4 28 Note PLCC package pins 1 and 23 are Don’t Connect. 2 AT27C2048 AT27C2048 System Considerations Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array. Ordering Information Standard Package tACC ICC mA Active Standby Ordering Code AT27C2048-55JI AT27C2048-55PI AT27C2048-55VI AT27C2048-90JI AT27C2048-90PI AT27C2048-90VI Note: Not recommended for new designs. Use Green package option. Package 44J 40P6 40V 1 44J 40P6 40V 1 Green Package Pb/Halide-free tACC ICC mA Active Standby Ordering Code AT27C2048-55JU AT27C2048-55PU AT27C2048-90JU AT27C2048-90PU Note The 40-lead VSOP package is not recommended for new designs. Package 44J 40P6 44J 40P6 Operation Range Industrial -40° C to 85° C Industrial -40° C to 85° C Operation Range Industrial -40° C to 85° C Industrial -40° C to 85° C 44J 40P6 40V Package Type 44-lead, Plastic J-leaded Chip Carrier PLCC 40-lead, Wide, Plastic Dual Inline Package PDIP 40-lead, Plastic Thin Small Outline Package VSOP 10 AT27C2048 Packaging Information 44J PLCC AT27C2048 PIN NO. 1 IDENTIFIER e D1 D D2/E2 A2 A1 A 0.51 0.020 MAX 3X COMMON DIMENSIONS Unit of Measure = mm This package conforms to JEDEC reference MS-018, Variation AC. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum. SYMBOL MIN NOM MAX NOTE Note 2 Note 2 D2/E2 TITLE 2325 Orchard Parkway 44J, 44-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131 10/04/01 40P6 PDIP D PIN 1 SEATING PLANE 0º ~ 15º REF This package conforms to JEDEC reference MS-011, Variation AC. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed mm

PDF Datasheet Preview

• Fast Read Access Time 55 ns
• Low Power CMOS Operation
100 µA Maximum Standby 35 mA Maximum Active at 5 MHz
• JEDEC Standard Packages 40-lead PDIP 44-lead PLCC 40-lead VSOP
• Direct Upgrade from 512-Kbit and 1-Mbit AT27C516 and AT27C1024 EPROMs
• 5V ± 10% Power Supply
• High Reliability CMOS Technology 2,000V ESD Protection 200 mA Latchup Immunity
• Rapid Programming Algorithm 50 µs/Word Typical
• CMOS and TTL Compatible Inputs and Outputs
• Integrated Product Identification Code
• Industrial Temperature Range
2-Megabit 128K x 16 OTP EPROM

AT27C2048

The AT27C2048 is a low-power, high-performance 2,097,152-bit one-time programmable read-only memory OTP EPROM organized 128K by 16 bits. It requires a single 5V power supply in normal read mode operation. Any word can be accessed in less than 55 ns, eliminating the need for speed-reducing WAIT states. The by-16 organization makes this part ideal for high-performance 16 and 32 bit microprocessor systems.

In read mode, the AT27C2048 typically consumes 15 mA. Standby mode supply current is typically less than 10 µA.

The AT27C2048 is available in industry-standard JEDEC-approved one-time programmable OTP plastic PDIP, PLCC, and VSOP packages. The device features two-line control CE, OE to eliminate bus contention in high-speed systems.

With high density 128K word storage capability, the AT27C2048 allows firmware to be stored reliably and to be accessed by the system without the delays of mass storage media.

Atmel’s AT27C2048 has additional features that ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guarantees reliable programming. Programming time is typically only 50 µs/word. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry-standard programming equipment to select the proper programming algorithms and voltages.

Pin Configurations

Pin Name

Function

A0 - A16

Addresses

O0 - O15

Outputs

Chip Enable

Output Enable

Program Strobe

No Connect

Don’t Connect

Note Both GND pins must be connected.
40-lead PDIP Top View

VPP 1 CE 2

O15 3 O14 4 O13 5 O12 6 O11 7 O10 8

O9 9 O8 10 GND 11 O7 12 O6 13 O5 14 O4 15 O3 16 O2 17 O1 18 O0 19 OE 20
40 VCC 39 PGM 38 A16 37 A15 36 A14 35 A13 34 A12 33 A11 32 A10 31 A9 30 GND 29 A8 28 A7 27 A6 26 A5 25 A4 24 A3 23 A2 22 A1 21 A0
40-lead VSOP Type 1 Top View

A9 1 A10 2 A11 3 A12 4 A13 5 A14 6 A15 7 A16 8 PGM 9 VCC 10 VPP 11 CE 12 O15 13 O14 14 O13 15 O12 16 O11 17 O10 18 O9 19 O8 20
40 GND 39 A8 38 A7 37 A6 36 A5 35 A4 34 A3 33 A2 32 A1 31 A0 30 OE 29 O0 28 O1 27 O2 26 O3 25 O4 24 O5 23 O6 22 O7 21 GND
44-lead PLCC Top View
6 O13 5 O14 4 O15 3 CE 2 VPP 1 DC 44 VCC 43 PGM 42 A16 41 A15 40 A14

O12 7 O11 8 O10 9

O9 10 O8 11 GND 12 NC 13 O7 14 O6 15 O5 16 O4 17
39 A13 38 A12 37 A11 36 A10 35 A9 34 GND 33 NC 32 A8 31 A7 30 A6 29 A5

O3 18 O2 19 O1 20 O0 21 OE 22 DC 23 A0 24 A1 25 A2 26 A3 27 A4 28

Note PLCC package pins 1 and 23 are Don’t Connect.
2 AT27C2048

AT27C2048

System Considerations

Switching between active and standby conditions via the Chip Enable pin may produce transient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the VCC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array.
Ordering Information

Standard Package
tACC

ICC mA

Active

Standby
Ordering Code

AT27C2048-55JI AT27C2048-55PI AT27C2048-55VI

AT27C2048-90JI AT27C2048-90PI AT27C2048-90VI

Note:

Not recommended for new designs. Use Green package option.

Package
44J 40P6 40V 1
44J 40P6 40V 1

Green Package Pb/Halide-free
tACC

ICC mA

Active

Standby
Ordering Code

AT27C2048-55JU

AT27C2048-55PU

AT27C2048-90JU

AT27C2048-90PU

Note The 40-lead VSOP package is not recommended for new designs.

Package
44J 40P6
44J 40P6

Operation Range Industrial
-40° C to 85° C Industrial
-40° C to 85° C

Operation Range Industrial
-40° C to 85° C Industrial
-40° C to 85° C
44J 40P6 40V

Package Type 44-lead, Plastic J-leaded Chip Carrier PLCC 40-lead, Wide, Plastic Dual Inline Package PDIP 40-lead, Plastic Thin Small Outline Package VSOP
10 AT27C2048

Packaging Information
44J PLCC

AT27C2048

PIN NO. 1 IDENTIFIER
e D1 D

D2/E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-018, Variation AC. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2

D2/E2

TITLE 2325 Orchard Parkway 44J, 44-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
10/04/01
40P6 PDIP

D PIN 1

SEATING PLANE
0º ~ 15º REF

This package conforms to JEDEC reference MS-011, Variation AC. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed mm

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived AT27C2048-90PU Datasheet file may be downloaded here without warranties.

Datasheet ID: AT27C2048-90PU 518939