AT24C1024-10PI-2.7

AT24C1024-10PI-2.7 Datasheet

The AT24C1024 provides 1,048,576 bits of serial electrically erasable and programmable read only memory EEPROM organized as 131,072 words of 8 bits each. The device’s cascadable feature allows up to 2 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where lowpower and low-voltage operation are essential. The devices are available in spacesaving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead Leadless Array LAP and 8-ball dBGA packages. In addition, the entire family is available in 2.7V 2.7V to 5.5V versions.

Part	Datasheet
AT24C1024-10PI-2.7	AT24C1024-10PI-2.7 (pdf)

Related Parts	Information
AT24C1024W-10SI-2.7	AT24C1024W-10SI-2.7
AT24C1024C1-10CI-2.7	AT24C1024C1-10CI-2.7
AT24C1024-10CI-2.7	AT24C1024-10CI-2.7
AT24C1024W-10SI-2.7-T	AT24C1024W-10SI-2.7-T

PDF Datasheet Preview
• Low-voltage Operation VCC = 2.7V to 5.5V • Internally Organized 131,072 x 8 • 2-wire Serial Interface • Schmitt Triggers, Filtered Inputs for Noise Suppression • Bi-directional Data Transfer Protocol • 400 kHz 2.7V and 1 MHz 5V Clock Rate • Write Protect Pin for Hardware and Software Data Protection • 256-byte Page Write Mode Partial Page Writes Allowed • Random and Sequential Read Modes • Self-timed Write Cycle 5 ms Typical • High Reliability Endurance 100,000 Write Cycles/Page Data Retention 40 Years • 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead LAP and 8-ball dBGATM Packages 2-wire Serial EEPROM 1M 131,072 x 8 The AT24C1024 provides 1,048,576 bits of serial electrically erasable and programmable read only memory EEPROM organized as 131,072 words of 8 bits each. The device’s cascadable feature allows up to 2 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where lowpower and low-voltage operation are essential. The devices are available in spacesaving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead Leadless Array LAP and 8-ball dBGA packages. In addition, the entire family is available in 2.7V 2.7V to 5.5V versions. AT24C1024 Pin Configurations Pin Name A1 Function Address Input SDA SCL WP NC Serial Data Serial Clock Input Write Protect No Connect 8-lead SOIC NC 1 A1 2 NC 3 GND 4 8 VCC 7 WP 6 SCL 5 SDA 8-lead PDIP NC 1 A1 2 NC 3 GND 4 8 VCC 7 WP 6 SCL 5 SDA 8-lead Leadless Array VCC 8 WP 7 SCL 6 SDA 5 1 NC 2 A1 3 NC 4 GND Bottom View 8-ball dBGA VCC 8 WP 7 SCL 6 SDA 5 1 NC 2 A1 3 NC 4 GND Bottom View Absolute Maximum Ratings* Operating -55°C to +125°C Storage Temperature -65°C to +150°C Voltage on Any Pin with Respect to Ground to +7.0V Maximum Operating Voltage 6.25V DC Output mA Block Diagram *NOTICE: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 AT24C1024 AT24C1024 Pin Description Memory Organization SERIAL CLOCK SCL The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA SDA The SDA pin is bi-directional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open-collector devices. DEVICE/PAGE ADDRESSES A1 The A1 pin is a device address input that can be hardwired or left not connected for hardware compatibility with AT24C128/256/512. When the A1 pin is hardwired, as many as two 1024K devices may be addressed on a single bus system device addressing is discussed in detail under the Device Addressing section . When the pin is not hardwired, the default A1 is zero. WRITE PROTECT WP The hardware Write Protect pin is useful for protecting the entire contents of the memory from inadvertent write operations. The write-protect input, when tied to GND, allows normal write operations. When WP is tied high to VCC, all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP to VCC prior to a write operation creates a software write-protect function. AT24C1024, 1024K SERIAL EEPROM The 1024K is internally organized as 512 pages of 256 bytes each. Random word addressing requires a 17-bit data word address. Pin Capacitance 1 Ordering Information Ordering Code Package Operation Range AT24C1024-10CI-2.7 AT24C1024C1-10CI-2.7 AT24C1024-10PI-2.7 AT24C1024W-10SI-2.7 AT24C1024-10UI-2.7 8CN3 8CN1 8P3 8S2 8U8 Industrial -40°C to 85°C Note For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables. 8CN3 8CN1 8P3 8S2 8U8 Package Type 8-lead, Wide, Leadless Array Package LAP 8-lead, Wide, Leadless Array Package LAP 8-lead, Wide, Plastic Dual In-line Package PDIP 8-lead, Wide, Plastic Gull Wing Small Outline Package EIAJ SOIC 8-ball, die Ball Grid Array Package dBGA Options Low Voltage 2.7V to 5.5V Packaging Information 8CN3 LAP Marked Pin1 Indentifier mm TYP Top View Bottom View Side View Pin1 Corner COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE Note Metal Pad Dimensions. 2325 Orchard Parkway R San Jose, CA 95131 8CN3, 8-lead, 6 x 5 x mm Body , Lead Pitch mm, Leadless Array Package LAP 11/14/01 8CN3 14 AT24C1024 8CN1 LAP AT24C1024 Marked Pin1 Indentifier mm TYP Top View Bottom View Note Metal Pad Dimensions. Side View Pin1 Corner COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE 2325 Orchard Parkway R San Jose, CA 95131 8CN1, 8-lead 8 x 5 x mm Body , Lead Pitch mm, Leadless Array Package LAP 11/13/01 8CN1

PDF Datasheet Preview

• Low-voltage Operation

VCC = 2.7V to 5.5V
• Internally Organized 131,072 x 8
• 2-wire Serial Interface
• Schmitt Triggers, Filtered Inputs for Noise Suppression
• Bi-directional Data Transfer Protocol
• 400 kHz 2.7V and 1 MHz 5V Clock Rate
• Write Protect Pin for Hardware and Software Data Protection
• 256-byte Page Write Mode Partial Page Writes Allowed
• Random and Sequential Read Modes
• Self-timed Write Cycle 5 ms Typical
• High Reliability

Endurance 100,000 Write Cycles/Page

Data Retention 40 Years
• 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead LAP and 8-ball dBGATM Packages
2-wire Serial EEPROM
1M 131,072 x 8

The AT24C1024 provides 1,048,576 bits of serial electrically erasable and programmable read only memory EEPROM organized as 131,072 words of 8 bits each. The device’s cascadable feature allows up to 2 devices to share a common 2-wire bus. The device is optimized for use in many industrial and commercial applications where lowpower and low-voltage operation are essential. The devices are available in spacesaving 8-lead PDIP, 8-lead EIAJ SOIC, 8-lead Leadless Array LAP and 8-ball dBGA packages. In addition, the entire family is available in 2.7V 2.7V to 5.5V versions.

AT24C1024

Pin Configurations

Pin Name A1

Function Address Input

SDA SCL WP NC

Serial Data Serial Clock Input Write Protect No Connect
8-lead SOIC

NC 1 A1 2 NC 3 GND 4
8 VCC 7 WP 6 SCL 5 SDA
8-lead PDIP

NC 1 A1 2 NC 3 GND 4
8 VCC 7 WP 6 SCL 5 SDA
8-lead Leadless Array

VCC 8 WP 7 SCL 6 SDA 5
1 NC 2 A1 3 NC 4 GND

Bottom View 8-ball dBGA

VCC 8 WP 7 SCL 6 SDA 5
1 NC 2 A1 3 NC 4 GND

Bottom View

Absolute Maximum Ratings*

Operating -55°C to +125°C Storage Temperature -65°C to +150°C Voltage on Any Pin with Respect to Ground to +7.0V Maximum Operating Voltage 6.25V DC Output mA

Block Diagram
*NOTICE:

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
2 AT24C1024

AT24C1024

Pin Description

Memory Organization

SERIAL CLOCK SCL The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device.

SERIAL DATA SDA The SDA pin is bi-directional for serial data transfer. This pin is opendrain driven and may be wire-ORed with any number of other open-drain or open-collector devices.

DEVICE/PAGE ADDRESSES A1 The A1 pin is a device address input that can be hardwired or left not connected for hardware compatibility with AT24C128/256/512. When the A1 pin is hardwired, as many as two 1024K devices may be addressed on a single bus system device addressing is discussed in detail under the Device Addressing section . When the pin is not hardwired, the default A1 is zero.

WRITE PROTECT WP The hardware Write Protect pin is useful for protecting the entire contents of the memory from inadvertent write operations. The write-protect input, when tied to GND, allows normal write operations. When WP is tied high to VCC, all write operations to the memory are inhibited. If left unconnected, WP is internally pulled down to GND. Switching WP to VCC prior to a write operation creates a software write-protect function.

AT24C1024, 1024K SERIAL EEPROM The 1024K is internally organized as 512 pages of 256 bytes each. Random word addressing requires a 17-bit data word address.

Pin Capacitance 1
Ordering Information
Ordering Code

Package

Operation Range

AT24C1024-10CI-2.7 AT24C1024C1-10CI-2.7 AT24C1024-10PI-2.7 AT24C1024W-10SI-2.7 AT24C1024-10UI-2.7
8CN3 8CN1 8P3 8S2 8U8

Industrial -40°C to 85°C

Note For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC Characteristics tables.
8CN3 8CN1 8P3 8S2 8U8

Package Type 8-lead, Wide, Leadless Array Package LAP 8-lead, Wide, Leadless Array Package LAP 8-lead, Wide, Plastic Dual In-line Package PDIP 8-lead, Wide, Plastic Gull Wing Small Outline Package EIAJ SOIC 8-ball, die Ball Grid Array Package dBGA

Options Low Voltage 2.7V to 5.5V

Packaging Information
8CN3 LAP

Marked Pin1 Indentifier
mm TYP

Top View

Bottom View

Side View

Pin1 Corner

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL MIN NOM MAX NOTE

Note Metal Pad Dimensions.
2325 Orchard Parkway R San Jose, CA 95131
8CN3, 8-lead, 6 x 5 x mm Body , Lead Pitch mm, Leadless Array Package LAP
11/14/01
8CN3
14 AT24C1024
8CN1 LAP

AT24C1024

Marked Pin1 Indentifier
mm TYP

Top View

Bottom View

Note Metal Pad Dimensions.

Side View

Pin1 Corner

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL MIN NOM MAX NOTE
2325 Orchard Parkway R San Jose, CA 95131
8CN1, 8-lead 8 x 5 x mm Body , Lead Pitch mm, Leadless Array Package LAP
11/13/01
8CN1

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Datasheet ID: AT24C1024-10PI-2.7 518879