AT17LV002-10BJI

AT17LV002-10BJI Datasheet

Devices, Lucent FPGAs, Xilinx XC3000 , XC4000 , XC5200 , Virtex FPGAs • Cascadable Read Back to Support Additional Configurators or Higher-density Arrays • Low-power CMOS EEPROM Process • Programmable Reset Polarity • Available in 6 mm x 6 mm x 1 mm 8-lead LAP Pin-compatible with 8-lead SOIC/VOIC Packages , 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages Pin-compatible Across Product Family • Emulation of Atmel’s AT24CXXX Serial EEPROMs • Available in 3.3V ± 10% LV and 5V ± 5% C Versions • System-friendly READY Pin • Low-power Standby Mode • Replacement for AT17C/LV020

Part	Datasheet
AT17LV002-10BJI	AT17LV002-10BJI (pdf)

Related Parts	Information
AT17C002-10CI	AT17C002-10CI
AT17C002-10JI	AT17C002-10JI
AT17LV002-10BJC	AT17LV002-10BJC
AT17C002-10JC	AT17C002-10JC
AT17LV002-10TQI	AT17LV002-10TQI
AT17LV002-10TQC	AT17LV002-10TQC
AT17C002-10CC	AT17C002-10CC

PDF Datasheet Preview
• EE Reprogrammable 2,097,152 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays FPGAs • In-System Programmable via 2-wire Bus • Simple Interface to SRAM FPGAs • Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera APEX Devices, Lucent FPGAs, Xilinx XC3000 , XC4000 , XC5200 , Virtex FPGAs • Cascadable Read Back to Support Additional Configurators or Higher-density Arrays • Low-power CMOS EEPROM Process • Programmable Reset Polarity • Available in 6 mm x 6 mm x 1 mm 8-lead LAP Pin-compatible with 8-lead SOIC/VOIC Packages , 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages Pin-compatible Across Product Family • Emulation of Atmel’s AT24CXXX Serial EEPROMs • Available in 3.3V ± 10% LV and 5V ± 5% C Versions • System-friendly READY Pin • Low-power Standby Mode • Replacement for AT17C/LV020 The AT17C002 and AT17LV002 high-density AT17 Series FPGA Configuration EEPROMs Configurators provide an easy-to-use, cost-effective configuration memory for programming Field Programmable Gate Arrays. The AT17 Series is packaged in the popular 8-lead LAP, 20-lead PLCC, 44-lead PLCC and the 44-lead TQFP. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes. These devices support a write protection mode and a systemfriendly READY pin, which signifies a “good” power level to the FPGA and can be used to ensure reliable system power-up. The AT17 Series Configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming System and Atmel’s ATDH2225 ISP Cable. FPGA Configuration EEPROM Memory 2-megabit AT17C002 AT17LV002 Pin Configuration 8-lead LAP DATA 1 CLK 2 RESET/OE 3 CE 4 8 VCC 7 SER_EN 6 CEO A2 5 GND 44-lead PLCC 20-lead PLCC 3 NC 2 DATA 1 NC 20 VCC 19 NC CLK 4 WP1 5 RESET/OE 6 NC 7 CE 8 18 NC 17 SER_EN 16 NC 15 READY 14 CEO A2 NC 9 GND 10 NC 11 NC 12 NC 13 44-lead TQFP 44 NC 43 CLK 42 NC 41 NC 40 DATA 39 NC 38 VCC 37 NC 36 NC 35 SER_EN 34 NC 6 NC 5 CLK 4 NC 3 NC 2 DATA 1 NC 44 VCC 43 NC 42 NC 41 SER_EN 40 NC WP1 7 NC 8 NC 9 NC 10 NC 11 NC 12 NC 13 NC 14 NC 15 NC 16 NC 17 39 NC 38 NC 37 NC 36 NC 35 NC 34 NC 33 NC 32 NC 31 NC 30 NC 29 READY NC 1 NC 2 NC 3 NC 4 NC 5 NC 6 WP1 7 NC 8 NC 9 NC 10 NC 11 33 NC 32 NC 31 NC 30 NC 29 NC 28 NC 27 NC 26 NC 25 NC 24 NC 23 READY NC 18 RESET/OE 19 NC 20 CE 21 NC 22 NC 23 GND 24 NC 25 NC 26 CEO A2 27 NC 28 NC 12 RESET/OE 13 NC 14 CE 15 NC 16 NC 17 GND 18 NC 19 NC 20 CEO A2 21 NC 22 2 AT17C/LV002 Block Diagram SER_EN WP1 OSC CONTROL POWER ON RESET PROGRAMMING MODE LOGIC ROW ADDRESS COUNTER BIT COUNTER AT17C/LV002 Ordering Information 5V Devices Memory Size 2-Mbit Ordering Code AT17C002-10CC AT17C002-10JC AT17C002-10TQC AT17C002-10BJC AT17C002-10CI AT17C002-10JI AT17C002-10TQI AT17C002-10BJI Ordering Information 3.3V Devices Memory Size Ordering Code 2-Mbit AT17LV002-10CC AT17LV002-10JC AT17LV002-10TQC AT17LV002-10BJC AT17LV002-10CI AT17LV002-10JI AT17LV002-10TQI AT17LV002-10BJI Package 8CN4 20J 44A 44J 8CN4 20J 44A 44J Package 8CN4 20J 44A 44J 8CN4 20J 44A 44J Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C Operation Range Commercial 0°C to 70°C Industrial -40°C to 85°C 8CN4 20J 44A 44J Package Type 8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package LAP Pin-compatible with 8-lead SOIC/VOIC Packages 20-lead, Plastic J-leaded Chip Carrier PLCC 44-lead, Thin mm Plastic Quad Flat Package Carrier TQFP 44-lead, Plastic J-leaded Chip Carrier PLCC 14 AT17C/LV002 Packaging Information 8CN4 LAP AT17C/LV002 Marked Pin1 Indentifier mm TYP Top View Bottom View Note Metal Pad Dimensions. Side View Pin1 Corner COMMON DIMENSIONS Unit of Measure = mm SYMBOL MIN NOM MAX NOTE TITLE 1150 E.Cheyenne Mtn Blvd. 8CN4, 8-lead 6 x 6 x mm Body , Lead Pitch mm, R Colorado Springs, CO 80906 Leadless Array Package LAP 11/14/01 8CN4 20J PLCC PIN NO. 1 IDENTIFIER e E1 E D2/E2 B1 A2 A1 A 0.51 0.020 MAX 3X COMMON DIMENSIONS Unit of Measure = mm This package conforms to JEDEC reference MS-018, Variation AA. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum. SYMBOL MIN NOM MAX NOTE Note 2 Note 2 D2/E2

PDF Datasheet Preview

• EE Reprogrammable 2,097,152 x 1-bit Serial Memories Designed to Store Configuration Programs for Field Programmable Gate Arrays FPGAs
• In-System Programmable via 2-wire Bus
• Simple Interface to SRAM FPGAs
• Compatible with Atmel AT6000, AT40K and AT94K Devices, Altera APEX

Devices, Lucent FPGAs, Xilinx XC3000 , XC4000 , XC5200 , Virtex FPGAs
• Cascadable Read Back to Support Additional Configurators or Higher-density Arrays
• Low-power CMOS EEPROM Process
• Programmable Reset Polarity
• Available in 6 mm x 6 mm x 1 mm 8-lead LAP Pin-compatible with 8-lead SOIC/VOIC Packages , 20-lead PLCC, 44-lead PLCC and 44-lead TQFP Packages Pin-compatible Across Product Family
• Emulation of Atmel’s AT24CXXX Serial EEPROMs
• Available in 3.3V ± 10% LV and 5V ± 5% C Versions
• System-friendly READY Pin
• Low-power Standby Mode
• Replacement for AT17C/LV020

The AT17C002 and AT17LV002 high-density AT17 Series FPGA Configuration EEPROMs Configurators provide an easy-to-use, cost-effective configuration memory for programming Field Programmable Gate Arrays. The AT17 Series is packaged in the popular 8-lead LAP, 20-lead PLCC, 44-lead PLCC and the 44-lead TQFP. The AT17 Series family uses a simple serial-access procedure to configure one or more FPGA devices. The user can select the polarity of the reset function by programming four EEPROM bytes. These devices support a write protection mode and a systemfriendly READY pin, which signifies a “good” power level to the FPGA and can be used to ensure reliable system power-up.

The AT17 Series Configurators can be programmed with industry-standard programmers, Atmel’s ATDH2200E Programming System and Atmel’s ATDH2225 ISP Cable.

FPGA Configuration EEPROM Memory
2-megabit

AT17C002 AT17LV002

Pin Configuration
8-lead LAP

DATA 1 CLK 2

RESET/OE 3 CE 4
8 VCC 7 SER_EN 6 CEO A2 5 GND
44-lead PLCC
20-lead PLCC
3 NC 2 DATA 1 NC 20 VCC 19 NC

CLK 4 WP1 5 RESET/OE 6

NC 7 CE 8
18 NC 17 SER_EN 16 NC 15 READY 14 CEO A2

NC 9 GND 10

NC 11 NC 12 NC 13
44-lead TQFP
44 NC 43 CLK 42 NC 41 NC 40 DATA 39 NC 38 VCC 37 NC 36 NC 35 SER_EN 34 NC
6 NC 5 CLK 4 NC 3 NC 2 DATA 1 NC 44 VCC 43 NC 42 NC 41 SER_EN 40 NC

WP1 7 NC 8 NC 9 NC 10 NC 11 NC 12 NC 13 NC 14 NC 15 NC 16 NC 17
39 NC 38 NC 37 NC 36 NC 35 NC 34 NC 33 NC 32 NC 31 NC 30 NC 29 READY

NC 1 NC 2 NC 3 NC 4 NC 5 NC 6 WP1 7 NC 8 NC 9 NC 10 NC 11
33 NC 32 NC 31 NC 30 NC 29 NC 28 NC 27 NC 26 NC 25 NC 24 NC 23 READY

NC 18 RESET/OE 19

NC 20 CE 21 NC 22 NC 23 GND 24 NC 25 NC 26 CEO A2 27 NC 28

NC 12 RESET/OE 13

NC 14 CE 15 NC 16 NC 17 GND 18 NC 19 NC 20 CEO A2 21 NC 22
2 AT17C/LV002

Block Diagram

SER_EN WP1

OSC CONTROL

POWER ON RESET

PROGRAMMING MODE LOGIC

ROW ADDRESS COUNTER

BIT COUNTER

AT17C/LV002
Ordering Information 5V Devices

Memory Size 2-Mbit
Ordering Code

AT17C002-10CC AT17C002-10JC AT17C002-10TQC AT17C002-10BJC

AT17C002-10CI AT17C002-10JI AT17C002-10TQI AT17C002-10BJI
Ordering Information 3.3V Devices

Memory Size
Ordering Code
2-Mbit

AT17LV002-10CC AT17LV002-10JC AT17LV002-10TQC AT17LV002-10BJC

AT17LV002-10CI AT17LV002-10JI AT17LV002-10TQI AT17LV002-10BJI

Package 8CN4 20J 44A 44J 8CN4 20J 44A 44J

Package 8CN4 20J 44A 44J 8CN4 20J 44A 44J

Operation Range Commercial 0°C to 70°C

Industrial -40°C to 85°C

Operation Range Commercial 0°C to 70°C

Industrial -40°C to 85°C
8CN4 20J 44A 44J

Package Type 8-lead, 6 mm x 6 mm x 1 mm, Leadless Array Package LAP Pin-compatible with 8-lead SOIC/VOIC Packages 20-lead, Plastic J-leaded Chip Carrier PLCC 44-lead, Thin mm Plastic Quad Flat Package Carrier TQFP 44-lead, Plastic J-leaded Chip Carrier PLCC
14 AT17C/LV002

Packaging Information
8CN4 LAP

AT17C/LV002

Marked Pin1 Indentifier
mm TYP

Top View

Bottom View

Note Metal Pad Dimensions.

Side View

Pin1 Corner

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL MIN NOM MAX NOTE

TITLE 1150 E.Cheyenne Mtn Blvd. 8CN4, 8-lead 6 x 6 x mm Body , Lead Pitch mm, R Colorado Springs, CO 80906 Leadless Array Package LAP
11/14/01
8CN4
20J PLCC

PIN NO. 1 IDENTIFIER
e E1 E

D2/E2 B1

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-018, Variation AA. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2

D2/E2

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Datasheet ID: AT17LV002-10BJI 518850