AT49LH00B4-33JX

AT49LH00B4-33JX Datasheet

The AT49LH00B4 is a Flash memory device designed for use in PC and notebook BIOS applications. The device complies with version of Intel’s LPC Interface Specification, providing support for both FWH and LPC memory read and write cycles. The device can also automatically detect the memory cycle type to allow the AT49LH00B4 to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets.

Part	Datasheet
AT49LH00B4-33JX	AT49LH00B4-33JX (pdf)

Related Parts	Information
AT49LH00B4-33JC-T	AT49LH00B4-33JC-T
AT49LH00B4-33JX-T	AT49LH00B4-33JX-T
AT49LH00B4-33JC	AT49LH00B4-33JC

PDF Datasheet Preview
• Auto-detection of FWH and LPC Memory Cycles Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets Can Be Used as LPC Flash for Non-Intel Chipsets • Top Boot with Bottom Partitioned Memory Array for Efficient Vital Data Storage 64-Kbyte Top Boot Sector, Six 64-Kbyte Sectors, One 32-Kbyte Sector, One 16-Kbyte Sector, Two 8-Kbyte Sectors Or Memory Array Can Be Divided Into Eight Uniform 64-Kbyte Sectors for Erasing • Two Configurable Interfaces FWH/LPC Interface for In-System Operation Address/Address Multiplexed A/A Mux Interface for Programming during Manufacturing • FWH/LPC Interface Operates with the 33 MHz PCI Bus Clock 5-signal Communication Interface Supporting Byte Reads and Writes Two Hardware Write Protect Pins TBL for Top Boot Sector and WP for All Other Sectors Five General-purpose Input GPI Pins for System Design Flexibility Identification ID Pins for Multiple Device Selection Sector Locking Registers for Individual Sector Read and Write Protection • A/A Mux Interface 11-pin Multiplexed Address and 8-pin Data Interface Facilitates Fast In-System or Out-of-System Programming • Single Voltage Operation 3.0V to 3.6V Supply Voltage for Read and Write Operations • Industry-Standard Package Options 32-lead PLCC 40-lead TSOP • Green Pb/Halide-free Packaging Option The AT49LH00B4 is a Flash memory device designed for use in PC and notebook BIOS applications. The device complies with version of Intel’s LPC Interface Specification, providing support for both FWH and LPC memory read and write cycles. The device can also automatically detect the memory cycle type to allow the AT49LH00B4 to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets. The sectoring of the AT49LH00B4’s memory array has been optimized to meet the needs of today’s BIOS applications. By optimizing the size of the sectors, the BIOS code memory space can be used more efficiently. Because certain BIOS code modules must reside in their own sectors by themselves, the wasted and unused memory space that occurred with previous generation BIOS Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional BIOS routines to be developed and added while still maintaining the same overall device density. 4-megabit Top Boot, Bottom Partitioned Firmware Hub and Low-Pin Count Flash Memory AT49LH00B4 Not Recommended for New Design Contact Atmel to discuss the latest design in trends and options The memory array of the AT49LH00B4 can be sectored in two ways simply by using two different erase commands. Using one erase command allows the device to contain a total of eleven sectors comprised of a 64-Kbyte boot sector, six 64-Kbyte sectors, a 32-Kbyte sector, a 16-Kbyte sector, and two 8-Kbyte sectors. The 64-Kbyte boot sector is located at the top uppermost of the device’s memory address space and can be hardware write protected by using the TBL pin. Alternatively, by using a different erase command, the memory array can be arranged into eight even erase sectors of 64-Kbyte each. The AT49LH00B4 supports two hardware interfaces The FWH/LPC interface for In-System operations and the A/A Mux interface for programming during manufacturing. The Interface Configuration IC pin of the device provides the control between these two interfaces. An internal Command User Interface CUI serves as the control center between the device interfaces and the internal operation of the nonvolatile memory. A valid command sequence written to the CUI initiates device automation. Specifically designed for use in 3-volt systems, the AT49LH00B4 supports read, program, and erase operations with a supply voltage range of 3.0V to 3.6V. No separate voltage is required for programming and erasing. The AT49LH00B4 utilizes fixed program and erase times, independent of the number of program and erase cycles that have occurred. Therefore, the system does not need to be calibrated or correlated to the cumulative number of program and erase cycles. 2 AT49LH00B4 Pin Configurations 32PLCC AT49LH00B4 4 GPI2 [A8] 3 GPI3 [A9] 2 RST [RST] 1 NC 32 VCC 31 CLK [R/C] 30 GPI4 [A10] [A7] GPI1 5 [A6] GPI0 6 [A5] WP 7 [A4] TBL 8 [A3] ID3 9 [A2] ID2 10 [A1] ID1 11 [A0] ID0 12 [I/O0] FWH0/LAD0 13 29 IC [IC] 28 GND 27 NC 26 NC 25 VCC 24 INIT [OE] 23 FWH4/LFRAME [WE] 22 RES [RDY/BSY] 21 RES [I/O7] [I/O1] FWH1/LAD1 14 [I/O2] FWH2/LAD2 15 GND 16 [I/O3] FWH3/LAD3 17 [I/O4] RES 18 [I/O5] RES 19 [I/O6] RES 20 40TSOP NC 1 [IC] IC 2 NC 3 NC 4 NC 5 NC 6 [A10] GPI4 7 NC 8 [R/C] CLK 9 VCC 10 NC 11 [RST] RST 12 NC 13 NC 14 [A9] GPI3 15 [A8] GPI2 16 [A7] GPI1 17 [A6] GPI0 18 [A5] WP 19 [A4] TBL 20 Note [ ] Designates A/A Mux Interface. 40 GND 39 VCC 38 FWH4/LFRAME [WE] 37 INIT [OE] 36 RES [RDY/BSY] 35 RES [I/O7] 34 RES [I/O6] 33 RES [I/O5] 32 RES [I/O4] 31 VCC 30 GND 29 GND 28 FWH3/LAD3 [I/O3] 27 FWH2/LAD2 [I/O2] 26 FWH1/LAD1 [I/O1] 25 FWH0/LAD0 [I/O0] 24 ID0 [A0] 23 ID1 [A1] 22 ID2 [A2] 21 ID3 [A3] Block Diagram TBL WP INIT CLK FWH4/LFRAME FWH/LAD[3:0] ID[3:0] GPI[4:0] IC RST R/C A[10:0] I/O[7:0] Ordering Information Standard Package ICC mA Active Standby Ordering Code AT49LH00B4-33JC AT49LH00B4-33TC Green Package Option Pb/Halide-free ICC mA Active Standby Ordering Code AT49LH00B4-33JX Package 32J 40T Operation Range Extended Commercial 0° to 85°C Package 32J Operation Range Extended Commercial 0° to 85°C Package Type 32-lead, Plastic J-leaded Chip Carrier Package PLCC 40-lead, Thin Small Outline Package TSOP 38 AT49LH00B4 Packaging Information 32J PLCC AT49LH00B4 PIN NO. 1 IDENTIFIER e D1 D B1 E2 A2 A1 A 0.51 0.020 MAX 3X COMMON DIMENSIONS Unit of Measure = mm This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum. SYMBOL MIN NOM MAX NOTE Note 2 Note 2 10/04/01 TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131 40T TSOP PIN 1 0º ~ 8º c Pin 1 Identifier SEATING PLANE GAGE PLANE This package conforms to JEDEC reference MO-142, Variation CD. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum. COMMON DIMENSIONS Unit of Measure = mm SYMBOL A A1 A2 D D1 E L L1 b c e MIN NOM MAX BASIC BASIC

PDF Datasheet Preview

• Auto-detection of FWH and LPC Memory Cycles Can Be Used as FWH for Intel 8xx, E7xxx, and E8xxx Series Chipsets Can Be Used as LPC Flash for Non-Intel Chipsets
• Top Boot with Bottom Partitioned Memory Array for Efficient Vital Data Storage 64-Kbyte Top Boot Sector, Six 64-Kbyte Sectors, One 32-Kbyte Sector, One 16-Kbyte Sector, Two 8-Kbyte Sectors Or Memory Array Can Be Divided Into Eight Uniform 64-Kbyte Sectors for Erasing
• Two Configurable Interfaces FWH/LPC Interface for In-System Operation Address/Address Multiplexed A/A Mux Interface for Programming during Manufacturing
• FWH/LPC Interface Operates with the 33 MHz PCI Bus Clock 5-signal Communication Interface Supporting Byte Reads and Writes Two Hardware Write Protect Pins TBL for Top Boot Sector and WP for All Other Sectors Five General-purpose Input GPI Pins for System Design Flexibility Identification ID Pins for Multiple Device Selection Sector Locking Registers for Individual Sector Read and Write Protection
• A/A Mux Interface 11-pin Multiplexed Address and 8-pin Data Interface Facilitates Fast In-System or Out-of-System Programming
• Single Voltage Operation 3.0V to 3.6V Supply Voltage for Read and Write Operations
• Industry-Standard Package Options 32-lead PLCC 40-lead TSOP
• Green Pb/Halide-free Packaging Option

The AT49LH00B4 is a Flash memory device designed for use in PC and notebook BIOS applications. The device complies with version of Intel’s LPC Interface Specification, providing support for both FWH and LPC memory read and write cycles. The device can also automatically detect the memory cycle type to allow the AT49LH00B4 to be used as a FWH with Intel chipsets or as an LPC Flash with non-Intel chipsets.

The sectoring of the AT49LH00B4’s memory array has been optimized to meet the needs of today’s BIOS applications. By optimizing the size of the sectors, the BIOS code memory space can be used more efficiently. Because certain BIOS code modules must reside in their own sectors by themselves, the wasted and unused memory space that occurred with previous generation BIOS Flash memory devices can be greatly reduced. This increased memory space efficiency allows additional BIOS routines to be developed and added while still maintaining the same overall device density.
4-megabit Top Boot, Bottom Partitioned Firmware Hub and Low-Pin Count Flash Memory

AT49LH00B4

Not Recommended for New Design

Contact Atmel to discuss the latest design in trends and options

The memory array of the AT49LH00B4 can be sectored in two ways simply by using two different erase commands. Using one erase command allows the device to contain a total of eleven sectors comprised of a 64-Kbyte boot sector, six 64-Kbyte sectors, a 32-Kbyte sector, a 16-Kbyte sector, and two 8-Kbyte sectors. The 64-Kbyte boot sector is located at the top uppermost of the device’s memory address space and can be hardware write protected by using the TBL pin. Alternatively, by using a different erase command, the memory array can be arranged into eight even erase sectors of 64-Kbyte each.

The AT49LH00B4 supports two hardware interfaces The FWH/LPC interface for In-System operations and the A/A Mux interface for programming during manufacturing. The Interface Configuration IC pin of the device provides the control between these two interfaces. An internal Command User Interface CUI serves as the control center between the device interfaces and the internal operation of the nonvolatile memory. A valid command sequence written to the CUI initiates device automation.

Specifically designed for use in 3-volt systems, the AT49LH00B4 supports read, program, and erase operations with a supply voltage range of 3.0V to 3.6V. No separate voltage is required for programming and erasing.

The AT49LH00B4 utilizes fixed program and erase times, independent of the number of program and erase cycles that have occurred. Therefore, the system does not need to be calibrated or correlated to the cumulative number of program and erase cycles.
2 AT49LH00B4

Pin Configurations
32PLCC

AT49LH00B4
4 GPI2 [A8] 3 GPI3 [A9] 2 RST [RST] 1 NC 32 VCC 31 CLK [R/C] 30 GPI4 [A10]
[A7] GPI1 5 [A6] GPI0 6
[A5] WP 7 [A4] TBL 8 [A3] ID3 9 [A2] ID2 10 [A1] ID1 11 [A0] ID0 12 [I/O0] FWH0/LAD0 13
29 IC [IC] 28 GND 27 NC 26 NC 25 VCC 24 INIT [OE] 23 FWH4/LFRAME [WE] 22 RES [RDY/BSY] 21 RES [I/O7]
[I/O1] FWH1/LAD1 14 [I/O2] FWH2/LAD2 15

GND 16 [I/O3] FWH3/LAD3 17
[I/O4] RES 18 [I/O5] RES 19 [I/O6] RES 20
40TSOP

NC 1 [IC] IC 2

NC 3 NC 4 NC 5 NC 6 [A10] GPI4 7 NC 8 [R/C] CLK 9 VCC 10 NC 11 [RST] RST 12 NC 13 NC 14 [A9] GPI3 15 [A8] GPI2 16 [A7] GPI1 17 [A6] GPI0 18 [A5] WP 19 [A4] TBL 20

Note [ ] Designates A/A Mux Interface.
40 GND 39 VCC 38 FWH4/LFRAME [WE] 37 INIT [OE] 36 RES [RDY/BSY] 35 RES [I/O7] 34 RES [I/O6] 33 RES [I/O5] 32 RES [I/O4] 31 VCC 30 GND 29 GND 28 FWH3/LAD3 [I/O3] 27 FWH2/LAD2 [I/O2] 26 FWH1/LAD1 [I/O1] 25 FWH0/LAD0 [I/O0] 24 ID0 [A0] 23 ID1 [A1] 22 ID2 [A2] 21 ID3 [A3]

Block Diagram

TBL WP INIT

CLK FWH4/LFRAME

FWH/LAD[3:0]

ID[3:0] GPI[4:0]

IC RST

R/C A[10:0] I/O[7:0]
Ordering Information

Standard Package

ICC mA

Active

Standby
Ordering Code AT49LH00B4-33JC AT49LH00B4-33TC

Green Package Option Pb/Halide-free

ICC mA

Active

Standby
Ordering Code

AT49LH00B4-33JX

Package 32J 40T

Operation Range Extended Commercial
0° to 85°C

Package 32J

Operation Range Extended Commercial
0° to 85°C

Package Type
32-lead, Plastic J-leaded Chip Carrier Package PLCC
40-lead, Thin Small Outline Package TSOP
38 AT49LH00B4

Packaging Information
32J PLCC

AT49LH00B4

PIN NO. 1 IDENTIFIER
e D1 D

B1 E2

A2 A1 A
0.51 0.020 MAX 3X

COMMON DIMENSIONS Unit of Measure = mm

This package conforms to JEDEC reference MS-016, Variation AE. Dimensions D1 and E1 do not include mold protrusion.

Allowable protrusion is mm per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. Lead coplanarity is mm maximum.

SYMBOL MIN NOM MAX NOTE

Note 2

Note 2
10/04/01

TITLE 2325 Orchard Parkway 32J, 32-lead, Plastic J-leaded Chip Carrier PLCC R San Jose, CA 95131
40T TSOP

PIN 1
0º ~ 8º c

Pin 1 Identifier

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-142, Variation CD. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 A2 D D1 E L L1 b c e

MIN NOM MAX

BASIC

BASIC

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Datasheet ID: AT49LH00B4-33JX 518708