AT49F1024-55VC

AT49F1024-55VC Datasheet


The AT49F1024 and the AT49F1025 are 5-volt-only in-system Flash memories. Their 1 megabit of memory is organized as 65,536 words by 16 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 35 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA. The only difference between the AT49F1024 and the AT49F1025 is the package.

Part Datasheet
AT49F1024-55VC AT49F1024-55VC AT49F1024-55VC (pdf)
Related Parts Information
AT49F1024-70VI AT49F1024-70VI AT49F1024-70VI
AT49F1024-70VC AT49F1024-70VC AT49F1024-70VC
AT49F1025-70JC AT49F1025-70JC AT49F1025-70JC
AT49F1025-70JI AT49F1025-70JI AT49F1025-70JI
AT49F1024-55VI AT49F1024-55VI AT49F1024-55VI
AT49F1025-55JI AT49F1025-55JI AT49F1025-55JI
PDF Datasheet Preview
• Single-voltage Operation 5V Read
5V Reprogramming
• Fast Read Access Time 35 ns
• Internal Program Control and Timer
• 8K Word Boot Block with Lockout
• Fast Erase Cycle Time 10 seconds
• Word-by-word Programming 10 µs/Word Typical
• Hardware Data Protection
• Data Polling for End of Program Detection
• Small 10 x 14 mm VSOP Package
• Typical 10,000 Write Cycles

The AT49F1024 and the AT49F1025 are 5-volt-only in-system Flash memories. Their 1 megabit of memory is organized as 65,536 words by 16 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 35 ns with power dissipation of just 275 mW over the commercial temperature range. When the device is deselected, the CMOS standby current is less than 100 µA. The only difference between the AT49F1024 and the AT49F1025 is the package.

To allow for simple in-system reprogrammability, the AT49F1024/1025 does not require high-input voltages for programming. Five-volt-only commands determine the
continued

Pin Configurations

Pin Name A0 - A15 CE OE WE I/O0 - I/O15 NC

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect

AT49F1025 PLCC Top View
6 I/O13 5 I/O14 4 I/O15 3 CE 2 NC 1 NC 44 VCC 43 WE 42 NC 41 A15 40 A14

I/O12 7 I/O11 8 I/O10 9

I/O9 10 I/O8 11 GND 12 NC 13 I/O7 14 I/O6 15 I/O5 16 I/O4 17
39 A13 38 A12 37 A11 36 A10 35 A9 34 GND 33 NC 32 A8 31 A7 30 A6 29 A5

AT49F1024 VSOP Top View Type 1
10 x 14 mm

A9 1 A10 2 A11 3 A12 4 A13 5 A14 6 A15 7 NC 8 WE 9 VCC 10 NC 11 CE 12 I/O15 13 I/O14 14 I/O13 15 I/O12 16 I/O11 17 I/O10 18 I/O9 19 I/O8 20
40 GND 39 A8 38 A7 37 A6 36 A5 35 A4 34 A3 33 A2 32 A1 31 A0 30 OE 29 I/O0 28 I/O1 27 I/O2 26 I/O3 25 I/O4 24 I/O5 23 I/O6 22 I/O7 21 GND
1-megabit 64K x 16 5-volt Only Flash Memory

AT49F1024 AT49F1025

I/O3 18 I/O2 19 I/O1 20 I/O0 21 OE 22 NC 23

A0 24 A1 25 A2 26 A3 27 A4 28

Block Diagram
read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49F1024/1025 is performed by erasing a block of data entire chip or main memory block and then programming on a word-by-word basis. The typical word programming time is a fast 10 µs. The end of a program cycle can be optionally detected by the Data Polling feature. Once the end of a byte program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

The optional 8K word boot block section includes a reprogramming write lockout feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being erased or reprogrammed.

VCC GND

OE WE CE

ADDRESS INPUTS

OE, CE, AND WE LOGIC

Y DECODER X DECODER

DATA INPUTS/OUTPUTS I/O15 - I/O0

DATA LATCH

INPUT/OUTPUT BUFFERS

Y-GATING

MAIN MEMORY 56K WORDS

OPTIONAL BOOT BLOCK 8K WORDS

FFFFH
2000H 1FFFH
0000H

Device Operation

READ The AT49F1024/1025 is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual line control gives designers flexibility in preventing bus contention.

CHIP ERASE When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together from the same Chip Erase command See Command Definitions table . If the boot block lockout function has been enabled, data in the boot section will not be erased. However, data in the main memory section will be erased. After a chip erase, the device will return to the read mode.
AT49F1024 Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code AT49F1024-35VC

AT49F1024-45VC

AT49F1024-50VC

AT49F1024-55VC

AT49F1024-55VI

AT49F1024-70VC

AT49F1024-70VI
AT49F1025 Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code AT49F1025-35JC

AT49F1025-45JC

AT49F1025-55JC

AT49F1025-55JI

AT49F1025-70JC

AT49F1025-70JI

AT49F1024/1025

Package 40V

Package 44J

Operation Range Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Industrial -40° to 85°C Commercial 0° to 70°C Industrial -40° to 85°C

Operation Range Commercial 0° to 70°C Commercial 0° to 70°C Commercial 0° to 70°C Industrial -40° to 85°C Commercial 0° to 70°C Industrial -40° to 85°C

Package Type
44-lead, Plastic J-leaded Chip Carrier Package PLCC
40-lead, 10 mm x 14 mm, Thin Small Outline Package VSOP

Packaging Information
44J, 44-lead, Plastic J-leaded Chip Carrier PLCC Dimensions in Inches and Millimeters

JEDEC STANDARD MS-018 AC

X 45° PIN NO. 1 IDENTIFY

X 30° - 45°
.685 17.4 SQ

REF SQ

X 45° MAX 3X
40V, 40-lead, Plastic Thin Small Outline Package VSOP Dimensions in Millimeters and Inches *
*Controlling dimension millimeters
14 AT49F1024/1025

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More datasheets: ABX00011 | 400494 | 74LVTH543MTC | 74LVTH543MTCX | 74LVTH543WMX | 74LVTH543WM | AT49F1024-70VI | AT49F1024-70VC | AT49F1025-70JC | AT49F1025-70JI


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Datasheet ID: AT49F1024-55VC 518695