AT49BV6416C-70CI

AT49BV6416C-70CI Datasheet

The AT49BV6416C T is a 2.7-volt 64-megabit Flash memory. The memory is divided into multiple sectors and planes for erase operations. The device can be read or reprogrammed off a single 2.7V power supply, making it ideally suited for In-System programming. The device can operate in the asynchronous or page read mode.

Part	Datasheet
AT49BV6416C-70CI	AT49BV6416C-70CI (pdf)

Related Parts	Information
AT49BV6416CT-70CI	AT49BV6416CT-70CI

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• 64-megabit 4M x 16 Flash Memory • 2.7V - 3.6V Read/Write • High Performance Asynchronous Access Time 70 ns Page Mode Read Time 20 ns • Sector Erase Architecture Eight 4K Word Sectors with Individual Write Lockout One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout • Typical Sector Erase Time 32K Word Sectors 700 ms 4K Word Sectors 200 ms • Four Plane Organization, Permitting Concurrent Read in Any of the Three Planes not Being Programmed/Erased Memory Plane A 16M Memory Including Eight 4K Word Sectors Memory Plane B 16M Memory Consisting of 32K Word Sectors Memory Plane C 16M Memory Consisting of 32K Word Sectors Memory Plane D 16M Memory Consisting of 32K Word Sectors • Suspend/Resume Feature for Erase and Program Supports Reading and Programming Data from Any Sector by Suspending Erase of a Different Sector Supports Reading Any Word by Suspending Programming of Any Other Word • Low-power Operation 30 mA Active 25 µA Standby • 2.2V I/O Option Reduces Overall System Power • VPP Pin for Write Protection and Accelerated Program/Erase Operations • RESET Input for Device Initialization • CBGA Package • Top or Bottom Boot Block Configuration Available • 128-bit Protection Register • Common Flash Interface CFI The AT49BV6416C T is a 2.7-volt 64-megabit Flash memory. The memory is divided into multiple sectors and planes for erase operations. The device can be read or reprogrammed off a single 2.7V power supply, making it ideally suited for In-System programming. The device can operate in the asynchronous or page read mode. 64-megabit 4M x 16 Page Mode 2.7-volt Flash Memory AT49BV6416C AT49BV6416CT Pin Configurations Pin Name I/O0 - I/O15 A0 - A21 CE OE WE RESET WP VPP VCCQ Pin Function Data Inputs/Outputs Addresses Chip Enable Output Enable Write Enable Reset Write Protect Write Protection and Power Supply for Accelerated Program/Erase Operations Output Power Supply AT49BV6416 T 7 x 10 mm Top View 1 2 3 4 5 6 78 A13 A11 A8 VPP WP A19 A7 A4 A14 A10 WE RST A18 A17 A5 A2 A15 A12 A9 A21 A20 A6 A3 A1 A16 I/O14 I/O5 I/O11 I/O2 I/O8 CE A0 VCCQ I/O15 I/O6 I/O12 I/O3 I/O9 I/O0 GND GND I/O7 I/O13 I/O4 VCC I/O10 I/O1 OE Device Operation The AT49BV6416C T is divided into four memory planes. A read operation can occur in any of the three planes which is not being programmed or erased. This concurrent operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors. There is no reason to suspend the erase or program operation if the data to be read is in another memory plane. The VPP pin provides data protection and faster programming and erase times. When the VPP input is below 0.7V, the program and erase functions are inhibited. When VPP is at 1.65V or above, normal program and erase operations can be performed. With VPP at 12.0V, the program Dual-word Program command and erase operations are accelerated. COMMAND SEQUENCES When the device is first powered on, it will be in the read mode. Command sequences are used to place the device in other operating modes such as program and erase. The command sequences are written by applying a low pulse on the WE input with CE low and OE high or by applying a low-going pulse on the CE input with WE low and OE high. The address is latched on the first rising edge of the WE or CE. Valid data is latched on the rising edge of the WE or the CE pulse, whichever occurs first. The addresses used in the command sequences are not affected by entering the command sequences. ASYNCHRONOUS READ The AT49BV6416C T is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention. PAGE READ The page read operation of the device is controlled by CE and OE inputs. The page size is four words. The first word access of the page read is the same as the asynchronous read. The first word is read at an asynchronous speed of 70 ns. Once the first word is read, toggling A0 and A1 will result in subsequent reads within the page being output at a speed of 20 ns. The page read diagram is shown on page RESET A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET pin halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to read mode. ERASE Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical The entire memory can be erased by using the Chip Erase command or individual planes can be erased by using the Plane Erase command or individual sectors can be erased by using the Sector Erase command. CHIP ERASE Chip Erase is a two-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected sectors. The hardware reset during chip erase will stop the erase, but the data will be of an unknown state. PLANE ERASE As an alternative to a full Chip Erase, the device is organized into four planes that can be individually erased. The Plane Erase command is a two-bus cycle operation. The plane whose address is valid at the second rising edge of WE will be erased. The Plane Erase command does not alter the data in the protected sectors. SECTOR ERASE The device is organized into multiple sectors that can be individually erased. The Sector Erase command is a two-bus cycle operation. The sector whose address is valid at the second rising edge of WE will be erased provided the given sector has not been protected. 2 AT49BV6416C T [Preliminary] AT49BV6416C T [Preliminary] WORD PROGRAMMING The device is programmed on a word-by-word basis. Programming is accomplished via the internal device command register and is a two-bus cycle operation. The programming address and data are latched in the second cycle. The device will automatically generate the required internal programming pulses. Please note that a “0” cannot be programmed back to a “1” only erase operations can convert “0”s to “1”s. FLEXIBLE SECTOR PROTECTION The AT49BV6416C T offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes frequently. The Hardlock protection mode is recommended for sectors whose content changes infrequently. Once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. Each sector can be independently programmed for either the Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled. SOFTLOCK AND UNLOCK The Softlock protection mode can be disabled by issuing a twobus cycle Unlock command to the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the selected sector. HARDLOCK AND WRITE PROTECT WP The Hardlock sector protection mode operates in conjunction with the Write Protection WP pin. The Hardlock sector protection mode can be enabled by issuing a two-bus cycle Hardlock software command to the selected sector. The state of the Write Protect pin affects whether the Hardlock protection mode can be overridden. • When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be unlocked and the contents of the sector is read-only. • When the WP pin is high, the Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command. To disable the Hardlock sector protection mode, the chip must be either reset or power cycled. Table Hardlock and Softlock Protection Configurations in Conjunction with WP Erase/ Hard- AT49BV6416C T Ordering Information tACC ICC mA Active Standby Ordering Code AT49BV6416C-70CI AT49BV6416CT-70CI Package 48C20 48C20 Operation Range Industrial -40° to 85°C Industrial -40° to 85°C 48C20 Package Type 48-ball, Plastic Chip-size Ball Grid Array Package CBGA Packaging Information AT49BV6416C T 48C20 CBGA E A1 BALL ID Top View A B C D E F 8 7 6 5 4 3 21 Øb Bottom View A1 BALL CORNER REF Side View COMMON DIMENSIONS Unit of Measure = mm SYMBOL E E1 D D1 A A1 e Øb NOM MAX NOTE TITLE 2325 Orchard Parkway 48C20, 48-ball 8 x 6 Array ,0.75 mm Pitch, x mm R San Jose, CA 95131 Chip-scale Ball Grid Array Package CBGA 01/8/04 48C20 28 AT49BV6416C T [Preliminary] Atmel Corporation 2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 487-2600 Regional Headquarters Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel 41 26-426-5555 Fax 41 26-426-5500 Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721-9778 Fax 852 2722-1369 Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581 Atmel Operations Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 436-4314 Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 436-4314 La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel 33 2-40-18-18-18 Fax 33 2-40-18-19-60 ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel 33 4-42-53-60-00 Fax 33 4-42-53-60-01 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel 1 719 576-3300 Fax 1 719 540-1759 Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel 44 1355-803-000 Fax 44 1355-242-743 RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel 49 71-31-67-0 Fax 49 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel 1 719 576-3300 Fax 1 719 540-1759 Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel 33 4-76-58-30-00 Fax 33 4-76-58-34-80

PDF Datasheet Preview

• 64-megabit 4M x 16 Flash Memory
• 2.7V - 3.6V Read/Write
• High Performance

Asynchronous Access Time 70 ns Page Mode Read Time 20 ns
• Sector Erase Architecture Eight 4K Word Sectors with Individual Write Lockout One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout
• Typical Sector Erase Time 32K Word Sectors 700 ms 4K Word Sectors 200 ms
• Four Plane Organization, Permitting Concurrent Read in Any of the Three Planes not Being Programmed/Erased Memory Plane A 16M Memory Including Eight 4K Word Sectors Memory Plane B 16M Memory Consisting of 32K Word Sectors Memory Plane C 16M Memory Consisting of 32K Word Sectors Memory Plane D 16M Memory Consisting of 32K Word Sectors
• Suspend/Resume Feature for Erase and Program Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation 30 mA Active 25 µA Standby
• 2.2V I/O Option Reduces Overall System Power
• VPP Pin for Write Protection and Accelerated Program/Erase Operations
• RESET Input for Device Initialization
• CBGA Package
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Common Flash Interface CFI

The AT49BV6416C T is a 2.7-volt 64-megabit Flash memory. The memory is divided into multiple sectors and planes for erase operations. The device can be read or reprogrammed off a single 2.7V power supply, making it ideally suited for In-System programming. The device can operate in the asynchronous or page read mode.
64-megabit 4M x 16 Page Mode 2.7-volt Flash Memory

AT49BV6416C AT49BV6416CT

Pin Configurations

Pin Name I/O0 - I/O15 A0 - A21 CE OE WE RESET WP VPP

VCCQ

Pin Function Data Inputs/Outputs Addresses Chip Enable Output Enable Write Enable Reset Write Protect Write Protection and Power Supply for Accelerated Program/Erase Operations Output Power Supply

AT49BV6416 T 7 x 10 mm Top View
1 2 3 4 5 6 78

A13 A11 A8 VPP WP A19 A7 A4

A14 A10 WE RST A18 A17 A5 A2

A15 A12 A9 A21 A20 A6 A3 A1

A16 I/O14 I/O5 I/O11 I/O2 I/O8 CE A0

VCCQ I/O15 I/O6 I/O12 I/O3 I/O9 I/O0 GND

GND I/O7 I/O13 I/O4 VCC I/O10 I/O1 OE

Device Operation

The AT49BV6416C T is divided into four memory planes. A read operation can occur in any of the three planes which is not being programmed or erased. This concurrent operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors. There is no reason to suspend the erase or program operation if the data to be read is in another memory plane.

The VPP pin provides data protection and faster programming and erase times. When the VPP input is below 0.7V, the program and erase functions are inhibited. When VPP is at 1.65V or above, normal program and erase operations can be performed. With VPP at 12.0V, the program Dual-word Program command and erase operations are accelerated.

COMMAND SEQUENCES When the device is first powered on, it will be in the read mode. Command sequences are used to place the device in other operating modes such as program and erase. The command sequences are written by applying a low pulse on the WE input with CE low and OE high or by applying a low-going pulse on the CE input with WE low and OE high. The address is latched on the first rising edge of the WE or CE. Valid data is latched on the rising edge of the WE or the CE pulse, whichever occurs first. The addresses used in the command sequences are not affected by entering the command sequences.

ASYNCHRONOUS READ The AT49BV6416C T is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

PAGE READ The page read operation of the device is controlled by CE and OE inputs. The page size is four words. The first word access of the page read is the same as the asynchronous read. The first word is read at an asynchronous speed of 70 ns. Once the first word is read, toggling A0 and A1 will result in subsequent reads within the page being output at a speed of 20 ns. The page read diagram is shown on page

RESET A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET pin halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to read mode.

ERASE Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical The entire memory can be erased by using the Chip Erase command or individual planes can be erased by using the Plane Erase command or individual sectors can be erased by using the Sector Erase command.

CHIP ERASE Chip Erase is a two-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected sectors. The hardware reset during chip erase will stop the erase, but the data will be of an unknown state.

PLANE ERASE As an alternative to a full Chip Erase, the device is organized into four planes that can be individually erased. The Plane Erase command is a two-bus cycle operation. The plane whose address is valid at the second rising edge of WE will be erased. The Plane Erase command does not alter the data in the protected sectors.

SECTOR ERASE The device is organized into multiple sectors that can be individually erased. The Sector Erase command is a two-bus cycle operation. The sector whose address is valid at the second rising edge of WE will be erased provided the given sector has not been protected.
2 AT49BV6416C T [Preliminary]

AT49BV6416C T [Preliminary]

WORD PROGRAMMING The device is programmed on a word-by-word basis. Programming is accomplished via the internal device command register and is a two-bus cycle operation. The programming address and data are latched in the second cycle. The device will automatically generate the required internal programming pulses. Please note that a “0” cannot be programmed back to a “1” only erase operations can convert “0”s to “1”s.

FLEXIBLE SECTOR PROTECTION The AT49BV6416C T offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes frequently. The Hardlock protection mode is recommended for sectors whose content changes infrequently. Once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. Each sector can be independently programmed for either the Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled.

SOFTLOCK AND UNLOCK The Softlock protection mode can be disabled by issuing a twobus cycle Unlock command to the selected sector. Once a sector is unlocked, its contents can be erased or programmed. To enable the Softlock protection mode, a two-bus cycle Softlock command must be issued to the selected sector.

HARDLOCK AND WRITE PROTECT WP The Hardlock sector protection mode operates in conjunction with the Write Protection WP pin. The Hardlock sector protection mode can be enabled by issuing a two-bus cycle Hardlock software command to the selected sector. The state of the Write Protect pin affects whether the Hardlock protection mode can be overridden.
• When the WP pin is low and the Hardlock protection mode is enabled, the sector cannot be
unlocked and the contents of the sector is read-only.
• When the WP pin is high, the Hardlock protection mode is overridden and the sector can be unlocked via the Unlock command.

To disable the Hardlock sector protection mode, the chip must be either reset or power cycled.

Table Hardlock and Softlock Protection Configurations in Conjunction with WP

Erase/

Hard-
AT49BV6416C T Ordering Information
tACC

ICC mA

Active

Standby
Ordering Code AT49BV6416C-70CI

AT49BV6416CT-70CI

Package 48C20
48C20

Operation Range

Industrial -40° to 85°C

Industrial -40° to 85°C
48C20

Package Type 48-ball, Plastic Chip-size Ball Grid Array Package CBGA

Packaging Information AT49BV6416C T 48C20 CBGA

E A1 BALL ID

Top View

A B C D E F
8 7 6 5 4 3 21 Øb

Bottom View

A1 BALL CORNER REF

Side View

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL E E1 D D1 A A1 e Øb

NOM MAX

NOTE

TITLE 2325 Orchard Parkway 48C20, 48-ball 8 x 6 Array ,0.75 mm Pitch, x mm R San Jose, CA 95131 Chip-scale Ball Grid Array Package CBGA
01/8/04
48C20
28 AT49BV6416C T [Preliminary]

Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 487-2600

Regional Headquarters

Europe Atmel Sarl Route des Arsenaux 41 Case Postale 80 CH-1705 Fribourg Switzerland Tel 41 26-426-5555 Fax 41 26-426-5500

Asia Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimshatsui East Kowloon Hong Kong Tel 852 2721-9778 Fax 852 2722-1369

Japan 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan Tel 81 3-3523-3551 Fax 81 3-3523-7581

Atmel Operations

Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 436-4314

Microcontrollers 2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 436-4314

La Chantrerie BP 70602 44306 Nantes Cedex 3, France Tel 33 2-40-18-18-18 Fax 33 2-40-18-19-60

ASIC/ASSP/Smart Cards Zone Industrielle 13106 Rousset Cedex, France Tel 33 4-42-53-60-00 Fax 33 4-42-53-60-01
1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel 1 719 576-3300 Fax 1 719 540-1759

Scottish Enterprise Technology Park Maxwell Building East Kilbride G75 0QR, Scotland Tel 44 1355-803-000 Fax 44 1355-242-743

RF/Automotive Theresienstrasse 2 Postfach 3535 74025 Heilbronn, Germany Tel 49 71-31-67-0 Fax 49 71-31-67-2340 1150 East Cheyenne Mtn. Blvd. Colorado Springs, CO 80906, USA Tel 1 719 576-3300 Fax 1 719 540-1759

Biometrics/Imaging/Hi-Rel MPU/ High Speed Converters/RF Datacom

Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex, France Tel 33 4-76-58-30-00 Fax 33 4-76-58-34-80

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Datasheet ID: AT49BV6416C-70CI 518679