AT49BV6416T-70TI-T

AT49BV6416T-70TI-T Datasheet


AT49BV6416 AT49BV6416T

Part Datasheet
AT49BV6416T-70TI-T AT49BV6416T-70TI-T AT49BV6416T-70TI-T (pdf)
Related Parts Information
AT49BV6416-70TU-T AT49BV6416-70TU-T AT49BV6416-70TU-T
AT49BV6416T-70TI AT49BV6416T-70TI AT49BV6416T-70TI
AT49BV6416-70TI AT49BV6416-70TI AT49BV6416-70TI
AT49BV6416-70TI-T AT49BV6416-70TI-T AT49BV6416-70TI-T
AT49BV6416-70TU AT49BV6416-70TU AT49BV6416-70TU
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• 64-megabit 4M x 16 Flash Memory
• 2.7V - 3.6V Read/Write
• High Performance

Asynchronous Access Time 70 ns Page Mode Read Time 20 ns
• Sector Erase Architecture Eight 4K Word Sectors with Individual Write Lockout One Hundred Twenty-seven 32K Word Main Sectors with Individual Write Lockout
• Typical Sector Erase Time 32K Word Sectors 700 ms 4K Word Sectors 200 ms
• Four Plane Organization, Permitting Concurrent Read in Any of Three Planes not Being Programmed/Erased Memory Plane A 16M of Memory Including Eight 4K Word Sectors Memory Plane B 16M of Memory Consisting of 32K Word Sectors Memory Plane C 16M of Memory Consisting of 32K Word Sectors Memory Plane D 16M of Memory Consisting of 32K Word Sectors
• Suspend/Resume Feature for Erase and Program Supports Reading and Programming Data from Any Sector by Suspending Erase
of a Different Sector Supports Reading Any Word by Suspending Programming of Any Other Word
• Low-power Operation 30 mA Active 35 µA Standby
• 2.2V I/O Option Reduces Overall System Power
• Data Polling and Toggle Bit for End of Program Detection
• VPP Pin for Write Protection and Accelerated Program Operations
• RESET Input for Device Initialization
• TSOP Package
• Top or Bottom Boot Block Configuration Available
• 128-bit Protection Register
• Common Flash Interface CFI
• Green Pb/Halide-free Packaging Option
64-megabit 4M x 16 Page Mode 2.7-volt Flash Memory

AT49BV6416 AT49BV6416T

Not Recommended for New Design. Use AT49BV642D T .

The AT49BV6416 T is a 2.7-volt 64-megabit Flash memory. The memory is divided into multiple sectors and planes for erase operations. The device can be read or reprogrammed off a single 2.7V power supply, making it ideally suited for in-system programming. The output voltage can be separately controlled down to 2.2V through the VCCQ supply pin. The device can operate in the asynchronous or page read mode.

The AT49BV6416 T is divided into four memory planes. A read operation can occur in any of the three planes which is not being programmed or erased. This concurrent operation allows improved system performance by not requiring the system to wait for a program or erase operation to complete before a read is performed. To further increase the flexibility of the device, it contains an Erase Suspend and Program Suspend feature. This feature will put the erase or program on hold for any amount of time and let the user read data from or program data to any of the remaining sectors. There is no reason to suspend the erase or program operation if the data to be read is in another memory plane. The end of program or erase is detected by Data Polling or toggle bit.

The VPP pin provides data protection and faster programming times. When the VPP input is below 0.7V, the program and erase functions are inhibited. When VPP is at 1.65V or above, normal program and erase operations can be performed. With VPP at 10.0V, the program dualword program command operation is accelerated.

A six-byte command Enter Single Pulse Program Mode to remove the requirement of entering the three-byte program sequence is offered to further improve programming time. After entering the six-byte code, only single pulses on the write control lines are required for writing into the device. This mode Single Pulse Word Program is exited by powering down the device, by taking the RESET pin to GND or by a high-to-low transition on the VPP input. Erase, Erase Suspend/Resume, Program Suspend/Resume and Read Reset commands will not work while in this mode if entered they will result in data being programmed into the device. It is not recommended that the six-byte code reside in the software of the final product but only exist in external programming code.

Pin Configurations

Pin Name I/O0 - I/O15 A0 - A21 CE OE WE RESET WP

VCCQ

TSOP Top View Type 1

Pin Function Data Inputs/Outputs Addresses Chip Enable Output Enable Write Enable Reset Write Protect Write Protection and Power Supply for Accelerated Program Operations Output Power Supply

A15 1 A14 2 A13 3 A12 4 A11 5 A10 6

A9 7 A8 8 A21 9 A20 10 WE 11 RESET 12 VPP 13 WP 14 A19 15 A18 16 A17 17 A7 18 A6 19 A5 20 A4 21 A3 22 A2 23 A1 24
48 A16 47 VCCQ 46 GND 45 I/O15 44 I/O7 43 I/O14 42 I/O6 41 I/O13 40 I/O5 39 I/O12 38 I/O4 37 VCC 36 I/O11 35 I/O3 34 I/O10 33 I/O2 32 I/O9 31 I/O1 30 I/O8 29 I/O0 28 OE 27 GND 26 CE 25 A0
2 AT49BV6416 T

AT49BV6416 T

Device Operation

Command Sequences

The device powers on in the read mode. Command sequences are used to place the device in other operating modes such as program and erase. After the completion of a program or an erase cycle, the device enters the read mode. The command sequences are written by applying a low pulse on the WE input with CE low and OE high or by applying a low-going pulse on the CE input with WE low and OE high. The address is latched on the falling edge of the WE or CE pulse whichever occurs first. Valid data is latched on the rising edge of the WE or the CE pulse, whichever occurs first. The addresses used in the command sequences are not affected by entering the command sequences.

Asynchronous Read

The AT49BV6416 T is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins are asserted on the outputs. The outputs are put in the high impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

Page Read

The page read operation of the device is controlled by CE and OE inputs. The page size is four words. The first word access of the page read is the same as the asynchronous read. The first word is read at an asynchronous speed of 70 ns. Once the first word is read, toggling A0 and A1 will result in subsequent reads within the page being output at a speed of 20 ns. The “Page Read Cycle Waveform” is shown on page

Reset

A RESET input pin is provided to ease some system applications. When RESET is at a logic high level, the device is in its standard operating mode. A low level on the RESET pin halts the present device operation and puts the outputs of the device in a high-impedance state. When a high level is reasserted on the RESET pin, the device returns to read or standby mode, depending upon the state of the control pins.

Erase

Before a word can be reprogrammed it must be erased. The erased state of the memory bits is a logical The entire memory can be erased by using the Chip Erase command or individual planes or sectors can be erased by using the Plane Erase or Sector Erase commands.

Chip Erase

Chip Erase is a six-bus cycle operation. The automatic erase begins on the rising edge of the last WE pulse. Chip Erase does not alter the data of the protected sectors. After the full chip erase the device will return back to the read mode. The hardware reset during Chip Erase will stop the erase but the data will be of unknown state. Any command during Chip Erase except Erase Suspend will be ignored.

Plane Erase

As a alternative to a full chip erase, the device is organized into four planes that can be individually erased. The plane erase command is a six-bus cycle operation. The plane whose address is valid at the sixth falling edge of WE will be erased. The plane erase command does not alter the data in protected sectors.

Sector Erase

As an alternative to a full chip erase or a plane erase, the device is organized into multiple sectors that can be individually erased. The Sector Erase command is a six-bus cycle operation. The sector whose address is valid at the sixth falling edge of WE will be erased provided the given sector has not been protected.

Word Programming

The device is programmed on a word-by-word basis. Programming is accomplished via the internal device command register and is a four-bus cycle operation. The programming address and data are latched in the fourth cycle. The device will automatically generate the required internal programming pulses. Please note that a “0” cannot be programmed back to a “1” only erase operations can convert “0”s to “1”s.

Flexible Sector Protection

The AT49BV6416 T offers two sector protection modes, the Softlock and the Hardlock. The Softlock mode is optimized as sector protection for sectors whose content changes frequently. The Hardlock protection mode is recommended for sectors whose content changes infrequently. Once either of these two modes is enabled, the contents of the selected sector is read-only and cannot be erased or programmed. Each sector can be independently programmed for either the Softlock or Hardlock sector protection mode. At power-up and reset, all sectors have their Softlock protection mode enabled.
Ordering Information

Standard Package
tACC

ICC mA

Active

Standby
Ordering Code AT49BV6416-70TI AT49BV6416T-70TI

Green Package Option Pb/Halide-free
tACC

ICC mA

Active

Standby
Ordering Code

AT49BV6416-70TU

AT49BV6416 T

Package 48T

Operation Range Industrial
-40° to 85° C Industrial
-40° to 85° C

Package 48T

Operation Range Industrial
-40° to 85° C

Package Type
48-lead, Plastic Thin Small Outline Package TSOP

Packaging Information
48T TSOP

PIN 1
0º ~ 8º c

Pin 1 Identifier

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-142, Variation DD. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 A2 D D1 E L L1 b c e

MIN NOM MAX

BASIC

BASIC

NOTE

Note 2 Note 2
2325 Orchard Parkway R San Jose, CA 95131
48T, 48-lead 12 x 20 mm Package Plastic Thin Small Outline Package, Type I TSOP
10/18/01
28 AT49BV6416 T

AT49BV6416 T

History
• Initial Release
• Removed “Preliminary” from the datasheet.
• Modified Plane Erase text on page
• Modified note 7 and added notes 11, 12, and 13 on page
• Removed note 1 on page
• Changed SA102 from plane D to plane C on page
• Changed the ISB1 spec to 35 µA.
• Converted datasheet to New Template.
• Changed the VPP value to ± 0.5V in the text, table
on page 12, and CFI table. VPP text also changed to show that a high voltage on VPP improves only the programming time.
• Added Green Package Pb/Halide-free Option in the Ordering Information section.

Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 487-2600

Regional Headquarters

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Atmel Operations

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Datasheet ID: AT49BV6416T-70TI-T 518678