AT49LV1024A-45VC

AT49LV1024A-45VC Datasheet


The AT49BV/LV1024A is a 3-volt only in-system Flash memory. The 1-megabit of memory is organized as 65,536 words by 16 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 45 ns with power dissipation of just 72 mW over the commercial temperature range.

Part Datasheet
AT49LV1024A-45VC AT49LV1024A-45VC AT49LV1024A-45VC (pdf)
Related Parts Information
AT49LV1024A-45VL AT49LV1024A-45VL AT49LV1024A-45VL
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• Single-voltage Operation Read/Write Operation 2.7V to 3.6V BV . 3.0V to 3.6V LV
• Fast Read Access Time 45 ns
• Internal Program Control and Timer
• 8K Word Boot Block with Lockout
• Fast Erase Cycle Time Seconds
• Word-by-word Programming 20 µs/Word Typical
• Hardware Data Protection
• Data Polling for End of Program Detection
• Small 10 x 14 mm VSOP Package
• Typical 10,000 Write Cycles
• Lead-free Packaging Option

The AT49BV/LV1024A is a 3-volt only in-system Flash memory. The 1-megabit of memory is organized as 65,536 words by 16 bits. Manufactured with Atmel’s advanced nonvolatile CMOS technology, the devices offer access times to 45 ns with power dissipation of just 72 mW over the commercial temperature range.

To allow for simple in-system reprogrammability, the AT49BV/LV1024A does not require high input voltages for programming. Three-volt-only commands determine the read and programming operation of the device. Reading data out of the device is similar to reading from an EPROM. Reprogramming the AT49BV/LV1024A is performed by erasing a block of data entire chip or main memory block and then programming on a word-by-word basis. The typical word programming time is a fast 20 µs. The end of a program cycle can be optionally detected by the Data Polling feature. Once the end of a word program cycle has been detected, a new access for a read or program can begin. The typical number of program and erase cycles is in excess of 10,000 cycles.

The optional 8K word boot block section includes a reprogramming write lock out feature to provide data integrity. The boot sector is designed to contain user secure code, and when the feature is enabled, the boot sector is permanently protected from being erased or reprogrammed.

Pin Configurations

Pin Name A0 - A15 CE OE WE I/O0 - I/O15 NC

Function Addresses Chip Enable Output Enable Write Enable Data Inputs/Outputs No Connect
40VSOP Type 1

A9 1 A10 2 A11 3 A12 4 A13 5 A14 6 A15 7 NC 8 WE 9 VCC 10 NC 11 CE 12 I/O15 13 I/O14 14 I/O13 15 I/O12 16 I/O11 17 I/O10 18 I/O9 19 I/O8 20
40 GND 39 A8 38 A7 37 A6 36 A5 35 A4 34 A3 33 A2 32 A1 31 A0 30 OE 29 I/O0 28 I/O1 27 I/O2 26 I/O3 25 I/O4 24 I/O5 23 I/O6 22 I/O7 21 GND
1-megabit 64K x 16 3-volt Only Flash Memory AT49BV1024A AT49LV1024A

Not Recommended for New Design

Contact Atmel to discuss the latest design in trends and options

Block Diagram

VCC GND

OE WE CE

ADDRESS INPUTS

OE, CE, AND WE LOGIC

Y DECODER X DECODER

DATA INPUTS/OUTPUTS I/O15 - I/O0

DATA LATCH

INPUT/OUTPUT BUFFERS

Y-GATING

MAIN MEMORY 56K WORDS

OPTIONAL BOOT BLOCK 8K WORDS

FFFFH
2000H 1FFFH
0000H

Device Operation

Read

The AT49BV/LV1024A is accessed like an EPROM. When CE and OE are low and WE is high, the data stored at the memory location determined by the address pins is asserted on the outputs. The outputs are put in the high-impedance state whenever CE or OE is high. This dual-line control gives designers flexibility in preventing bus contention.

Chip Erase

When the boot block programming lockout feature is not enabled, the boot block and the main memory block will erase together from the same Chip Erase command See “Command Definition Table” on page If the boot block lockout function has been enabled, data in the boot section will not be erased. However, data in the main memory section will be erased. After a chip erase, the device will return to the read mode.

Main Memory Erase

As an alternative to the chip erase, a main memory block erase can be performed, which will erase all words not located in the boot block region to an FFFFH. Data located in the boot region will not be changed during a main memory block erase. The Main Memory Erase command is a six-bus cycle operation. The address 555H is latched on the falling edge of the sixth cycle while the 30H data input is latched on the rising edge of WE. The main memory erase starts after the rising edge of WE of the sixth cycle. Please see “Main Memory or Chip Erase Cycle Waveforms” on page The main memory erase operation is internally controlled it will automatically time to completion.
2 AT49BV/LV1024A

AT49BV/LV1024A

Word Programming

Once the memory array is erased, the device is programmed to a logic “0” on a word-byword basis. Please note that a data “0” cannot be programmed back to a “1” only erase operations can convert “0”s to “1”s. Programming is accomplished via the internal device command register and is a four-bus cycle operation please refer to the “Command Definition Table” on page The device will automatically generate the required internal program pulses.

The program cycle has addresses latched on the falling edge of WE or CE, whichever occurs last, and the data latched on the rising edge of WE or CE, whichever occurs first. Programming is completed after the specified tBP cycle time. The Data Polling feature may also be used to indicate the end of a program cycle.

Boot Block Programming Lockout
Ordering Information

Standard Package Option
tACC

ICC mA

Active

Standby
Ordering Code

AT49LV1024A-45VC

Lead-Free Option
tACC

ICC mA

Active

Standby
Ordering Code AT49LV1024A-45VL

AT49BV/LV1024A

Package 40V

Operation Range Commercial 0° to 70°C

Package 40V

Operation Range Commercial 0° to 70°C

Package Type
40-lead, Thin Small Outline Package VSOP 10 mm x 14 mm

Packaging Information
40V VSOP

PIN 1
0º ~ 8º c

Pin 1 Identifier

SEATING PLANE

GAGE PLANE

This package conforms to JEDEC reference MO-142, Variation CA. Dimensions D1 and E do not include mold protrusion. Allowable
protrusion on E is mm per side and on D1 is mm per side. Lead coplanarity is mm maximum.

COMMON DIMENSIONS Unit of Measure = mm

SYMBOL A A1 A2 D D1 E L L1 b c e

MIN NOM MAX

BASIC

BASIC

NOTE

Note 2 Note 2
2325 Orchard Parkway R San Jose, CA 95131
40V, 40-lead 10 x 14 mm Package Plastic Thin Small Outline Package, Type I VSOP
10/18/01
14 AT49BV/LV1024A

Atmel Corporation
2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 487-2600

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Atmel Operations

Memory 2325 Orchard Parkway San Jose, CA 95131, USA Tel 1 408 441-0311 Fax 1 408 436-4314

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Datasheet ID: AT49LV1024A-45VC 518644