DS1254YB-100

DS1254YB-100 Datasheet

DS1254

Part	Datasheet
DS1254YB-100	DS1254YB-100 (pdf)

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19-4621 5/09 DS1254 2M x 8 NV SRAM with Phantom Clock The DS1254 is a fully nonvolatile static RAM NV SRAM organized as 2M words by 8 bits with built-in real-time clock. It has a self-contained lithium energy source and control circuitry that constantly monitors VCC for an out-oftolerance condition. When such a condition occurs, the DS1254 makes use of an attached DS3800 battery cap to maintain clock information and preserve stored data while protecting that data by disallowing all memory accesses. Additionally, the DS1254 has dedicated circuitry for monitoring the status of an attached DS3800 battery cap. • Real-Time Clock RTC Keeps Track of Hundredths of Seconds, Seconds, Minutes, Hours, Days, Date, Months, and Years with Automatic Leap-Year Compensation Valid Up to the Year 2100 • 2M x 8 NV SRAM • Watch Function is Transparent to RAM Operation • Automatic Data Protection During Power Loss • Unlimited Write-Cycle Endurance • Surface-Mountable BGA Module Construction • Over 10 Years of Data Retention in the Absence of Power • Battery Monitor Checks Remaining Capacity Daily • +3.3V or +5V Operation • Underwriters Laboratory UL Recognized Side -A- Shown For Reference Only, Not to Scale Component placement may vary. TYPICAL OPERATING CIRCUIT Telecom Switches Routers RAID Systems ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE DS1254WB-150 DS1254WB2-150 DS1254YB-100 DS1254YB2-100 0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C 40mm BGA 40mm BGA 40mm BGA 40mm BGA VOLTAGE RANGE V TOP MARK DS1254W-150 DS1254W-150 DS1254Y-100 DS1254Y-100 1 of 18 DS1254 DETAILED DESCRIPTION The DS1254 is a fully nonvolatile static RAM NV SRAM organized as 2M words by 8 bits with built-in real-time clock. It has a self-contained lithium energy source and control circuitry that constantly monitors VCC for an out-oftolerance condition. When such a condition occurs, the DS1254 makes use of an attached DS3800 battery cap to maintain clock information and preserve stored data while protecting that data by disallowing all memory accesses. Additionally, the DS1254 has dedicated circuitry for monitoring the status of an attached DS3800 battery cap. The phantom clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap years. The phantom clock operates in either 24-hour or 12-hour format with an AM/PM indicator. Because the DS1254 has a total of 168 balls and only 35 active signals, balls are wired together into groups, thus providing redundant connections for every signal. Figure Pin Configuration VBAT Dallas Semiconductor DS1254 RECEPTACLES FOR DS3800 BATTERY CAP PINS 2 of 18 DS1254 RAM READ MODE The DS1254 executes a read cycle whenever WE is inactive high and CE is active low . The unique address specified by the 21 address inputs defines which of the 2MB of data is to be accessed. Valid data will be available to the eight data-output drivers within tACC access time after the last address input is stable, providing that CE and OE access times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal CE or OE and the limiting parameter is either tCO for CE or tOE for OE rather than address access. RAM WRITE MODE The DS1254 is in the write mode whenever WE and CE are in their active low state after address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time tWR before another cycle can be initiated. The OE control signal should be kept inactive high during write cycles to avoid bus contention. However, if the output bus has been enabled CE and OE active , then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The device is fully accessible and data can be written and read only when VCC is greater than VPF. However, when VCC falls below the power-fail point, VPF point at which write protection occurs , the internal clock registers and SRAM are blocked from any access. When VCC falls below VBAT, device power is switched from the VCC to VBAT. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. All signals must be powered down when VCC is powered down. PHANTOM CLOCK OPERATION Communication with the phantom clock is established by pattern recognition on a serial bit stream of 64 bits that must be matched by executing 64 consecutive write cycles containing the proper data on DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory. After recognition is established, the next 64 read or write cycles either extract or update data in the phantom clock, and memory access is inhibited. Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable CE , output enable OE , and write enable WE . Initially, a read cycle to any memory location using the CE and OE control of the phantom clock starts the pattern-recognition sequence by moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CE and WE signals of the device. These 64 write cycles are used only to gain access to the phantom clock. Therefore, any address within the first 512kB of memory, 00h to 7FFFFh is acceptable. However, the write cycles generated to gain access to the phantom clock are also writing data to a location in the memory. The preferred way to manage this requirement is to set aside just one address location in memory as a phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched this bit pattern is shown in Figure With a correct match for 64-bits, the phantom clock is enabled and 3 of 18 DS1254 data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without interrupting the pattern-recognition sequence or data-transfer sequence to the phantom clock. PHANTOM CLOCK REGISTER INFORMATION The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially accessed one bit at a time after the 64-bit pattern-recognition sequence has been completed. When updating the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These read/write registers are defined in Figure Figure Phantom Clock Protocol Definition NOTE THE PATTERN RECOGNITION IN HEX IS C5, 3A, A3, 5C, C5, 3A, A3, 5C. THE ODDS OF THIS PATTERN BEING ACCIDENTALLY DUPLICATED AND CAUSING INADVERTENT ENTRY TO THE PHANTOM CLOCK IS LESS THAN 1 IN THIS PATTERN IS SENT TO THE PHANTOM CLOCK LSB TO MSB 4 of 18 Figure Phantom Clock Register Definition DS1254

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19-4621 5/09

DS1254
2M x 8 NV SRAM with Phantom Clock

The DS1254 is a fully nonvolatile static RAM NV SRAM organized as 2M words by 8 bits with built-in real-time clock. It has a self-contained lithium energy source and control circuitry that constantly monitors VCC for an out-oftolerance condition. When such a condition occurs, the DS1254 makes use of an attached DS3800 battery cap to maintain clock information and preserve stored data while protecting that data by disallowing all memory accesses. Additionally, the DS1254 has dedicated circuitry for monitoring the status of an attached DS3800 battery cap.
• Real-Time Clock RTC Keeps Track of Hundredths of Seconds, Seconds, Minutes, Hours, Days, Date, Months, and Years with Automatic Leap-Year Compensation Valid Up to the Year 2100
• 2M x 8 NV SRAM
• Watch Function is Transparent to RAM Operation
• Automatic Data Protection During Power Loss
• Unlimited Write-Cycle Endurance
• Surface-Mountable BGA Module Construction
• Over 10 Years of Data Retention in the Absence of Power
• Battery Monitor Checks Remaining Capacity Daily
• +3.3V or +5V Operation
• Underwriters Laboratory UL Recognized

Side -A- Shown For Reference Only, Not to Scale Component placement may vary.

TYPICAL OPERATING CIRCUIT

Telecom Switches Routers RAID Systems
ORDERING INFORMATION

PART

TEMP RANGE PIN-PACKAGE

DS1254WB-150 DS1254WB2-150 DS1254YB-100 DS1254YB2-100
0°C to +70°C 0°C to +70°C 0°C to +70°C 0°C to +70°C
40mm BGA 40mm BGA 40mm BGA 40mm BGA

VOLTAGE RANGE V

TOP MARK

DS1254W-150 DS1254W-150 DS1254Y-100 DS1254Y-100
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DS1254

DETAILED DESCRIPTION

The DS1254 is a fully nonvolatile static RAM NV SRAM organized as 2M words by 8 bits with built-in real-time clock. It has a self-contained lithium energy source and control circuitry that constantly monitors VCC for an out-oftolerance condition. When such a condition occurs, the DS1254 makes use of an attached DS3800 battery cap to maintain clock information and preserve stored data while protecting that data by disallowing all memory accesses. Additionally, the DS1254 has dedicated circuitry for monitoring the status of an attached DS3800 battery cap.

The phantom clock provides timekeeping information including hundredths of seconds, seconds, minutes, hours, day, date, month, and year information. The date at the end of the month is automatically adjusted for months with fewer than 31 days, including correction for leap years. The phantom clock operates in either 24-hour or 12-hour format with an AM/PM indicator.

Because the DS1254 has a total of 168 balls and only 35 active signals, balls are wired together into groups, thus providing redundant connections for every signal.

Figure Pin Configuration

VBAT

Dallas Semiconductor

DS1254

RECEPTACLES FOR DS3800 BATTERY CAP PINS
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DS1254

RAM READ MODE

The DS1254 executes a read cycle whenever WE is inactive high and CE is active low . The unique address specified by the 21 address inputs defines which of the 2MB of data is to be accessed. Valid data will be available to the eight data-output drivers within tACC access time after the last address input is stable, providing that CE and OE access times and states are also satisfied. If OE and CE access times are not satisfied, then data access must be measured from the later occurring signal CE or OE and the limiting parameter is either tCO for CE or tOE for OE rather than address access.

RAM WRITE MODE

The DS1254 is in the write mode whenever WE and CE are in their active low state after address inputs are stable. The later occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE. All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time tWR before another cycle can be initiated. The OE control signal should be kept inactive high during write cycles to avoid bus contention. However, if the output bus has been enabled CE and OE active , then WE will disable the outputs in tODW from its falling edge.

DATA RETENTION MODE

The device is fully accessible and data can be written and read only when VCC is greater than VPF. However, when VCC falls below the power-fail point, VPF point at which write protection occurs , the internal clock registers and SRAM are blocked from any access. When VCC falls below VBAT, device power is switched from the VCC to VBAT. RTC operation and SRAM data are maintained from the battery until VCC is returned to nominal levels. All signals must be powered down when VCC is powered down.

PHANTOM CLOCK OPERATION

Communication with the phantom clock is established by pattern recognition on a serial bit stream of 64 bits that must be matched by executing 64 consecutive write cycles containing the proper data on DQ0. All accesses that occur prior to recognition of the 64-bit pattern are directed to memory.

After recognition is established, the next 64 read or write cycles either extract or update data in the phantom clock, and memory access is inhibited.

Data transfer to and from the timekeeping function is accomplished with a serial bit stream under control of chip enable CE , output enable OE , and write enable WE . Initially, a read cycle to any memory location using the CE and OE control of the phantom clock starts the pattern-recognition sequence by moving a pointer to the first bit of the 64-bit comparison register. Next, 64 consecutive write cycles are executed using the CE and WE signals of the device. These 64 write cycles are used only to gain access to the phantom clock. Therefore, any address within the first 512kB of memory, 00h to 7FFFFh is acceptable. However, the write cycles generated to gain access to the phantom clock are also writing data to a location in the memory. The preferred way to manage this requirement is to set aside just one address location in memory as a phantom clock scratch pad. When the first write cycle is executed, it is compared to bit 0 of the 64-bit comparison register. If a match is found, the pointer increments to the next location of the comparison register and awaits the next write cycle. If a match is not found, the pointer does not advance and all subsequent write cycles are ignored. If a read cycle occurs at any time during pattern recognition, the present sequence is aborted and the comparison register pointer is reset. Pattern recognition continues for a total of 64 write cycles as described above until all the bits in the comparison register have been matched this bit pattern is shown in Figure With a correct match for 64-bits, the phantom clock is enabled and
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DS1254 data transfer to or from the timekeeping registers can proceed. The next 64 cycles will cause the phantom clock to either receive or transmit data on DQ0, depending on the level of the OE pin or the WE pin. Cycles to other locations outside the memory block can be interleaved with CE cycles without interrupting the pattern-recognition sequence or data-transfer sequence to the phantom clock.

PHANTOM CLOCK REGISTER INFORMATION

The phantom clock information is contained in eight registers of 8 bits, each of which is sequentially accessed one bit at a time after the 64-bit pattern-recognition sequence has been completed. When updating the phantom clock registers, each register must be handled in groups of 8 bits. Writing and reading individual bits within a register could produce erroneous results. These read/write registers are defined in Figure

Figure Phantom Clock Protocol Definition

NOTE THE PATTERN RECOGNITION IN HEX IS C5, 3A, A3, 5C, C5, 3A, A3, 5C. THE ODDS OF THIS PATTERN BEING ACCIDENTALLY DUPLICATED AND CAUSING INADVERTENT ENTRY TO THE PHANTOM CLOCK IS LESS THAN 1 IN THIS PATTERN IS SENT TO THE PHANTOM CLOCK LSB TO MSB
4 of 18

Figure Phantom Clock Register Definition

DS1254

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Datasheet ID: DS1254YB-100 647154