DS1225Y-200IND+

DS1225Y-200IND+ Datasheet

DS1225Y 64k Nonvolatile SRAM

Part	Datasheet
DS1225Y-200IND+	DS1225Y-200IND+ (pdf)

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• 10 years minimum data retention in the absence of external power • Data is automatically protected during power loss • Directly replaces 2k x 8 volatile static RAM or EEPROM • Unlimited write cycles • Low-power CMOS • JEDEC standard 28-pin DIP package • Read and write access times as fast as 150 ns • Full ±10% operating range • Optional industrial temperature range of -40°C to +85°C, designated IND DS1225Y 64k Nonvolatile SRAM PIN ASSIGNMENT A12 2 A0 10 DQ0 11 DQ1 12 DQ2 13 GND 14 VCC WE NC A8 A9 A11 OE A10 CE DQ7 DQ6 24-Pin ENCAPSULATED PACKAGE 720-mil EXTENDED PIN DESCRIPTION A0-A12 DQ0-DQ7 - Address Inputs - Data In/Data Out - Chip Enable - Write Enable OE VCC GND - Output Enable - Power +5V - Ground The DS1225Y 64k Nonvolatile SRAM is a 65,536-bit, fully static, nonvolatile RAM organized as 8192 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAM can be used in place of existing 8k x 8 SRAMs directly conforming to the popular bytewide 28-pin DIP standard. The DS1225Y also matches the pinout of the 2764 EPROM or the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing. 1 of 8 121907 READ MODE DS1225Y The DS1225Y executes a read cycle whenever WE Write Enable is inactive high and CE Chip Enable and OE Output Enable are active low . The unique address specified by the 13 address inputs A0-A12 defines which of the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC Access Time after the last address input signal is stable, providing that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data access must be measured from the later-occurring signal and the limiting parameter is either tCO for CE or tOE for OE rather than address access. WRITE MODE The DS1225Y executes a write cycle whenever the WE and CE signals are active low after address inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write cycle. The write cycle is terminated by the earlier rising edge of CE or WE All address inputs must be kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time tWR before another cycle can be initiated. The OE control signal should be kept inactive high during write cycles to avoid bus contention. However, if the output drivers are enabled CE and OE active then WE will disable the outputs in tODW from its falling edge. DATA RETENTION MODE The DS1225Y provides full functional capability for VCC greater than volts and write protects at nominal. Data is maintained in the absence of VCC without any additional support circuitry. The DS1225Y constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write protects itself, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls below approximately volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately volts, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds volts. ORDERING INFORMATION TEMPERATURE RANGE DS1225Y-150 0°C to +70°C DS1225Y-150+ 0°C to +70°C DS1225Y-150IND -40°C to +85°C DS1225Y-150IND+ -40°C to +85°C DS1225Y-170 0°C to +70°C DS1225Y-170+ 0°C to +70°C DS1225Y-200 0°C to +70°C DS1225Y-200+ 0°C to +70°C DS1225Y-200IND -40°C to +85°C DS1225Y-200IND+ -40°C to +85°C + Denotes lead Pb -free/RoHS-compliant product. SUPPLY TOLERANCE 5V  10% 5V  10% 5V  10% 5V  10% 5V  10% 5V  10% 5V  10% 5V  10% 5V  10% 5V  10% PIN/PACKAGE 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD SPEED GRADE 150ns 170ns 200ns PACKAGE INFORMATION For the latest package outline information and land patterns, go to PACKAGE TYPE PACKAGE CODE DOCUMENT NO. 28 EDIP MDT28+2 21-0245 7 of 8 Added package information table. 121907 Removed the DIP module package drawing and dimension table. DS1225Y PAGES CHANGED 7

PDF Datasheet Preview

• 10 years minimum data retention in the
absence of external power
• Data is automatically protected during power
loss
• Directly replaces 2k x 8 volatile static RAM
or EEPROM
• Unlimited write cycles
• Low-power CMOS
• JEDEC standard 28-pin DIP package
• Read and write access times as fast as 150 ns
• Full ±10% operating range
• Optional industrial temperature range of
-40°C to +85°C, designated IND

DS1225Y 64k Nonvolatile SRAM

PIN ASSIGNMENT

A12 2

A0 10

DQ0 11

DQ1 12

DQ2 13

GND 14

VCC WE NC A8 A9 A11 OE A10 CE DQ7 DQ6
24-Pin ENCAPSULATED PACKAGE 720-mil EXTENDED

PIN DESCRIPTION

A0-A12 DQ0-DQ7
- Address Inputs - Data In/Data Out
- Chip Enable
- Write Enable

OE VCC GND
- Output Enable - Power +5V - Ground

The DS1225Y 64k Nonvolatile SRAM is a 65,536-bit, fully static, nonvolatile RAM organized as 8192 words by 8 bits. Each NV SRAM has a self-contained lithium energy source and control circuitry which constantly monitors VCC for an out-of-tolerance condition. When such a condition occurs, the lithium energy source is automatically switched on and write protection is unconditionally enabled to prevent data corruption. The NV SRAM can be used in place of existing 8k x 8 SRAMs directly conforming to the popular bytewide 28-pin DIP standard. The DS1225Y also matches the pinout of the 2764 EPROM or the 2864 EEPROM, allowing direct substitution while enhancing performance. There is no limit on the number of write cycles that can be executed and no additional support circuitry is required for microprocessor interfacing.
1 of 8
121907

READ MODE

DS1225Y

The DS1225Y executes a read cycle whenever WE Write Enable is inactive high and CE Chip

Enable and OE Output Enable are active low . The unique address specified by the 13 address inputs A0-A12 defines which of the 8192 bytes of data is to be accessed. Valid data will be available to the eight data output drivers within tACC Access Time after the last address input signal is stable, providing
that CE and OE access times are also satisfied. If CE and OE access times are not satisfied, then data
access must be measured from the later-occurring signal and the limiting parameter is either tCO for CE
or tOE for OE rather than address access.

WRITE MODE

The DS1225Y executes a write cycle whenever the WE and CE signals are active low after address
inputs are stable. The later-occurring falling edge of CE or WE will determine the start of the write
cycle. The write cycle is terminated by the earlier rising edge of CE or WE All address inputs must be
kept valid throughout the write cycle. WE must return to the high state for a minimum recovery time
tWR before another cycle can be initiated. The OE control signal should be kept inactive high during write cycles to avoid bus contention. However, if the output drivers are enabled CE and OE active then

WE will disable the outputs in tODW from its falling edge.

DATA RETENTION MODE

The DS1225Y provides full functional capability for VCC greater than volts and write protects at nominal. Data is maintained in the absence of VCC without any additional support circuitry. The DS1225Y constantly monitors VCC. Should the supply voltage decay, the NV SRAM automatically write protects itself, all inputs become “don’t care,” and all outputs become high impedance. As VCC falls below approximately volts, a power switching circuit connects the lithium energy source to RAM to retain data. During power-up, when VCC rises above approximately volts, the power switching circuit connects external VCC to RAM and disconnects the lithium energy source. Normal RAM operation can resume after VCC exceeds volts.
ORDERING INFORMATION

TEMPERATURE RANGE

DS1225Y-150
0°C to +70°C

DS1225Y-150+
0°C to +70°C

DS1225Y-150IND
-40°C to +85°C

DS1225Y-150IND+
-40°C to +85°C

DS1225Y-170
0°C to +70°C

DS1225Y-170+
0°C to +70°C

DS1225Y-200
0°C to +70°C

DS1225Y-200+
0°C to +70°C

DS1225Y-200IND
-40°C to +85°C

DS1225Y-200IND+
-40°C to +85°C
+ Denotes lead Pb -free/RoHS-compliant product.

SUPPLY TOLERANCE
5V  10% 5V  10% 5V  10% 5V  10% 5V  10% 5V  10% 5V  10% 5V  10% 5V  10% 5V  10%

PIN/PACKAGE
28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD 28 / 720 EMOD

SPEED GRADE
150ns 170ns 200ns

PACKAGE INFORMATION

For the latest package outline information and land patterns, go to

PACKAGE TYPE PACKAGE CODE DOCUMENT NO.
28 EDIP

MDT28+2
21-0245
7 of 8

Added package information table.
121907

Removed the DIP module package drawing and dimension table.

DS1225Y

PAGES CHANGED 7

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived DS1225Y-200IND+ Datasheet file may be downloaded here without warranties.

Datasheet ID: DS1225Y-200IND+ 647153