MX29GL128FHXGI-90G

MX29GL128FHXGI-90G Datasheet

MX29GL128F

Part	Datasheet
MX29GL128FHXGI-90G	MX29GL128FHXGI-90G (pdf)

Related Parts	Information
MX29GL128FDT2I-90G	MX29GL128FDT2I-90G
MX29GL128FUT2I-90G	MX29GL128FUT2I-90G
MX29GL128FHXGI-70G	MX29GL128FHXGI-70G
MX29GL128FLXGI-90G	MX29GL128FLXGI-90G
MX29GL128FLXGI-70G	MX29GL128FLXGI-70G

PDF Datasheet Preview
MX29GL128F MX29GL128F DATASHEET P/N:PM1683 MX29GL128F Contents 5 PIN 6 PIN 7 BLOCK 8 BLOCK DIAGRAM 9 BLOCK 10 Table 1 SECTOR ARCHITECTURE 10 BUS 11 Table BUS 11 Table BUS 12 FUNCTIONAL OPERATION 13 READ 13 PAGE 13 WRITE 13 DEVICE 13 STANDBY 13 OUTPUT 14 BYTE/WORD 14 HARDWARE WRITE 14 ACCELERATED PROGRAMMING OPERATION 14 WRITE BUFFER PROGRAMMING 14 SECTOR PROTECT 15 AUTOMATIC SELECT BUS 15 SECTOR LOCK STATUS 15 READ SILICON ID MANUFACTURER 16 READ INDICATOR BIT Q7 FOR SECURITY 16 INHERENT DATA 16 COMMAND 16 LOW VCC WRITE 16 WRITE PULSE "GLITCH" 16 LOGICAL 16 POWER-UP 17 POWER-UP WRITE 17 POWER SUPPLY 17 COMMAND 18 READING THE MEMORY 18 AUTOMATIC PROGRAMMING OF THE MEMORY 18 ERASING THE MEMORY 19 SECTOR 19 P/N:PM1683 MX29GL128F CHIP 20 ERASE 21 SECTOR ERASE 21 PROGRAM 22 PROGRAM 22 BUFFER WRITE 22 AUTOMATIC SELECT 23 AUTOMATIC SELECT COMMAND 23 READ MANUFACTURER ID OR DEVICE 24 RESET 24 ADVANCED SECTOR 25 Figure Advance Sector Protection/Unprotection SPB Program 25 Lock 26 Figure Lock Register Program 26 Solid write non-volatile protection 27 Figure SPB Program 28 Solid Protection Bit Lock 29 Password Protection 29 Sector Protection Status 30 SECURITY SECTOR FLASH MEMORY 31 Factory Locked Security Sector Programmed and Protected at the 31 Customer Lockable Security Sector NOT Programmed or Protected at the 31 TABLE COMMAND 32 COMMON FLASH MEMORY INTERFACE CFI 35 QUERY COMMAND AND COMMAND FLASH MEMORY INTERFACE CFI MODE................................ 35 Table CFI mode Identification Data 35 Table CFI mode System Interface Data 35 Table CFI mode Device Geometry Data 36 Table CFI mode Primary Vendor-Specific Extended Query Data 37 ELECTRICAL 38 ABSOLUTE MAXIMUM STRESS 38 OPERATING TEMPERATURE AND 38 Maximum Negative Overshoot 38 Maximum Positive Overshoot 38 DC 39 SWITCHING TEST 40 SWITCHING TEST 40 AC 41 WRITE 43 Figure COMMAND WRITE 43 READ/RESET 44 Figure READ TIMING 44 P/N:PM1683 MX29GL128F Figure RESET# TIMING 45 ERASE/PROGRAM 46 P/N:PM1683 MX29GL128F SINGLE VOLTAGE 3V ONLY FLASH MEMORY GENERAL FEATURES • Power Supply Operation - to volt for read, erase, and program operations - MX29GL128F H/L VI/O=VCC=2.7V~3.6V, VI/O voltage must tight with VCC - MX29GL128F U/D VI/O=1.65V~3.6V for Input/Output • Byte/Word mode switchable - 16,777,216 x 8 / 8,388,608 x 16 • 64KW/128KB uniform sector architecture - 128 equal sectors • 16-byte/8-word page read buffer • 64-byte/32-word write buffer • Extra 128-word sector for security - Features factory locked and identifiable, and customer lockable • Advanced sector protection function Solid and Password Protect • Latch-up protected to 100mA from -1V to 1.5xVcc • Low Vcc write inhibit Vcc VLKO • Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash • Deep power down mode PERFORMANCE • High Performance - Fast access time - MX29GL128F H/L 70/90ns VCC=2.7~3.6V - MX29GL128F U/D 90/110ns VCC=2.7~3.6V, V I/O=1.65V to Vcc - Page access time - MX29GL128F H/L 25ns - MX29GL128F U/D 30ns - Fast program time 11us/word - Fast erase time 0.6s/sector • Low Power Consumption - Low active read current 20mA typical at 5MHz - Low standby current 30uA typical • Minimum 100,000 erase/program cycle • 20 years data retention SOFTWARE FEATURES • Program/Erase Suspend & Program/Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased - Suspends sector program operation to read data from another sector which is not being program • Status Reply - Data# Polling & Toggle bits provide detection of program and erase operation completion • Support Common Flash Interface CFI HARDWARE FEATURES • Ready/Busy# RY/BY# Output - Provides a hardware method of detecting program and erase operation completion • Hardware Reset# Input - Provides a hardware method to reset the internal state machine to read mode • WP#/ACC input pin - Hardware write protect pin/Provides accelerated program capability PACKAGE • 56-Pin TSOP • 56-Ball FBGA 7mm x 9mm • 64-Ball LFBGA 11mm x 13mm • All devices are RoHS Compliant P/N:PM1683 PIN CONFIGURATION 56 TSOP RESET# WP#/ACC RY/BY# MX29GL128F BYTE# Q15/A-1 VI/O 64 LFBGA VI/O BYTE# Q15/ RES- WP#/ VI/O P/N:PM1683 MX29GL128F 56 FBGA 7x9x1.2mm NC WP#/ACC WE# RESET# NC A18 RY/BY# A20 VI/O *1 Q12 Note G5 pin is NC on MX29GL128F H/L. Only support word mode for 56-FBGA. The DPBs are default erased to “1” when first shipped from factory. The default DPB state can be decided by the ordering choices. P/N:PM1683 MX29GL128F Temporary Un-protect Solid write protect bit USPB Temporary Un-protect Solid write Protect Bits are volatile. They are unique for each sector and can be individually modified. Software can temporarily unprotect write protect sectors despite of SPB's property when DPBs are cleared. While the USPB is set to “0” , the corresponding sector's SPB property is masked. Notes Upon power up, the USPBs are cleared all The USPBs can be set to “0” or cleared to “1” as often as needed. The hardware reset will reset USPB/DPB to their default values. However, users don’t need to clear all SPBs when writing a protect sector status of solid protect bit. They just use software to set corresponding USPB to 0, which guarantees that corresponding DPB status is clear, and original solid protect bit protected sectors can be temporary written. SPBLK should be cleared to modify USPB status. Figure SPB Program Algorithm SPB command set entry Program SPB Read Q7~Q0 Twice Wait 500 µs NO Q6 Toggle ? Q5 = 1 ? Read Q7~Q0 Twice Read Q7~Q0 Twice Q0= '1' Erase '0' Program Pass Q6 Toggle ? Program Fail Write Reset CMD SPB command set Exit Note SPB program/erase status polling flowchart check Q6 toggle, when Q6 stop toggle, the read status is 00H /01H 00H for program/ 01H for erase , otherwise the status is “fail” and “exit”. P/N:PM1683 MX29GL128F Solid Protection Bit Lock Bit The Solid Protection Bit Lock Bit SPBLK is assign to control all SPB status. It is a unique and volatile. When SPBLK=0 set , all SPBs are locked and can not be changed. When SPBLK=1 cleared , all SPBs are unlock and allows to be changed. There is no software command sequence requested to unlocks this bit, unless the device is in the password protection mode. To clear the SPB Lock Bit, just take the device through a hardware reset or a power-up cycle. In order to prevent modified, the SPB Lock Bit must be set SPBLK=0 after all SPBs are setting the desired status. Password Protection Method The security level of Password Protection Method is higher then the Solid protection mode. The 64 bit password is requested before modify SPB lock bit status. When device is under password protection mode, the SPB lock bit is set “0”, after a power-up cycle or Reset Command. A correct password is required for password Unlock command, to unlock the SPB lock bit. Await 2us is necessary to unlocked the device after valid password is given. After that, the SPB bits are allows to be changed. The Password Unlock command are issued slower then 2 us every time, to prevent hacker from trying all the 64-bit password combinations. There are a few steps to start password protection mode Set a 64-bit password for verification before entering the password protection mode. This verification is only allowed in password programming. Set the Password Protection Mode Lock Bit to”0” to activate the password protection mode. Once programmed, the programmed bit can not be erased and the device will remain permanently in password protection mode. The previous set 64-bit password can not be retrieved or programmed. All the commands to the password-protected address will also be disabled. All the combinations of the 64-bit password can be used as a password, and programming the password does not require special address. The password is defaulted to be all “1” when shipped from the factory. Under password program command, only "0" can be programmed. In order to prevent access, the Password Mode Locking Bit must be set after the Password is programmed and verified. To set the Password Mode Lock Bit will prevent this 64-bits password on the data bus to be read. Any modification is impossible then, and the password can not be checked anymore after the Password Mode Lock Bit is set. Entry command sequence will cause the read and write operation to be disabled for normal sector until this mode exits. Once sector under protected status, device will ignores the program/erase command, enable status polling and returns to read mode without contents change. The DPB, SPB,USPB and SPB lock bit status of each sector can be verified by issue status read commands. P/N:PM1683 MX29GL128F Sector Protection Status Table DPB clear set ORDERING INFORMATION PART NO. MX29GL128FHT2I-70G MX29GL128FLT2I-70G MX29GL128FHXFI-70G MX29GL128FLXFI-70G MX29GL128FHT2I-90G MX29GL128FLT2I-90G MX29GL128FHXFI-90G MX29GL128FLXFI-90G MX29GL128FHXGI-90G MX29GL128FLXGI-90G MX29GL128FUT2I-90G MX29GL128FDT2I-90G MX29GL128FUT2I-11G MX29GL128FDT2I-11G MX29GL128FUXFI-11G MX29GL128FDXFI-11G ACCESS TIME ns 70 90 110 MX29GL128F PACKAGE 56 Pin TSOP 56 Pin TSOP 64 LFBGA 64 LFBGA 56 Pin TSOP 56 Pin TSOP 64 LFBGA 64 LFBGA 56 FBGA 56 FBGA 56 Pin TSOP 56 Pin TSOP 56 Pin TSOP 56 Pin TSOP 64 LFBGA 64 LFBGA Remark P/N:PM1683 MX29GL128F PART NAME DESCRIPTION MX 29 GL 128 F H T2 I OPTION G RoHS compliant with Vcc 2.7V~3.6V SPEED 70 70ns 90 90ns 11 110ns TEMPERATURE RANGE I Industrial -40° C to 85° C PACKAGE T2 56-TSOP XF LFBGA 11mm x 13mm x 1.4mm, ball size, ball-pitch XG FBGA 7mm x 9mm x 1.2mm, ball size, ball-pitch PRODUCT TYPE Protection when WP#=VIL H VI/O=VCC=2.7 to 3.6V, Highest Address Sector Protected L VI/O=VCC=2.7 to 3.6V, Lowest Address Sector Protected U VI/O=1.65 to VCC, VCC=2.7 to 3.6V, Highest Address Sector Protected D VI/O=1.65 to VCC, VCC=2.7 to 3.6V, Lowest Address Sector Protected DENSITY & MODE 128 128Mb x8/x16 Architecture TYPE GL 3V Page Mode DEVICE 29:Flash P/N:PM1683 PACKAGE INFORMATION MX29GL128F P/N:PM1683 MX29GL128F P/N:PM1683 MX29GL128F P/N:PM1683 MX29GL128F Changed title from "Advanced Information" to "Preliminary" JUN/28/2011 Modified Figure Status Polling For Write Buffer Program for P15,57 Abort function Modified Total Write Buffer Time from 200us typ. to 120us typ. P64 ACC Total Write Buffer Time from 100us typ. to 70us typ. Modified standby current typ. from 50uA to 30uA P5,39 Added 56-Ball FBGA package information P5,7,65,66, JUL/14/2011 Modified Pin Configuration--56 FBGA OCT/12/2011 Modified Icr1 Ordering Information Modified Figure CE# Controlled Write Timing Waveform JUN/28/2012 Added VI/O Setup Time Added access time 70ns spec 64-LFBGA Ordering Information P65 Removed access time 90ns spec with VI/O Ordering Information P65 Added access time 70ns spec for Trc, Twc and Tcwc NOV/09/2012 Modified Figure PAGE READ TIMING WAVEFORM Added "Note Query data are always presented on the lowest P35 data output Q7~Q0 only, Q8~Q15 are Added 90ns spec for VI/O P5,41,66 APR/26/2013 Modified G5 pin for 56 FBGA Added MAX. Total Write Buffer Time 480us Modified Sector Protection Status Table P/N:PM1683 MX29GL128F Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright Macronix International Co., Ltd. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich io, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto if any are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at: MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 72

PDF Datasheet Preview

MX29GL128F

MX29GL128F DATASHEET

P/N:PM1683

MX29GL128F

Contents
5 PIN 6 PIN 7 BLOCK 8 BLOCK DIAGRAM 9 BLOCK 10

Table 1 SECTOR ARCHITECTURE 10 BUS 11

Table BUS 11 Table BUS 12 FUNCTIONAL OPERATION 13 READ 13 PAGE 13 WRITE 13 DEVICE 13 STANDBY 13 OUTPUT 14 BYTE/WORD 14 HARDWARE WRITE 14 ACCELERATED PROGRAMMING OPERATION 14 WRITE BUFFER PROGRAMMING 14 SECTOR PROTECT 15 AUTOMATIC SELECT BUS 15 SECTOR LOCK STATUS 15 READ SILICON ID MANUFACTURER 16 READ INDICATOR BIT Q7 FOR SECURITY 16 INHERENT DATA 16 COMMAND 16 LOW VCC WRITE 16 WRITE PULSE "GLITCH" 16 LOGICAL 16 POWER-UP 17 POWER-UP WRITE 17 POWER SUPPLY 17 COMMAND 18 READING THE MEMORY 18 AUTOMATIC PROGRAMMING OF THE MEMORY 18 ERASING THE MEMORY 19 SECTOR 19

P/N:PM1683

MX29GL128F

CHIP 20 ERASE 21 SECTOR ERASE 21 PROGRAM 22 PROGRAM 22 BUFFER WRITE 22 AUTOMATIC SELECT 23 AUTOMATIC SELECT COMMAND 23 READ MANUFACTURER ID OR DEVICE 24 RESET 24 ADVANCED SECTOR 25

Figure Advance Sector Protection/Unprotection SPB Program 25 Lock 26 Figure Lock Register Program 26 Solid write non-volatile protection 27 Figure SPB Program 28 Solid Protection Bit Lock 29 Password Protection 29 Sector Protection Status 30 SECURITY SECTOR FLASH MEMORY 31 Factory Locked Security Sector Programmed and Protected at the 31 Customer Lockable Security Sector NOT Programmed or Protected at the 31 TABLE COMMAND 32 COMMON FLASH MEMORY INTERFACE CFI 35 QUERY COMMAND AND COMMAND FLASH MEMORY INTERFACE CFI MODE................................ 35 Table CFI mode Identification Data 35 Table CFI mode System Interface Data 35 Table CFI mode Device Geometry Data 36 Table CFI mode Primary Vendor-Specific Extended Query Data 37 ELECTRICAL 38 ABSOLUTE MAXIMUM STRESS 38 OPERATING TEMPERATURE AND 38 Maximum Negative Overshoot 38 Maximum Positive Overshoot 38 DC 39 SWITCHING TEST 40 SWITCHING TEST 40 AC 41 WRITE 43 Figure COMMAND WRITE 43 READ/RESET 44 Figure READ TIMING 44

P/N:PM1683

MX29GL128F

Figure RESET# TIMING 45 ERASE/PROGRAM 46
P/N:PM1683

MX29GL128F

SINGLE VOLTAGE 3V ONLY FLASH MEMORY

GENERAL FEATURES
• Power Supply Operation
- to volt for read, erase, and program operations - MX29GL128F H/L VI/O=VCC=2.7V~3.6V, VI/O voltage must tight with VCC - MX29GL128F U/D VI/O=1.65V~3.6V for Input/Output
• Byte/Word mode switchable - 16,777,216 x 8 / 8,388,608 x 16
• 64KW/128KB uniform sector architecture - 128 equal sectors
• 16-byte/8-word page read buffer
• 64-byte/32-word write buffer
• Extra 128-word sector for security - Features factory locked and identifiable, and customer lockable
• Advanced sector protection function Solid and Password Protect
• Latch-up protected to 100mA from -1V to 1.5xVcc
• Low Vcc write inhibit Vcc VLKO
• Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash
• Deep power down mode

PERFORMANCE
• High Performance
- Fast access time - MX29GL128F H/L 70/90ns VCC=2.7~3.6V
- MX29GL128F U/D 90/110ns VCC=2.7~3.6V, V I/O=1.65V to Vcc - Page access time - MX29GL128F H/L 25ns
- MX29GL128F U/D 30ns - Fast program time 11us/word - Fast erase time 0.6s/sector
• Low Power Consumption - Low active read current 20mA typical at 5MHz - Low standby current 30uA typical
• Minimum 100,000 erase/program cycle
• 20 years data retention

SOFTWARE FEATURES
• Program/Erase Suspend & Program/Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being erased - Suspends sector program operation to read data from another sector which is not being program
• Status Reply - Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface CFI

HARDWARE FEATURES
• Ready/Busy# RY/BY# Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset# Input
- Provides a hardware method to reset the internal state machine to read mode
• WP#/ACC input pin
- Hardware write protect pin/Provides accelerated program capability

PACKAGE
• 56-Pin TSOP
• 56-Ball FBGA 7mm x 9mm
• 64-Ball LFBGA 11mm x 13mm
• All devices are RoHS Compliant

P/N:PM1683

PIN CONFIGURATION
56 TSOP

RESET#

WP#/ACC

RY/BY#

MX29GL128F

BYTE#

Q15/A-1

VI/O
64 LFBGA

VI/O

BYTE#

Q15/

RES-

WP#/

VI/O

P/N:PM1683

MX29GL128F
56 FBGA 7x9x1.2mm

NC WP#/ACC WE#

RESET# NC

A18 RY/BY# A20

VI/O *1 Q12

Note G5 pin is NC on MX29GL128F H/L. Only support word mode for 56-FBGA.
The DPBs are default erased to “1” when first shipped from factory. The default DPB state can be decided by the ordering choices.

P/N:PM1683

MX29GL128F

Temporary Un-protect Solid write protect bit USPB

Temporary Un-protect Solid write Protect Bits are volatile. They are unique for each sector and can be individually modified. Software can temporarily unprotect write protect sectors despite of SPB's property when DPBs are cleared. While the USPB is set to “0” , the corresponding sector's SPB property is masked.

Notes Upon power up, the USPBs are cleared all The USPBs can be set to “0” or cleared to “1” as often as
needed. The hardware reset will reset USPB/DPB to their default values. However, users don’t need to clear all SPBs when writing a protect sector status of solid protect bit. They just
use software to set corresponding USPB to 0, which guarantees that corresponding DPB status is clear, and original solid protect bit protected sectors can be temporary written. SPBLK should be cleared to modify USPB status.

Figure SPB Program Algorithm

SPB command set entry

Program SPB

Read Q7~Q0 Twice

Wait 500 µs

NO Q6 Toggle ?

Q5 = 1 ?

Read Q7~Q0 Twice

Read Q7~Q0 Twice

Q0= '1' Erase
'0' Program

Pass

Q6 Toggle ?

Program Fail Write Reset CMD

SPB command set Exit

Note SPB program/erase status polling flowchart check Q6 toggle, when Q6 stop toggle, the read status is 00H /01H 00H for program/ 01H for erase , otherwise the status is “fail” and “exit”.

P/N:PM1683

MX29GL128F

Solid Protection Bit Lock Bit

The Solid Protection Bit Lock Bit SPBLK is assign to control all SPB status. It is a unique and volatile. When SPBLK=0 set , all SPBs are locked and can not be changed. When SPBLK=1 cleared , all SPBs are unlock and allows to be changed.

There is no software command sequence requested to unlocks this bit, unless the device is in the password protection mode. To clear the SPB Lock Bit, just take the device through a hardware reset or a power-up cycle. In order to prevent modified, the SPB Lock Bit must be set SPBLK=0 after all SPBs are setting the desired status.

Password Protection Method

The security level of Password Protection Method is higher then the Solid protection mode. The 64 bit password is requested before modify SPB lock bit status. When device is under password protection mode, the SPB lock bit is set “0”, after a power-up cycle or Reset Command.

A correct password is required for password Unlock command, to unlock the SPB lock bit. Await 2us is necessary to unlocked the device after valid password is given. After that, the SPB bits are allows to be changed. The Password Unlock command are issued slower then 2 us every time, to prevent hacker from trying all the 64-bit password combinations.

There are a few steps to start password protection mode Set a 64-bit password for verification before entering the password protection mode. This verification is only
allowed in password programming. Set the Password Protection Mode Lock Bit to”0” to activate the password protection mode.

Once programmed, the programmed bit can not be erased and the device will remain permanently in password protection mode. The previous set 64-bit password can not be retrieved or programmed. All the commands to the password-protected address will also be disabled.

All the combinations of the 64-bit password can be used as a password, and programming the password does not require special address. The password is defaulted to be all “1” when shipped from the factory. Under password program command, only "0" can be programmed. In order to prevent access, the Password Mode Locking Bit must be set after the Password is programmed and verified. To set the Password Mode Lock Bit will prevent this 64-bits password on the data bus to be read. Any modification is impossible then, and the password can not be checked anymore after the Password Mode Lock Bit is set.

Entry command sequence will cause the read and write operation to be disabled for normal sector until this mode exits. Once sector under protected status, device will ignores the program/erase command, enable status polling and returns to read mode without contents change. The DPB, SPB,USPB and SPB lock bit status of each sector can be verified by issue status read commands.

P/N:PM1683

MX29GL128F

Sector Protection Status Table

DPB clear set
ORDERING INFORMATION PART NO. MX29GL128FHT2I-70G MX29GL128FLT2I-70G MX29GL128FHXFI-70G MX29GL128FLXFI-70G MX29GL128FHT2I-90G MX29GL128FLT2I-90G MX29GL128FHXFI-90G MX29GL128FLXFI-90G MX29GL128FHXGI-90G MX29GL128FLXGI-90G MX29GL128FUT2I-90G MX29GL128FDT2I-90G MX29GL128FUT2I-11G MX29GL128FDT2I-11G MX29GL128FUXFI-11G MX29GL128FDXFI-11G

ACCESS TIME ns 70 90 110

MX29GL128F

PACKAGE 56 Pin TSOP 56 Pin TSOP
64 LFBGA 64 LFBGA 56 Pin TSOP 56 Pin TSOP 64 LFBGA 64 LFBGA 56 FBGA 56 FBGA 56 Pin TSOP 56 Pin TSOP 56 Pin TSOP 56 Pin TSOP 64 LFBGA 64 LFBGA

Remark

P/N:PM1683

MX29GL128F

PART NAME DESCRIPTION MX 29 GL 128 F H T2 I

OPTION G RoHS compliant with Vcc 2.7V~3.6V

SPEED 70 70ns
90 90ns
11 110ns

TEMPERATURE RANGE I Industrial -40° C to 85° C

PACKAGE T2 56-TSOP XF LFBGA 11mm x 13mm x 1.4mm, ball size, ball-pitch XG FBGA 7mm x 9mm x 1.2mm, ball size, ball-pitch

PRODUCT TYPE Protection when WP#=VIL H VI/O=VCC=2.7 to 3.6V, Highest Address Sector Protected L VI/O=VCC=2.7 to 3.6V, Lowest Address Sector Protected U VI/O=1.65 to VCC, VCC=2.7 to 3.6V, Highest Address Sector Protected D VI/O=1.65 to VCC, VCC=2.7 to 3.6V, Lowest Address Sector Protected

DENSITY & MODE 128 128Mb x8/x16 Architecture

TYPE GL 3V Page Mode

DEVICE 29:Flash

P/N:PM1683

PACKAGE INFORMATION

MX29GL128F

P/N:PM1683

MX29GL128F

P/N:PM1683

MX29GL128F

P/N:PM1683

MX29GL128F

Changed title from "Advanced Information" to "Preliminary"

JUN/28/2011

Modified Figure Status Polling For Write Buffer Program for P15,57

Abort function

Modified Total Write Buffer Time from 200us typ. to 120us typ. P64

ACC Total Write Buffer Time from 100us typ. to 70us typ.

Modified standby current typ. from 50uA to 30uA

P5,39

Added 56-Ball FBGA package information

P5,7,65,66, JUL/14/2011

Modified Pin Configuration--56 FBGA

OCT/12/2011

Modified Icr1
Ordering Information

Modified Figure CE# Controlled Write Timing Waveform

JUN/28/2012

Added VI/O Setup Time
Added access time 70ns spec 64-LFBGA Ordering Information P65
Removed access time 90ns spec with VI/O Ordering Information P65

Added access time 70ns spec for Trc, Twc and Tcwc

NOV/09/2012

Modified Figure PAGE READ TIMING WAVEFORM

Added "Note Query data are always presented on the lowest P35
data output Q7~Q0 only, Q8~Q15 are

Added 90ns spec for VI/O

P5,41,66 APR/26/2013

Modified G5 pin for 56 FBGA

Added MAX. Total Write Buffer Time 480us

Modified Sector Protection Status Table

P/N:PM1683

MX29GL128F

Except for customized products which has been expressly identified in the applicable agreement, Macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. In the event Macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said Macronix's product qualified for its actual use in accordance with the applicable laws and regulations and Macronix as well as it’s suppliers and/or distributors shall be released from any and all liability arisen therefrom. Copyright Macronix International Co., Ltd. All rights reserved, including the trademarks and tradename thereof, such as Macronix, MXIC, MXIC Logo, MX Logo, Integrated Solutions Provider, NBit, Nbit, NBiit, Macronix NBit, eLiteFlash, HybridNVM, HybridFlash, XtraROM, Phines, KH Logo, BE-SONOS, KSMC, Kingtech, MXSMIO, Macronix vEE, Macronix MAP, Rich io, Rich Book, Rich TV, and FitCAM. The names and brands of third party referred thereto if any are for identification purposes only. For the contact and order information, please visit Macronix’s Web site at:

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 72

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MX29GL128FHXGI-90G Datasheet file may be downloaded here without warranties.

Datasheet ID: MX29GL128FHXGI-90G 646959