MX29GL128EHT2I-90G

MX29GL128EHT2I-90G Datasheet

MX29GL128E

Part	Datasheet
MX29GL128EHT2I-90G	MX29GL128EHT2I-90G (pdf)

Related Parts	Information
MX29GL128EHXFI-90G	MX29GL128EHXFI-90G
MX29GL128ELXFI-90G	MX29GL128ELXFI-90G
MX29GL128ELT2I-90G	MX29GL128ELT2I-90G

PDF Datasheet Preview
MX29GL128E MX29GL128E DATASHEET P/N:PM1500 MX29GL128E SINGLE VOLTAGE 3V ONLY FLASH MEMORY GENERAL FEATURES • Power Supply Operation - to volt for read, erase, and program operations - MX29GL128E H/L VI/O=VCC=2.7V~3.6V, VI/O voltage must tight with VCC - MX29GL128E U/D VI/O=1.65V~3.6V for Input/Output • Byte/Word mode switchable - 16,777,216 x 8 / 8,388,608 x 16 • 64KW/128KB uniform sector architecture - 128 equal sectors • 16-byte/8-word page read buffer • 64-byte/32-word write buffer • Extra 128-word sector for security - Features factory locked and identifiable, and customer lockable • Advanced sector protection function Solid and Password Protect • Latch-up protected to 100mA from -1V to 1.5xVcc • Low Vcc write inhibit Vcc VLKO • Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash • Deep power down mode PERFORMANCE • High Performance - Fast access time - MX29GL128E H/L 90ns VCC=2.7~3.6V - MX29GL128E U/D 110ns VCC=2.7~3.6V, V I/O=1.65V to Vcc - Page access time - MX29GL128E H/L 25ns - MX29GL128E U/D 30ns - Fast program time 11us/word - Fast erase time 0.6s/sector • Low Power Consumption - Low active read current 30mA typical at 5MHz - Low standby current 30uA typical • Typical 100,000 erase/program cycle • 20 years data retention SOFTWARE FEATURES • Program/Erase Suspend & Program/Erase Resume - Suspends sector erase operation to read data from or program data to another sector which is not being erased - Suspends sector program operation to read data from another sector which is not being program • Status Reply - Data# Polling & Toggle bits provide detection of program and erase operation completion • Support Common Flash Interface CFI HARDWARE FEATURES • Ready/Busy# RY/BY# Output - Provides a hardware method of detecting program and erase operation completion • Hardware Reset# Input - Provides a hardware method to reset the internal state machine to read mode • WP#/ACC input pin - Hardware write protect pin/Provides accelerated program capability PACKAGE • 56-Pin TSOP • 64-Ball FBGA 10mm x 13mm • 64-Ball LFBGA 11mm x 13mm • 70-Pin SSOP • All devices are RoHS Compliant P/N:PM1500 PIN CONFIGURATION 56 TSOP RESET# WP#/ACC RY/BY# MX29GL128E BYTE# Q15/A-1 VI/O 64 FBGA/64 LFBGA BYTE# Q15/ RES- WP#/ P/N:PM1500 MX29GL128E 70 SSOP BYTE# WP#/ACC RESET# Q15/A-1 PIN DESCRIPTION When the parts are first shipped, the SPBs are cleared erased to “1” and upon power up or reset, the DPBs can be set or cleared depending upon the ordering option chosen. P/N:PM1500 MX29GL128E Temporary Un-protect Solid write protect bit USPB Temporary Un-protect Solid write Protect Bits are volatile and unique for each sector and can be individually modified. By issuing the USPB Set or Clear command sequences, the USPBs are set programmed to “0” or cleared erased to “1” , thus mask each sector's solid write protect bit property. This feature allows software to temp unprotect write protect sectors despite of SPB's property when DPBs are cleared. Notes The USPBs can be set programmed to “0” or cleared erased to “1” as often as needed. The USPBs are cleared all 1s upon power up. Hardware reset won”t change USPBs/DPBs status. The sectors SPBs would be in effective state after power up is chosen. However, if there is a need to write a solid protect bit protect sector status, user don't have to clear all SPB bits. They just use software to set corresponding USPB to 0, which guarantees that corresponding DPB status is clear, and original solid protect bit protected sectors can be temporary written. SPBLK should be cleared to modify USPB status. SPB Program Algorithm : SPB command set entry Program SPB Read Q7~Q0 Twice NO Wait 500 Q6 Toggle ? Q5 = 1 ? YES Read Q7~Q0 Twice Read Q7~Q0 Twice Q0= '1' Erase '0' Program YES Pass Q6 Toggle ? YES Program Fail Write Reset CMD SPB command set Exit Note SPB program/ erase status polling flowchart check Q6 toggle, when Q6 stop toggle, the read status is 00H /01H 00H for program/ 01H for erase , otherwise the status is “fail” and “exit”. P/N:PM1500 MX29GL128E Solid Protection Bit Lock Bit The Solid Protection Bit Lock Bit SPB is assign to control all SPB status. It is a unique and volatile. When SPB=0 set , all SPBs are locked and can not be changed. When SPB=1 cleared , all SPBs are unlock and allows to be changed. There is no software command sequence requested to unlocks this bit, unless the device is in the password protection mode. To clear the SPB lock bit, just take the device through a hardware reset or a power-up cycle. In order to prevent moified, the SPB Lock Bit must be set SPB=0 after all SPBs are setting the desired status. Password Protection Method The security level of Password Protection Method is higher then the Solid protection mode. The 64 bit password is requested before modify SPB lock bit status. When device is under password protection mode, the SPB lock bit is set “0”, after a power-up cycle or Reset Command. A correct password is required for password Unlock command, to unlock the SPB lock bit. Await 2us is necessary to unlocked the device after valid password is given. After that, the SPB bits are allows to be changed. The Password Unlock command are issued slower then 2 us every time,. to prevent hacker from trying all the 64-bit password combinations. The password is all “1”s when shipped from the factory, it is only capable to programming "0"s under password program command. All 64-bit password combinations are valid as a password. No special address is required for programming the password. In order to prevent access, the Password Mode Locking Bit must be set after the Password is programmed and verified. Once the Password Mode Lock Bit is set, prevents reading 64-bits password on the data bus and any future modification. There is no means to verify what the password is after it is set. Entry command sequence will cause the read and write operation to be disabled for normal sector until this mode exits. Once sector under protected status, device will ignores the program/erase command, enable status polling and returns to read mode without contents change. The DPB, SPB,USPB and SPB lock bit status of each sector can be verified by issue status read commands. P/N:PM1500 MX29GL128E Sector Protection Status Table Protection Bit Status DPB SPBLK SPB USPB clear clear clear clear ORDERING INFORMATION PART NO. MX29GL128EHMC-90G * MX29GL128EHXFI-90G MX29GL128ELXFI-90G MX29GL128EHXCI-90G MX29GL128ELXCI-90G MX29GL128EHT2I-90G MX29GL128ELT2I-90G MX29GL128EUXFI-11G MX29GL128EDXFI-11G MX29GL128EUT2I-11G MX29GL128EDT2I-11G ACCESS TIME ns 90 110 Note 70-pin SSOP only for Pachinko Socket. MX29GL128E PACKAGE 70 Pin SSOP 64 LFBGA 64 LFBGA 64 FBGA 64 FBGA 56 Pin TSOP 56 Pin TSOP 64 LFBGA 64 LFBGA 56 Pin TSOP 56 Pin TSOP Remark VI/O=VCC VI/O=VCC VI/O=VCC VI/O=VCC VI/O=VCC VI/O=VCC VI/O=VCC VI/O=1.65 to VCC VI/O=1.65 to VCC VI/O=1.65 to VCC VI/O=1.65 to VCC P/N:PM1500 MX29GL128E PART NAME DESCRIPTION MX 29 GL 128 E H T2 I OPTION G RoHS compliant with Vcc 2.7V~3.6V SPEED 90 90ns 11 110ns TEMPERATURE RANGE I Industrial -40° C to 85° C Commercial 0° C to 70° C PACKAGE T2 56-TSOP M 70SSOP XF LFBGA 11mm x 13mm XC FBGA 10mm x 13mm PRODUCT TYPE Protection when WP#=VIL H VI/O=VCC=2.7 to 3.6V, Highest Address Sector Protected L VI/O=VCC=2.7 to 3.6V, Lowest Address Sector Protected U VI/O=1.65 to VCC, VCC=2.7 to 3.6V, Highest Address Sector Protected D VI/O=1.65 to VCC, VCC=2.7 to 3.6V, Lowest Address Sector Protected DENSITY & MODE 128 128Mb x8/x16 Architecture TYPE GL 3V Page Mode DEVICE 29:Flash P/N:PM1500 PACKAGE INFORMATION MX29GL128E P/N:PM1500 MX29GL128E P/N:PM1500 MX29GL128E P/N:PM1500 MX29GL128E P/N:PM1500 MX29GL128E Added overshoot & undershoot specifications. Removed "Preliminary". Changed data retention from 10 years to 20 years. P2,61 Modified Tdf max. = 20ns. Added 1.8V VI/O information. P2,37,40 P64,65 Modified Tsrw min. = 35ns. Added Icr2 parameter and "status Polling for write buffer program" P38,56 flowchart.

PDF Datasheet Preview

MX29GL128E

MX29GL128E DATASHEET

P/N:PM1500

MX29GL128E

SINGLE VOLTAGE 3V ONLY FLASH MEMORY

GENERAL FEATURES
• Power Supply Operation
- to volt for read, erase, and program operations - MX29GL128E H/L VI/O=VCC=2.7V~3.6V, VI/O voltage must tight with VCC - MX29GL128E U/D VI/O=1.65V~3.6V for Input/Output
• Byte/Word mode switchable - 16,777,216 x 8 / 8,388,608 x 16
• 64KW/128KB uniform sector architecture - 128 equal sectors
• 16-byte/8-word page read buffer
• 64-byte/32-word write buffer
• Extra 128-word sector for security - Features factory locked and identifiable, and customer lockable
• Advanced sector protection function Solid and Password Protect
• Latch-up protected to 100mA from -1V to 1.5xVcc
• Low Vcc write inhibit Vcc VLKO
• Compatible with JEDEC standard - Pinout and software compatible to single power supply Flash
• Deep power down mode

PERFORMANCE
• High Performance
- Fast access time - MX29GL128E H/L 90ns VCC=2.7~3.6V - MX29GL128E U/D 110ns VCC=2.7~3.6V, V I/O=1.65V to Vcc
- Page access time - MX29GL128E H/L 25ns - MX29GL128E U/D 30ns
- Fast program time 11us/word - Fast erase time 0.6s/sector
• Low Power Consumption - Low active read current 30mA typical at 5MHz - Low standby current 30uA typical
• Typical 100,000 erase/program cycle
• 20 years data retention

SOFTWARE FEATURES
• Program/Erase Suspend & Program/Erase Resume
- Suspends sector erase operation to read data from or program data to another sector which is not being erased - Suspends sector program operation to read data from another sector which is not being program
• Status Reply - Data# Polling & Toggle bits provide detection of program and erase operation completion
• Support Common Flash Interface CFI

HARDWARE FEATURES
• Ready/Busy# RY/BY# Output
- Provides a hardware method of detecting program and erase operation completion
• Hardware Reset# Input
- Provides a hardware method to reset the internal state machine to read mode
• WP#/ACC input pin
- Hardware write protect pin/Provides accelerated program capability

PACKAGE
• 56-Pin TSOP
• 64-Ball FBGA 10mm x 13mm
• 64-Ball LFBGA 11mm x 13mm
• 70-Pin SSOP
• All devices are RoHS Compliant

P/N:PM1500

PIN CONFIGURATION
56 TSOP

RESET#

WP#/ACC

RY/BY#

MX29GL128E

BYTE#

Q15/A-1

VI/O
64 FBGA/64 LFBGA

BYTE#

Q15/

RES-

WP#/

P/N:PM1500

MX29GL128E
70 SSOP

BYTE#

WP#/ACC

RESET#

Q15/A-1

PIN DESCRIPTION
When the parts are first shipped, the SPBs are cleared erased to “1” and upon power up or reset, the DPBs can be set or cleared depending upon the ordering option chosen.

P/N:PM1500

MX29GL128E

Temporary Un-protect Solid write protect bit USPB Temporary Un-protect Solid write Protect Bits are volatile and unique for each sector and can be individually modified. By issuing the USPB Set or Clear command sequences, the USPBs are set programmed to “0” or cleared erased to “1” , thus mask each sector's solid write protect bit property. This feature allows software to temp unprotect write protect sectors despite of SPB's property when DPBs are cleared.

Notes The USPBs can be set programmed to “0” or cleared erased to “1” as often as needed. The USPBs are
cleared all 1s upon power up. Hardware reset won”t change USPBs/DPBs status. The sectors SPBs would be in effective state after power up is chosen. However, if there is a need to write a solid protect bit protect sector status, user don't have to clear all SPB bits. They just use software to set corresponding USPB to 0, which guarantees that corresponding DPB status is clear, and original solid protect bit protected sectors can be temporary written. SPBLK should be cleared to modify USPB status.

SPB Program Algorithm :

SPB command set entry

Program SPB

Read Q7~Q0 Twice

NO Wait 500

Q6 Toggle ?

Q5 = 1 ?

YES Read Q7~Q0

Twice

Read Q7~Q0 Twice

Q0= '1' Erase '0' Program

YES Pass

Q6 Toggle ? YES

Program Fail Write Reset CMD

SPB command set Exit

Note SPB program/ erase status polling flowchart check Q6 toggle, when Q6 stop toggle, the read status is 00H /01H 00H for program/ 01H for erase , otherwise the status is “fail” and “exit”.

P/N:PM1500

MX29GL128E

Solid Protection Bit Lock Bit

The Solid Protection Bit Lock Bit SPB is assign to control all SPB status. It is a unique and volatile. When SPB=0 set , all SPBs are locked and can not be changed. When SPB=1 cleared , all SPBs are unlock and allows to be changed.

There is no software command sequence requested to unlocks this bit, unless the device is in the password protection mode. To clear the SPB lock bit, just take the device through a hardware reset or a power-up cycle. In order to prevent moified, the SPB Lock Bit must be set SPB=0 after all SPBs are setting the desired status.

Password Protection Method

The security level of Password Protection Method is higher then the Solid protection mode. The 64 bit password is requested before modify SPB lock bit status. When device is under password protection mode, the SPB lock bit is set “0”, after a power-up cycle or Reset Command.

A correct password is required for password Unlock command, to unlock the SPB lock bit. Await 2us is necessary to unlocked the device after valid password is given. After that, the SPB bits are allows to be changed. The Password Unlock command are issued slower then 2 us every time,. to prevent hacker from trying all the 64-bit password combinations.

The password is all “1”s when shipped from the factory, it is only capable to programming "0"s under password program command. All 64-bit password combinations are valid as a password. No special address is required for programming the password. In order to prevent access, the Password Mode Locking Bit must be set after the Password is programmed and verified. Once the Password Mode Lock Bit is set, prevents reading 64-bits password on the data bus and any future modification. There is no means to verify what the password is after it is set.

Entry command sequence will cause the read and write operation to be disabled for normal sector until this mode exits. Once sector under protected status, device will ignores the program/erase command, enable status polling and returns to read mode without contents change. The DPB, SPB,USPB and SPB lock bit status of each sector can be verified by issue status read commands.

P/N:PM1500

MX29GL128E

Sector Protection Status Table

Protection Bit Status

DPB SPBLK SPB USPB
clear
clear
clear
clear
ORDERING INFORMATION

PART NO. MX29GL128EHMC-90G * MX29GL128EHXFI-90G MX29GL128ELXFI-90G MX29GL128EHXCI-90G MX29GL128ELXCI-90G MX29GL128EHT2I-90G MX29GL128ELT2I-90G MX29GL128EUXFI-11G MX29GL128EDXFI-11G MX29GL128EUT2I-11G MX29GL128EDT2I-11G

ACCESS TIME ns 90 110

Note 70-pin SSOP only for Pachinko Socket.

MX29GL128E

PACKAGE 70 Pin SSOP
64 LFBGA 64 LFBGA 64 FBGA 64 FBGA 56 Pin TSOP 56 Pin TSOP 64 LFBGA 64 LFBGA 56 Pin TSOP 56 Pin TSOP

Remark VI/O=VCC VI/O=VCC VI/O=VCC VI/O=VCC VI/O=VCC VI/O=VCC VI/O=VCC VI/O=1.65 to VCC VI/O=1.65 to VCC VI/O=1.65 to VCC VI/O=1.65 to VCC

P/N:PM1500

MX29GL128E

PART NAME DESCRIPTION MX 29 GL 128 E H T2 I

OPTION G RoHS compliant with Vcc 2.7V~3.6V

SPEED 90 90ns 11 110ns

TEMPERATURE RANGE I Industrial -40° C to 85° C Commercial 0° C to 70° C

PACKAGE T2 56-TSOP M 70SSOP XF LFBGA 11mm x 13mm XC FBGA 10mm x 13mm

PRODUCT TYPE Protection when WP#=VIL H VI/O=VCC=2.7 to 3.6V, Highest Address Sector Protected L VI/O=VCC=2.7 to 3.6V, Lowest Address Sector Protected U VI/O=1.65 to VCC, VCC=2.7 to 3.6V, Highest Address Sector Protected D VI/O=1.65 to VCC, VCC=2.7 to 3.6V, Lowest Address Sector Protected

DENSITY & MODE 128 128Mb x8/x16 Architecture

TYPE GL 3V Page Mode

DEVICE 29:Flash

P/N:PM1500

PACKAGE INFORMATION

MX29GL128E

P/N:PM1500

MX29GL128E

P/N:PM1500

MX29GL128E

P/N:PM1500

MX29GL128E

P/N:PM1500

MX29GL128E

Added overshoot & undershoot specifications.

Removed "Preliminary".

Changed data retention from 10 years to 20 years.

P2,61

Modified Tdf max. = 20ns.

Added 1.8V VI/O information.

P2,37,40

P64,65

Modified Tsrw min. = 35ns.

Added Icr2 parameter and "status Polling for write buffer program" P38,56
flowchart.

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived MX29GL128EHT2I-90G Datasheet file may be downloaded here without warranties.

Datasheet ID: MX29GL128EHT2I-90G 646958