MX25U12835FZNI-08G

MX25U12835FZNI-08G Datasheet

MX25U12835F

Part	Datasheet
MX25U12835FZNI-08G	MX25U12835FZNI-08G (pdf)

Related Parts	Information
MX25U12835FZNI-10G	MX25U12835FZNI-10G
MX25U12835FMI-10G	MX25U12835FMI-10G
MX25U12835FZ2I-10G	MX25U12835FZ2I-10G

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MX25U12835F MX25U12835F DATASHEET P/N PM1728 MX25U12835F Contents 4 GENERAL 6 Table Additional Feature PIN CONFIGURATIONS 7 PIN 7 BLOCK 8 DATA 9 Table Protected Area Table 4K-bit Secured OTP 11 Memory 12 Table Memory DEVICE 13 Quad Peripheral Interface QPI Read 15 COMMAND 16 Table Command Write Enable 20 Write Disable 21 Read Identification 22 Release from Deep Power-down RDP , Read Electronic Signature 23 Read Electronic Manufacturer ID & Device ID 25 QPI ID Read 26 Table ID Definitions Read Status Register 27 Read Configuration Register 28 Write Status Register 33 Table Protection Read Data Bytes 37 Read Data Bytes at Higher Speed 38 2 x I/O Read Mode 40 4 x I/O Read Mode 41 Burst 44 Performance Enhance 45 Performance Enhance Mode Reset 48 Sector Erase 49 Block Erase 50 Block Erase 51 Chip Erase 52 Page Program 53 4 x I/O Page Program 55 Deep Power-down 56 Enter Secured OTP 57 Exit Secured OTP 57 P/N PM1728 MX25U12835F Read Security Register 57 Table Security Register Write Security Register 58 Write Protection Selection 59 Single Block Lock/Unlock Protection 62 Read Block Lock Status 64 Gang Block Lock/Unlock 64 Program/ Erase Suspend/ 65 Erase 65 Program 65 67 No Operation 67 Software Reset-Enable RSTEN and Reset 67 Read SFDP Mode 69 P/N PM1728 MX25U12835F 1.8V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM SERIAL MULTI I/O FLASH MEMORY GENERAL • Serial Peripheral Interface compatible -- Mode 0 and Mode 3 • 134,217,728 x 1 bit structure or 67,108,864 x 2 bits two I/O mode structure or 33,554,432 x 4 bits four I/O mode structure • Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each - Any Block can be erased individually • Single Power Supply Operation - to volt for read, erase, and program operations • Latch-up protected to 100mA from -1V to Vcc +1V • Low Vcc write inhibit is from 1.0V to 1.4V PERFORMANCE • High Performance - Fast read for SPI mode - 1 I/O 104MHz with 8 dummy cycles - 2 I/O 84MHz with 4 dummy cycles, equivalent to 168MHz - 4 I/O 104MHz with 2+4 dummy cycles, equivalent to 416MHz - Fast read for QPI mode - 4 I/O 84MHz with 2+2 dummy cycles, equivalent to 336MHz - 4 I/O 104MHz with 2+4 dummy cycles, equivalent to 416MHz - Fast program time 1.2ms typ. and 3ms max. /page 256-byte per page - Byte program time 12us typical - 8/16/32/64 byte Wrap-Around Burst Read Mode - Fast erase time 60ms typ. /sector 4K-byte per sector 250ms typ. /block 32K-byte per block , 500ms typ. / block 64K-byte per block • Low Power Consumption - Low active read current 20mA typ. at 104MHz, 15mA typ. at 84MHz - Low active erase/programming current 20mA typ. - Standby current 30uA typ. • Deep Power Down 5uA typ. • Typical 100,000 erase/program cycles • 10 years data retention SOFTWARE FEATURES • Input Data Format - 1-byte Command code • Advanced Security Features - Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions - Additional 4k-bit secured OTP for unique identifier • Auto Erase and Auto Program Algorithm - Automatically erases and verifies data at selected sector or block - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the program pulse widths Any page to be programed should have page in the erased state first P/N PM1728 MX25U12835F • Status Register Feature • Command Reset • Program/Erase Suspend • Electronic Identification - JEDEC 1-byte manufacturer ID and 2-byte device ID - RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID • Support Serial Flash Discoverable Parameters SFDP mode HARDWARE FEATURES • SCLK Input - Serial clock input • SI/SIO0 - Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • SO/SIO1 - Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode • WP#/SIO2 - Hardware write protection or serial data Input/Output for 4 x I/O read mode • RESET#/SIO3 - Hardware Reset pin or Serial input & Output for 4 x I/O read mode • PACKAGE - 16-pin SOP 300mil - 8-land WSON 6x5mm - 8-land WSON 8x6mm - All devices are RoHS Compliant P/N PM1728 MX25U12835F MX25U12835F is 128Mb bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When it is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x MX25U12835F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input SCLK , a serial data input SI , and a serial data output SO . Serial access to the device is enabled by CS# input. When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and Reset# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output. The MX25U12835F MXSMIOTM Serial Multi I/O provides sequential read operation on whole chip. After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page 256 bytes basis, or word basis for erase command is executed on sector 4K-byte , block 32K-byte , or block 64K-byte , or whole chip basis. To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit. Advanced security features enhance the protection and security functions, please see security features section for more details. When the device is not in operation and CS# is high, it is put in standby mode and draws less than 30uA DC current. The MX25U12835F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. Table Additional Feature Comparison Additional Features ORDERING INFORMATION PART NO. MX25U12835FMI-10G CLOCK MHz 104 MX25U12835FZNI-10G MX25U12835FZ2I-10G TEMPERATURE -40°C~85°C -40°C~85°C -40°C~85°C PACKAGE 16-SOP 300mil 8-WSON 6x5mm 8-WSON 8x6mm Remark P/N PM1728 MX25U12835F PART NAME DESCRIPTION MX 25 U 12835F ZN I OPTION G RoHS Compliant SPEED 10 104MHz TEMPERATURE RANGE I Industrial -40°C to 85°C PACKAGE M 16-SOP 300mil ZN 8-WSON 6x5mm Z2 8-WSON 8x6mm DENSITY & MODE 12835F 128Mb TYPE U 1.8V DEVICE 25 Serial Flash P/N PM1728 PACKAGE INFORMATION MX25U12835F P/N PM1728 MX25U12835F P/N PM1728 MX25U12835F P/N PM1728 MX25U12835F Changed title from "Advanced Information" to "Preliminary" Modified Chip Erase Cycle Time Modified tVSL min. from 500us to 800us Modified Write Protection Selection WPSEL description Modified Power-up Timing Changed EPN of 8WSON 8x6mm Modified tCE from 100 to 72 sec. typ. , 200 to 160 sec. max. Modified tVSL min. in Power-Up Timing Table Modified value of tWHSL, tSHWL, tCHDX, tCHSH, tSHCH, tSHSL and ISB1 max. in CHARACTERISTICS Table Added Reset# description for write/erase execution Page P4

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MX25U12835F

MX25U12835F DATASHEET

P/N PM1728

MX25U12835F

Contents
4 GENERAL 6

Table Additional Feature PIN CONFIGURATIONS 7 PIN 7 BLOCK 8 DATA 9

Table Protected Area Table 4K-bit Secured OTP 11 Memory 12 Table Memory DEVICE 13 Quad Peripheral Interface QPI Read 15 COMMAND 16 Table Command Write Enable 20 Write Disable 21 Read Identification 22 Release from Deep Power-down RDP , Read Electronic Signature 23 Read Electronic Manufacturer ID & Device ID 25 QPI ID Read 26 Table ID Definitions Read Status Register 27 Read Configuration Register 28 Write Status Register 33 Table Protection Read Data Bytes 37 Read Data Bytes at Higher Speed 38 2 x I/O Read Mode 40 4 x I/O Read Mode 41 Burst 44 Performance Enhance 45 Performance Enhance Mode Reset 48 Sector Erase 49 Block Erase 50 Block Erase 51 Chip Erase 52 Page Program 53 4 x I/O Page Program 55 Deep Power-down 56 Enter Secured OTP 57 Exit Secured OTP 57

P/N PM1728

MX25U12835F

Read Security Register 57 Table Security Register

Write Security Register 58 Write Protection Selection 59 Single Block Lock/Unlock Protection 62 Read Block Lock Status 64 Gang Block Lock/Unlock 64 Program/ Erase Suspend/ 65 Erase 65 Program 65 67 No Operation 67 Software Reset-Enable RSTEN and Reset 67 Read SFDP Mode 69
P/N PM1728

MX25U12835F
1.8V 128M-BIT [x 1/x 2/x 4] CMOS MXSMIOTM SERIAL MULTI I/O FLASH MEMORY

GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 134,217,728 x 1 bit structure or 67,108,864 x 2 bits two I/O mode structure or 33,554,432 x 4 bits four I/O
mode structure
• Equal Sectors with 4K byte each, or Equal Blocks with 32K byte each or Equal Blocks with 64K byte each - Any Block can be erased individually
• Single Power Supply Operation - to volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
• Low Vcc write inhibit is from 1.0V to 1.4V

PERFORMANCE
• High Performance
- Fast read for SPI mode - 1 I/O 104MHz with 8 dummy cycles - 2 I/O 84MHz with 4 dummy cycles, equivalent to 168MHz - 4 I/O 104MHz with 2+4 dummy cycles, equivalent to 416MHz
- Fast read for QPI mode - 4 I/O 84MHz with 2+2 dummy cycles, equivalent to 336MHz - 4 I/O 104MHz with 2+4 dummy cycles, equivalent to 416MHz
- Fast program time 1.2ms typ. and 3ms max. /page 256-byte per page - Byte program time 12us typical - 8/16/32/64 byte Wrap-Around Burst Read Mode - Fast erase time 60ms typ. /sector 4K-byte per sector 250ms typ. /block 32K-byte per block , 500ms typ. / block 64K-byte per block
• Low Power Consumption - Low active read current 20mA typ. at 104MHz, 15mA typ. at 84MHz - Low active erase/programming current 20mA typ. - Standby current 30uA typ.
• Deep Power Down 5uA typ.
• Typical 100,000 erase/program cycles
• 10 years data retention

SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Advanced Security Features
- Block lock protection The BP0-BP3 status bit defines the size of the area to be software protection against program and erase instructions - Additional 4k-bit secured OTP for unique identifier
• Auto Erase and Auto Program Algorithm
- Automatically erases and verifies data at selected sector or block - Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths Any page to be programed should have page in the erased state first

P/N PM1728

MX25U12835F
• Status Register Feature
• Command Reset
• Program/Erase Suspend
• Electronic Identification
- JEDEC 1-byte manufacturer ID and 2-byte device ID
- RES command for 1-byte Device ID - REMS command for 1-byte manufacturer ID and 1-byte device ID
• Support Serial Flash Discoverable Parameters SFDP mode

HARDWARE FEATURES
• SCLK Input
- Serial clock input
• SI/SIO0
- Serial Data Input or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• SO/SIO1
- Serial Data Output or Serial Data Input/Output for 2 x I/O read mode and 4 x I/O read mode
• WP#/SIO2
- Hardware write protection or serial data Input/Output for 4 x I/O read mode
• RESET#/SIO3
- Hardware Reset pin or Serial input & Output for 4 x I/O read mode
• PACKAGE
- 16-pin SOP 300mil - 8-land WSON 6x5mm - 8-land WSON 8x6mm - All devices are RoHS Compliant

P/N PM1728

MX25U12835F

MX25U12835F is 128Mb bits serial Flash memory, which is configured as 16,777,216 x 8 internally. When it is in two or four I/O mode, the structure becomes 67,108,864 bits x 2 or 33,554,432 bits x MX25U12835F features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus while it is in single I/O mode. The three bus signals are a clock input SCLK , a serial data input SI , and a serial data output SO . Serial access to the device is enabled by CS# input.

When it is in two I/O read mode, the SI pin and SO pin become SIO0 pin and SIO1 pin for address/dummy bits input and data output. When it is in four I/O read mode, the SI pin, SO pin, WP# pin and Reset# pin become SIO0 pin, SIO1 pin, SIO2 pin and SIO3 pin for address/dummy bits input and data output.

The MX25U12835F MXSMIOTM Serial Multi I/O provides sequential read operation on whole chip.

After program/erase command is issued, auto program/ erase algorithms which program/ erase and verify the specified page or sector/block locations will be executed. Program command is executed on byte basis, or page 256 bytes basis, or word basis for erase command is executed on sector 4K-byte , block 32K-byte , or block 64K-byte , or whole chip basis.

To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read command can be issued to detect completion status of a program or erase operation via WIP bit.

Advanced security features enhance the protection and security functions, please see security features section for more details.

When the device is not in operation and CS# is high, it is put in standby mode and draws less than 30uA DC current.

The MX25U12835F utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles.

Table Additional Feature Comparison

Additional Features
ORDERING INFORMATION

PART NO. MX25U12835FMI-10G

CLOCK MHz 104

MX25U12835FZNI-10G

MX25U12835FZ2I-10G

TEMPERATURE -40°C~85°C -40°C~85°C -40°C~85°C

PACKAGE 16-SOP 300mil
8-WSON 6x5mm
8-WSON 8x6mm

Remark

P/N PM1728

MX25U12835F

PART NAME DESCRIPTION MX 25 U 12835F ZN I

OPTION G RoHS Compliant

SPEED 10 104MHz

TEMPERATURE RANGE I Industrial -40°C to 85°C

PACKAGE M 16-SOP 300mil ZN 8-WSON 6x5mm Z2 8-WSON 8x6mm

DENSITY & MODE 12835F 128Mb

TYPE U 1.8V

DEVICE 25 Serial Flash

P/N PM1728

PACKAGE INFORMATION

MX25U12835F

P/N PM1728

MX25U12835F

P/N PM1728

MX25U12835F

P/N PM1728

MX25U12835F

Changed title from "Advanced Information" to "Preliminary"

Modified Chip Erase Cycle Time

Modified tVSL min. from 500us to 800us

Modified Write Protection Selection WPSEL description

Modified Power-up Timing

Changed EPN of 8WSON 8x6mm

Modified tCE from 100 to 72 sec. typ. , 200 to 160 sec. max.

Modified tVSL min. in Power-Up Timing Table

Modified value of tWHSL, tSHWL, tCHDX, tCHSH, tSHCH,
tSHSL and ISB1 max. in CHARACTERISTICS Table

Added Reset# description for write/erase execution

Page P4

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Datasheet ID: MX25U12835FZNI-08G 646945