M21260G-12

M21260G-12 Datasheet

This part has been replaced by the M21355

Part	Datasheet
M21260G-12	M21260G-12 (pdf)

PDF Datasheet Preview
Not Recommended for New Designs This part has been replaced by the M21355 M21260 4x4 Crosspoint Switch with Integrated CDR/Reclockers The M21260 is a high-performance 4x4 crosspoint switch with an integrated independent multi-rate quad channel CDR/reclocker array, optimized for telecom, datacom, and digital video applications. Each channel has an independent multi-rate reclocker capable of operating at data-rates between 42 Mbps and Gbps. Signal conditioning features include input equalization and output pre-emphasis, allowing robust reception and transmission of signals to other devices up to 60" away. The built-in frequency synthesizer allows multi-rate operation, while operating from a single reference clock. The device can be controlled either through hardwired pins or a 2-wire or 4-wire serial programming interface. The hardwired mode eliminates the need for an external micro-controller, while allowing control of the key features of the device. The serial programming interface is available as a two wire or four wire and allows complete control of the device features. The M21260 supports JTAG external boundary scan, which includes all of the high-speed I/O as well as the traditional digital I/O. • 4x4 Crosspoint Switch with four independent Reclockers RCLKs • 3G/HD/SD-SDI Routing Switchers, Distribution amplifiers, and SMPTE, DVB-ASI compliant transport systems1 • Integrated loop filter and terminations • SONET systems and modules • Serial control or hardwired control, JTAG boundary scan • 10 GBASE-CX4 systems • Low power consumption of 405 mW 1 channel active • Gigabit Ethernet systems • Built-in pattern generator and receiver for module and system • PCI-Express testing PRBS, 8b/10b, Fibre Channel, User Programmable patterns • SAS/S-ATA/S-ATA2 systems • Broadcast and Multicast crosspoint modes Standards Compliance • User Selectable Input Equalization and Pre-Emphasis for backplane • SMPTE 292M ISI reduction • SMPTE 259M • SMPTE 344M • SMPTE 424M Functional Block Diagram Not Recommended for New Designs xEn_Port [3:0] MF [11:0] XPoint_Mode [3:0] CTRL_Mode [1:0] Out_Mode [1:0] xRST xLOL[3:0] xLOA[3:0] xJTAG_En xRegu_En Input Equalization Input Buffer BIST Transmitter Mux 4x4 Crosspoint Reclocker Array BIST Receiver Mux Selectable CML, LVDS Output Buffer + Pre-Emphasis Din0 [P/N] Din1 [P/N] Din2 [P/N] Din3 [P/N] Multifunction Pin Array Serial Interface/Hardwired Mode BIST Transmitter JTAG Voltage Regulator Dout0 [P/N] Dout1 [P/N] Dout2 [P/N] BIST Receiver Dout3 [P/N] Ordering Information Number of Channels Package M21260-12 M21260G-12* 72-terminal, 10 mm, QFN 72-terminal, 10 mm, QFN, RoHS compliant package Operating Temperature -40°C to +85°C -40°C to +85°C * The letter “G” designator after the part number indicates that the device is RoHS compliant. Refer to for additional information. The RoHS compliant devices are backwards compatible with 225°C reflow profiles. Not Recommended for New Designs 21260-DSH-001-H Mindspeed Not Recommended for New Designs / Mindspeed Proprietary and Confidential Not Recommended for New Designs December 2010 March 2009 May 2008 January 2007 October 2005 February 2005 May 2004 March 2004 • Removed video support in hardware mode Table 3-5 and Table • Update table reference in Section • Updated LOS Section and added Figure • JTRF replaced with JTRAN • tPLL replaced with tLOCK • tPD, CLOCK replaced with tSKEW, CLK-DATA • DCD replaced with DCDDATA • DR and DR replaced with DR • idd_core replaced with DIDDCORE • idd_io replaced with DIDDIO • VID replaced with VIN • CVOD replaced with VOD • NNARROW replaced with NNARROW • NWIDE replaced with NWIDE • Added register M8h, CDR#N LOA Window Control trim Section • Added support for Telecom and Datacom applications. • Updated specification tables. • Reformatted register tables. • Changed temperature range as follows from to 85°C” to “0°C to 70°C.” • Removed reference to LVPECL output mode. Inputs can be AC-coupled to LVPECL signals. • Changed ESD rating for high speed pins to 350V with HBM testing. • Removed references to FDA operation. FDA is not supported with this device. • Modified ARD description, added misc. figures, tables, updated device description as necessary. • Changed ordering information from M21260-11P to M21260-12P. • Initial release. 21260-DSH-001-H Mindspeed Not Recommended for New Designs / Mindspeed Proprietary and Confidential Table of Contents Ordering Information 2 Table of Contents 4 List of Figures 6 List of Tables 7 Product Specifications 10 Absolute Maximum Ratings Recommended Operating Conditions Power Dissipation Input/Output Specifications High-Speed Performance Specifications Package Drawings and Surface Mount Assembly Details PCB High-Speed Design and Layout Guidelines Auto Rate Detect ARD . Registers. 31 Global Control Registers 21260-DSH-001-H Mindspeed Mindspeed Proprietary and Confidential Table of Contents Internal Junction Temperature Monitor Internal Junction Temperature Value CDR/RCLK Loss of Lock Register Alarm Status CDR/RCLK Loss of Activity Register Alarm Status 32h:VCO Trim Alarm Window Individual Channel/CDR/RCLK Control M0h:CDR N Control Register A M1h:CDR/RCLK N Control Register B CDR/RCLK N Control Register C Output Buffer Control for CDR/RCLK N Output Buffer Pre-Emphasis Control for Output N Input Equalization Control for Output N CDR/RCLK N Loop Bandwidth and Data Sampling Point Adjust. CDR#N LOA Window Control trim CDR/RCLK N LOL Window Control MAh Jitter Reduction Control Functional Description 54 Applications. Detailed Feature Descriptions 21260-DSH-001-H Mindspeed Mindspeed Proprietary and Confidential Table of Contents Appendix 80 A.1 Glossary of Terms/Acronyms A.2 Reference Documents A.2.1 External A.2.2 Mindspeed 21260-DSH-001-H Mindspeed Mindspeed Proprietary and Confidential List of Figures Figure Data Input Internal Circuitry Figure Definitions of Eye Parameters. Figure Reference Clock Input Internal Circuitry Figure SMPTE Jitter Tolerance Specification Mask Figure SONET Jitter Tolerance Specification Mask Figure SONET/SMPTE Jitter Transfer Specification Mask Figure Cross-Section of QFN Package Figure Package Drawing 1of 2 Figure Package Drawing 2 of 2 Figure 72-Pin Package Dimensions Figure PCB Footprint for 72-Pin 10 mm QFN Package. Figure PCB Pad Extensions Figure Recommended Via Array for Thermal Pad Figure Trace-Length Matching Using Serpentine Pattern Figure Loop Length Matching for Differential Traces. Figure M21260 Application - Small Routing Switcher Figure Module Application Figure Backplane Application. Figure Recommended Data and Reference Clock Input Coupling Circuitry Figure Serial Word Format. Figure Serial WRITE Mode. Figure Serial READ Mode Figure STS-48 waveform after transmission through 76” of PCB traces input to M21260 Figure STS-48 waveform at M21260 output with input shown in Figure Definition of Pre-Emphasis Levels Figure Block Diagram of Frequency Acquisition Circuits Figure M21260 Pinout Diagram Top View 21260-DSH-001-H Mindspeed Mindspeed Proprietary and Confidential List of Tables BIST_pattern0 Address 1Bh 41 21260-DSH-001-H Mindspeed Mindspeed Proprietary and Confidential List of Tables Table Built In Self-Test BIST Transmitter 16/20 bit User Programmable Pattern BIST_pattern1 Address 1Ch 41 Table Built In Self-Test BIST Transmitter 16/20 bit User Programmable Pattern BIST_pattern2 Address 1Dh 41 Table Built In Self-Test BIST Transmitter Alarm BISTtx_alarm Address 1Fh Table Internal Junction Temperature Monitor Temp_mon Address 20h . Table Internal Junction Temperature Value Temp_value Address 21h Table CDR/RCLK Loss of Lock Register Alarm Status Alarm_LOL Address 30h Table CDR/RCLK Loss of Activity Register Alarm Status Alarm_LOA Address 31h Table VCO Trim Alarm Window Trim Alarm_trim Address 32h Table CDR N Control Register A RCLK_ctrlA_N Address M0h Table CDR N Control Register B RCLK_ctrlB_N Address M1h Table CDR/RCLK N Control Register C RCLK_ctrlC_N Address M2h Table Output Buffer Control for CDR/RCLK N Out_ctrl_N Address M3h . Table Output Buffer Pre-Emphasis Control for Output N Preemp_ctrl_N Address M4h Table Input Equalization Control for Output N Ineq_ctrl_N Address M5h Table CDR/RCLK N Loop Bandwidth and Data Sampling Point Adjust Phadj_ctrl_N Address M6h Table CDR#N LOA Window Control trim LOA_ctrl_N Address M8h . Table CDR/RCLK N LOL Window Control LOL_ctrl_N Address M9h Table Jitter Reduction Control Jitter_reduc_N Address MAh Table Output Interface and Level Mapping For both hardwired and software modes Table Output Interface and Recommended AVDDIO Range Table Crosspoint Switch-State in Hardwired Mode Table Mode Select Pins Table Multifunction Pins for Hardwired Mode Table Hardwired Data-Rates and Associated Reference Clock Frequencies Table Multi-function Pins for Four-Wire Interface Table Serial Interface Timing Specified at Recommended Operating Conditions Table Multifunction Pins for Two-Wire Interface Table Multifunction Pins for JTAG Table Valid Input Data Ranges Table Reference Clock Frequency Ranges Table DRD/RFD/VCD Settings for Different Data-Rates and Reference Frequencies. Table LOL Window Size and Decision Time Examples Table Supported Ambient Temperature Range by Data-Rate Table BIST PRBS Patterns Table BIST 8b/10b Patterns Table Junction Temperature Monitor Table Power Pins Table High-Speed Signal Pins

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Not Recommended for New Designs

This part has been replaced by the M21355

M21260
4x4 Crosspoint Switch with Integrated CDR/Reclockers

The M21260 is a high-performance 4x4 crosspoint switch with an integrated independent multi-rate quad channel CDR/reclocker array, optimized for telecom, datacom, and digital video applications. Each channel has an independent multi-rate reclocker capable of operating at data-rates between 42 Mbps and Gbps. Signal conditioning features include input equalization and output pre-emphasis, allowing robust reception and transmission of signals to other devices up to 60" away. The built-in frequency synthesizer allows multi-rate operation, while operating from a single reference clock.

The device can be controlled either through hardwired pins or a 2-wire or 4-wire serial programming interface. The hardwired mode eliminates the need for an external micro-controller, while allowing control of the key features of the device. The serial programming interface is available as a two wire or four wire and allows complete control of the device features.

The M21260 supports JTAG external boundary scan, which includes all of the high-speed I/O as well as the traditional digital I/O.
• 4x4 Crosspoint Switch with four independent Reclockers RCLKs
• 3G/HD/SD-SDI Routing Switchers, Distribution amplifiers, and

SMPTE, DVB-ASI compliant
transport systems1
• Integrated loop filter and terminations
• SONET systems and modules
• Serial control or hardwired control, JTAG boundary scan
• 10 GBASE-CX4 systems
• Low power consumption of 405 mW 1 channel active
• Gigabit Ethernet systems
• Built-in pattern generator and receiver for module and system
• PCI-Express
testing PRBS, 8b/10b, Fibre Channel, User Programmable patterns
• SAS/S-ATA/S-ATA2 systems
• Broadcast and Multicast crosspoint modes

Standards Compliance
• User Selectable Input Equalization and Pre-Emphasis for backplane
• SMPTE 292M ISI reduction
• SMPTE 259M
• SMPTE 344M
• SMPTE 424M

Functional Block Diagram

Not Recommended for New Designs
xEn_Port [3:0] MF [11:0] XPoint_Mode [3:0] CTRL_Mode [1:0] Out_Mode [1:0] xRST xLOL[3:0] xLOA[3:0] xJTAG_En xRegu_En

Input Equalization Input Buffer

BIST Transmitter Mux 4x4 Crosspoint

Reclocker Array BIST Receiver Mux

Selectable CML, LVDS Output Buffer +

Pre-Emphasis

Din0 [P/N] Din1 [P/N] Din2 [P/N] Din3 [P/N]

Multifunction Pin Array Serial Interface/Hardwired Mode

BIST Transmitter

JTAG

Voltage Regulator

Dout0 [P/N] Dout1 [P/N] Dout2 [P/N]

BIST Receiver

Dout3 [P/N]
Ordering Information

Number of Channels

Package

M21260-12 M21260G-12*
72-terminal, 10 mm, QFN
72-terminal, 10 mm, QFN, RoHS compliant package

Operating Temperature
-40°C to +85°C -40°C to +85°C
* The letter “G” designator after the part number indicates that the device is RoHS compliant. Refer to for additional information. The RoHS compliant devices are backwards compatible with 225°C reflow profiles.

Not Recommended for New Designs
21260-DSH-001-H

Mindspeed

Not Recommended for New Designs / Mindspeed Proprietary and Confidential

Not Recommended for New Designs

December 2010

March 2009

May 2008

January 2007

October 2005

February 2005

May 2004

March 2004
• Removed video support in hardware mode Table 3-5 and Table
• Update table reference in Section
• Updated LOS Section and added Figure
• JTRF replaced with JTRAN
• tPLL replaced with tLOCK
• tPD, CLOCK replaced with tSKEW, CLK-DATA
• DCD replaced with DCDDATA
• DR and DR replaced with DR
• idd_core replaced with DIDDCORE
• idd_io replaced with DIDDIO
• VID replaced with VIN
• CVOD replaced with VOD
• NNARROW replaced with NNARROW
• NWIDE replaced with NWIDE
• Added register M8h, CDR#N LOA Window Control trim Section
• Added support for Telecom and Datacom applications.
• Updated specification tables.
• Reformatted register tables.
• Changed temperature range as follows from to 85°C” to “0°C to 70°C.”
• Removed reference to LVPECL output mode. Inputs can be AC-coupled to LVPECL signals.
• Changed ESD rating for high speed pins to 350V with HBM testing.
• Removed references to FDA operation. FDA is not supported with this device.
• Modified ARD description, added misc. figures, tables, updated device description as necessary.
• Changed ordering information from M21260-11P to M21260-12P.
• Initial release.
21260-DSH-001-H

Mindspeed

Not Recommended for New Designs / Mindspeed Proprietary and Confidential

Table of Contents
Ordering Information 2

Table of Contents 4

List of Figures 6

List of Tables 7

Product Specifications 10

Absolute Maximum Ratings Recommended Operating Conditions Power Dissipation Input/Output Specifications High-Speed Performance Specifications Package Drawings and Surface Mount Assembly Details PCB High-Speed Design and Layout Guidelines Auto Rate Detect ARD .

Registers. 31

Global Control Registers
21260-DSH-001-H

Mindspeed

Mindspeed Proprietary and Confidential

Table of Contents

Internal Junction Temperature Monitor Internal Junction Temperature Value CDR/RCLK Loss of Lock Register Alarm Status CDR/RCLK Loss of Activity Register Alarm Status 32h:VCO Trim Alarm Window Individual Channel/CDR/RCLK Control

M0h:CDR N Control Register A M1h:CDR/RCLK N Control Register B CDR/RCLK N Control Register C Output Buffer Control for CDR/RCLK N Output Buffer Pre-Emphasis Control for Output N Input Equalization Control for Output N CDR/RCLK N Loop Bandwidth and Data Sampling Point Adjust. CDR#N LOA Window Control trim CDR/RCLK N LOL Window Control MAh Jitter Reduction Control

Functional Description 54

Applications.

Detailed Feature Descriptions
21260-DSH-001-H

Mindspeed

Mindspeed Proprietary and Confidential

Table of Contents

Appendix 80

A.1 Glossary of Terms/Acronyms A.2 Reference Documents

A.2.1 External A.2.2 Mindspeed
21260-DSH-001-H

Mindspeed

Mindspeed Proprietary and Confidential

List of Figures

Figure Data Input Internal Circuitry Figure Definitions of Eye Parameters. Figure Reference Clock Input Internal Circuitry Figure SMPTE Jitter Tolerance Specification Mask Figure SONET Jitter Tolerance Specification Mask Figure SONET/SMPTE Jitter Transfer Specification Mask Figure Cross-Section of QFN Package Figure Package Drawing 1of 2 Figure Package Drawing 2 of 2 Figure 72-Pin Package Dimensions Figure PCB Footprint for 72-Pin 10 mm QFN Package. Figure PCB Pad Extensions Figure Recommended Via Array for Thermal Pad Figure Trace-Length Matching Using Serpentine Pattern Figure Loop Length Matching for Differential Traces. Figure M21260 Application - Small Routing Switcher Figure Module Application Figure Backplane Application. Figure Recommended Data and Reference Clock Input Coupling Circuitry Figure Serial Word Format. Figure Serial WRITE Mode. Figure Serial READ Mode Figure STS-48 waveform after transmission through 76” of PCB traces input to M21260 Figure STS-48 waveform at M21260 output with input shown in Figure Definition of Pre-Emphasis Levels Figure Block Diagram of Frequency Acquisition Circuits Figure M21260 Pinout Diagram Top View
21260-DSH-001-H

Mindspeed

Mindspeed Proprietary and Confidential

List of Tables

BIST_pattern0 Address 1Bh 41
21260-DSH-001-H

Mindspeed

Mindspeed Proprietary and Confidential

List of Tables

Table Built In Self-Test BIST Transmitter 16/20 bit User Programmable Pattern BIST_pattern1 Address 1Ch 41

Table Built In Self-Test BIST Transmitter 16/20 bit User Programmable Pattern BIST_pattern2 Address 1Dh 41

Table Built In Self-Test BIST Transmitter Alarm BISTtx_alarm Address 1Fh Table Internal Junction Temperature Monitor Temp_mon Address 20h . Table Internal Junction Temperature Value Temp_value Address 21h Table CDR/RCLK Loss of Lock Register Alarm Status Alarm_LOL Address 30h Table CDR/RCLK Loss of Activity Register Alarm Status Alarm_LOA Address 31h Table VCO Trim Alarm Window Trim Alarm_trim Address 32h Table CDR N Control Register A RCLK_ctrlA_N Address M0h Table CDR N Control Register B RCLK_ctrlB_N Address M1h Table CDR/RCLK N Control Register C RCLK_ctrlC_N Address M2h Table Output Buffer Control for CDR/RCLK N Out_ctrl_N Address M3h . Table Output Buffer Pre-Emphasis Control for Output N Preemp_ctrl_N Address M4h Table Input Equalization Control for Output N Ineq_ctrl_N Address M5h Table CDR/RCLK N Loop Bandwidth and Data Sampling Point Adjust Phadj_ctrl_N Address M6h Table CDR#N LOA Window Control trim LOA_ctrl_N Address M8h . Table CDR/RCLK N LOL Window Control LOL_ctrl_N Address M9h Table Jitter Reduction Control Jitter_reduc_N Address MAh Table Output Interface and Level Mapping For both hardwired and software modes Table Output Interface and Recommended AVDDIO Range Table Crosspoint Switch-State in Hardwired Mode Table Mode Select Pins Table Multifunction Pins for Hardwired Mode Table Hardwired Data-Rates and Associated Reference Clock Frequencies Table Multi-function Pins for Four-Wire Interface Table Serial Interface Timing Specified at Recommended Operating Conditions Table Multifunction Pins for Two-Wire Interface Table Multifunction Pins for JTAG Table Valid Input Data Ranges Table Reference Clock Frequency Ranges Table DRD/RFD/VCD Settings for Different Data-Rates and Reference Frequencies. Table LOL Window Size and Decision Time Examples Table Supported Ambient Temperature Range by Data-Rate Table BIST PRBS Patterns Table BIST 8b/10b Patterns Table Junction Temperature Monitor Table Power Pins Table High-Speed Signal Pins

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived M21260G-12 Datasheet file may be downloaded here without warranties.

Datasheet ID: M21260G-12 646845