M21250G-12

M21250G-12 Datasheet

This part has been replaced by the M21355

Part	Datasheet
M21250G-12	M21250G-12 (pdf)

PDF Datasheet Preview
Not Recommended for New Designs This part has been replaced by the M21355 M21250/M21251/M21252 Quad-Channel CDR/Reclocker 42 Mbps - Gbps The M21250, M21251, and M21252 M2125x devices are high-performance quad channel retimers optimized for telecom, datacom, and digital video applications. Each channel of the CDR/reclocker array includes an independent multi-rate CDR/reclocker, allowing maximum flexibility in system design. Signal conditioning features of the M2125x include input equalization and output pre-emphasis to compensate for lossy PCB traces and backplane connectors. A built-in frequency synthesizer allows each channel of the device to operate at a different data rate simultaneously while operating from a single reference clock. The M2125x can be controlled through hardwired pins or via a 2-wire or 4-wire serial programming interface. The serial programming interface allows users to have complete control of the device features. The M2125x devices support JTAG external boundary scan which includes all of the high-speed I/O as well as the digital I/O. • Four independent CDR/reclockers CDR/RCLKs SMPTE, DVB-ASI compliant • Integrated loop filter and terminations • Serial control or hardwired control, JTAG boundary scan • Low power consumption of 400 mW 1 channel active • Built-in pattern generator and receiver with JTAG support for module and system testing PRBS, 8b/10b, Fibre Channel, User Programmable patterns • User Selectable Input Equalization and Pre-Emphasis for backplane ISI reduction • Multirate support 42 Mbps - Gbps • Differential outputs for recovered clock and retimed data • 3G/HD/SD-SDI Routing Switchers1 • 3G/HD/SD-SDI Video Transport Systems1 • 3G/HD/SD-SDI Distribution Amplifiers1 • Backplane Reach Extension • SONET Systems and Modules • 10GBASE-CX4 Systems • Gigabit Ethernet Systems • SAS/S-ATA/S-ATA2 Systems • PCI Express Standards Compliance • SMPTE 292M • SMPTE 259M • SMPTE 344M • SMPTE 424M Functional Block Diagram Not Recommended for New Designs MF[11:0] CTRL_Mode[1:0] Out_Mode[1:0] xRST xLOA[3:0] xLOL[3:0] xJTAG_En xRegu_En Input Buffer BIST Transmitter Mux Reclocker Array BIST Rx Mux Selectable CML, LVDS Output Buffer Din0P/N VddT0/1 Din1P/N Din2P/N VddT2/3 Din3P/N Multi-function Pin Array Serial Interface/Hardwired Mode BIST Tx PRBS & 8b/10 JTAG Voltage Regulator BIST Rx PRBS & 8b/10 Cout0P/N Cout1P/N Cout2P/N Cout3P/N Dout0P/N Dout1P/N Dout2P/N Dout3P/N RefClkP/N 2125x-DSH-001-J Mindspeed Mindspeed Proprietary and Confidential / Not Recommend for New Designs December 2010 Not Recommended for New Designs Ordering Information Ordering Part Number Package M21250 Quad Multi-rate CDR/Reclocker Mbps M21250-12 72-terminal, 10 mm, QFN M21251 Quad Multi-rate CDR/Reclocker Mbps DS-M21251-21 72-terminal, 10 mm, QFN M21252 Quad Multi-rate CDR/Reclocker Mbps DS-M21252-21 72-terminal, 10 mm, QFN M21250 Quad Multi-rate CDR/Reclocker Mbps M21250G-12* 72-terminal, 10 mm, QFN, RoHS compliant package M21251 Quad Multi-rate CDR/Reclocker Mbps DS-M21251G-21* 72-terminal, 10 mm, QFN, RoHS compliant package M21252 Quad Multi-rate CDR/Reclocker Mbps DS-M21252G-21* 72-terminal, 10 mm, QFN, RoHS compliant package * The letter “G” designator after the part number indicates that the device is RoHS-compliant. The RoHS-compliant devices are backwards compatible with 225°C reflow profiles. Refer to for additional information. Comments December 2010 Added warning that this part is not recommended for new designs. Standardized symbols throughout document: • JTRF replaced with JTRAN • tPLL replaced with tLOCK • tPD, CLOCK replaced with tSKEW, CLK-DATA • DCD replaced with DCDDATA • DRIN and DROUT replaced with DR • idd_core replaced with DIDDCORE • idd_io replaced with DIDDIO • VID replaced with VIN • CVOD replaced with VOD • NRW replaced with NNARROW • WRW replaced with NWIDE Added register M8h, CDR#N LOA Window Control trim Section November 2009 - Removed video support in hardware mode Table 4-4 and Table 4-5 - Updated video support in Section and Table 4-12 - Added Figure 4-11 LOA Timing trigger and updated Section - Added marking diagrams. Various October 2003 Original release. 2125x-DSH-001-J Mindspeed Mindspeed Proprietary and Confidential / Not Recommend for New Designs M21250, M21251, M21252 Marking Diagrams M21250G-12 Lot # Date/Country Code M21251G-21 Lot # Date/Country Code M21252G-21 Lot # Date/Country Code Ordering Information 2 Table of Contents 4 List of Figures 7 List of Tables 8 Electrical Characteristics 10 Absolute Maximum Ratings Recommended Operating Conditions Power Dissipation Input/Output Specifications High-Speed Performance Specifications Pinout Diagram, Pin Descriptions, and Package Outline Drawing 23 Pin Definitions Package Drawings and Surface Mount Assembly Details PCB High-Speed Design and Layout Guidelines Auto Rate Detect ARD for HD/SD-SDI Digital Video Rates Control Registers Map and Descriptions. 35 Global Control Registers 2125x-DSH-001-J Mindspeed Mindspeed Proprietary and Confidential / Not Recommend for New Designs Table of Contents Not Recommended for New Designs 1Dh:Built In Self-Test BIST Transmitter 16/20 bit User Programmable Pattern. 1Fh:Built In Self-Test BIST Transmitter Alarm 20h:Internal Junction Temperature Monitor. 21h:Internal Junction Temperature Value. 30h:CDR/RCLK Loss of Lock Register Alarm Status 31h:Loss of Activity Register Alarm Status 32h:VCO Trim Alarm Window Individual Channel/CDR/RCLK Control M0h:CDR N Control Register A M1h:CDR/RCLK N Control Register B M2h:CDR/RCLK N Control Register C M3h:Output Buffer Control for CDR/RCLK N M4h:Output Buffer Pre-Emphasis Control for Output N M5h:Input Equalization Control for Output N M6h:CDR/RCLK N Loop Bandwidth and Data Sampling Point Adjust. CDR#N LOA Window Control trim M9h:CDR/RCLK N LOL Window Control MAh Trim Force. MBh Trim Value. Functional Descriptions. 58 Applications. Detailed Feature Descriptions Reference Documents 2125x-DSH-001-J Mindspeed Mindspeed Proprietary and Confidential / Not Recommend for New Designs Table of Contents External Mindspeed Not Recommended for New Designs 2125x-DSH-001-J Mindspeed Mindspeed Proprietary and Confidential / Not Recommend for New Designs Not Recommended for New Designs List of Figures Figure Data Input Internal Circuitry Figure Definitions of Eye Parameters. Figure Reference Clock Input Internal Circuitry Figure Clock and Data Output Skew Timing. Figure SMPTE Jitter Tolerance Specification Mask Figure SONET Jitter Tolerance Specification Mask Figure SONET/SMPTE Jitter Transfer Specification Mask Figure M2125x Pinout Diagram Top View . Figure Cross-Section of QFN Package Figure Package Drawing 1of 2 Figure Package Drawing 2 of 2 Figure 72-Pin Package Dimensions Figure PCB Footprint for 72-Pin 10 mm QFN Package. Figure PCB Pad Extensions Figure Recommended Via Array for Thermal Pad Figure Trace-Length Matching Using Serpentine Pattern Figure Loop Length Matching for Differential Traces. Figure Module Application Figure Backplane Application. Figure Recommended Data and Reference Clock Input Coupling Circuitry Figure Serial Word Format. Figure Serial WRITE Mode. Figure Serial READ Mode Figure STS-48 waveform after transmission through 76” of PCB traces input to M21250 Figure STS-48 waveform at M21250 output with input shown in Figure Definition of Pre-Emphasis Levels Figure Block Diagram of Frequency Acquisition Circuits Figure LOA Timing. 2125x-DSH-001-J Mindspeed Mindspeed Proprietary and Confidential / Not Recommend for New Designs List of Tables Not Recommended for New Designs BIST_pattern0 Address 1Bh 44 Table Built In Self-Test BIST Transmitter 16/20 bit User Programmable Pattern BIST_pattern1 Address 1Ch 44 2125x-DSH-001-J

PDF Datasheet Preview

Not Recommended for New Designs

This part has been replaced by the M21355

M21250/M21251/M21252

Quad-Channel CDR/Reclocker 42 Mbps - Gbps

The M21250, M21251, and M21252 M2125x devices are high-performance quad channel retimers optimized for telecom, datacom, and digital video applications. Each channel of the CDR/reclocker array includes an independent multi-rate CDR/reclocker, allowing maximum flexibility in system design. Signal conditioning features of the M2125x include input equalization and output pre-emphasis to compensate for lossy PCB traces and backplane connectors. A built-in frequency synthesizer allows each channel of the device to operate at a different data rate simultaneously while operating from a single reference clock. The M2125x can be controlled through hardwired pins or via a 2-wire or 4-wire serial programming interface. The serial programming interface allows users to have complete control of the device features. The M2125x devices support JTAG external boundary scan which includes all of the high-speed I/O as well as the digital I/O.
• Four independent CDR/reclockers CDR/RCLKs SMPTE, DVB-ASI compliant
• Integrated loop filter and terminations
• Serial control or hardwired control, JTAG boundary scan
• Low power consumption of 400 mW 1 channel active
• Built-in pattern generator and receiver with JTAG support for module
and system testing PRBS, 8b/10b, Fibre Channel, User Programmable patterns
• User Selectable Input Equalization and Pre-Emphasis for backplane ISI reduction
• Multirate support 42 Mbps - Gbps
• Differential outputs for recovered clock and retimed data
• 3G/HD/SD-SDI Routing Switchers1
• 3G/HD/SD-SDI Video Transport Systems1
• 3G/HD/SD-SDI Distribution Amplifiers1
• Backplane Reach Extension
• SONET Systems and Modules
• 10GBASE-CX4 Systems
• Gigabit Ethernet Systems
• SAS/S-ATA/S-ATA2 Systems
• PCI Express

Standards Compliance
• SMPTE 292M
• SMPTE 259M
• SMPTE 344M
• SMPTE 424M

Functional Block Diagram

Not Recommended for New Designs

MF[11:0] CTRL_Mode[1:0] Out_Mode[1:0] xRST xLOA[3:0] xLOL[3:0] xJTAG_En xRegu_En

Input Buffer BIST Transmitter Mux

Reclocker Array BIST Rx Mux

Selectable CML, LVDS Output Buffer

Din0P/N VddT0/1 Din1P/N

Din2P/N VddT2/3 Din3P/N

Multi-function Pin Array Serial Interface/Hardwired Mode

BIST Tx PRBS &
8b/10

JTAG

Voltage Regulator

BIST Rx PRBS &
8b/10

Cout0P/N Cout1P/N Cout2P/N Cout3P/N

Dout0P/N Dout1P/N Dout2P/N Dout3P/N

RefClkP/N
2125x-DSH-001-J

Mindspeed

Mindspeed Proprietary and Confidential / Not Recommend for New Designs

December 2010

Not Recommended for New Designs
Ordering Information
Ordering Part Number

Package

M21250 Quad Multi-rate CDR/Reclocker Mbps

M21250-12
72-terminal, 10 mm, QFN

M21251 Quad Multi-rate CDR/Reclocker Mbps

DS-M21251-21
72-terminal, 10 mm, QFN

M21252 Quad Multi-rate CDR/Reclocker Mbps

DS-M21252-21
72-terminal, 10 mm, QFN

M21250 Quad Multi-rate CDR/Reclocker Mbps

M21250G-12*
72-terminal, 10 mm, QFN, RoHS compliant package

M21251 Quad Multi-rate CDR/Reclocker Mbps

DS-M21251G-21*
72-terminal, 10 mm, QFN, RoHS compliant package

M21252 Quad Multi-rate CDR/Reclocker Mbps

DS-M21252G-21*
72-terminal, 10 mm, QFN, RoHS compliant package
* The letter “G” designator after the part number indicates that the device is RoHS-compliant. The RoHS-compliant devices are backwards compatible with 225°C reflow profiles. Refer to for additional information.

Comments

December 2010 Added warning that this part is not recommended for new designs.

Standardized symbols throughout document:
• JTRF replaced with JTRAN
• tPLL replaced with tLOCK
• tPD, CLOCK replaced with tSKEW, CLK-DATA
• DCD replaced with DCDDATA
• DRIN and DROUT replaced with DR
• idd_core replaced with DIDDCORE
• idd_io replaced with DIDDIO
• VID replaced with VIN
• CVOD replaced with VOD
• NRW replaced with NNARROW
• WRW replaced with NWIDE Added register M8h, CDR#N LOA Window Control trim Section

November 2009 - Removed video support in hardware mode Table 4-4 and Table 4-5
- Updated video support in Section and Table 4-12
- Added Figure 4-11 LOA Timing trigger and updated Section
- Added marking diagrams.

Various

October 2003 Original release.
2125x-DSH-001-J

Mindspeed

Mindspeed Proprietary and Confidential / Not Recommend for New Designs

M21250, M21251, M21252 Marking Diagrams

M21250G-12 Lot #

Date/Country Code

M21251G-21 Lot #

Date/Country Code

M21252G-21 Lot #

Date/Country Code
Ordering Information 2

Table of Contents 4

List of Figures 7

List of Tables 8

Electrical Characteristics 10

Absolute Maximum Ratings Recommended Operating Conditions Power Dissipation Input/Output Specifications High-Speed Performance Specifications

Pinout Diagram, Pin Descriptions, and Package Outline Drawing 23

Pin Definitions Package Drawings and Surface Mount Assembly Details PCB High-Speed Design and Layout Guidelines Auto Rate Detect ARD for HD/SD-SDI Digital Video Rates

Control Registers Map and Descriptions. 35

Global Control Registers
2125x-DSH-001-J

Mindspeed

Mindspeed Proprietary and Confidential / Not Recommend for New Designs

Table of Contents

Not Recommended for New Designs
1Dh:Built In Self-Test BIST Transmitter 16/20 bit User Programmable Pattern. 1Fh:Built In Self-Test BIST Transmitter Alarm 20h:Internal Junction Temperature Monitor. 21h:Internal Junction Temperature Value. 30h:CDR/RCLK Loss of Lock Register Alarm Status 31h:Loss of Activity Register Alarm Status 32h:VCO Trim Alarm Window Individual Channel/CDR/RCLK Control

M0h:CDR N Control Register A M1h:CDR/RCLK N Control Register B M2h:CDR/RCLK N Control Register C M3h:Output Buffer Control for CDR/RCLK N M4h:Output Buffer Pre-Emphasis Control for Output N M5h:Input Equalization Control for Output N M6h:CDR/RCLK N Loop Bandwidth and Data Sampling Point Adjust. CDR#N LOA Window Control trim M9h:CDR/RCLK N LOL Window Control MAh Trim Force. MBh Trim Value.

Functional Descriptions. 58

Applications.

Detailed Feature Descriptions

Reference Documents
2125x-DSH-001-J

Mindspeed

Mindspeed Proprietary and Confidential / Not Recommend for New Designs

Table of Contents

External Mindspeed

Not Recommended for New Designs
2125x-DSH-001-J

Mindspeed

Mindspeed Proprietary and Confidential / Not Recommend for New Designs

Not Recommended for New Designs

List of Figures

Figure Data Input Internal Circuitry Figure Definitions of Eye Parameters. Figure Reference Clock Input Internal Circuitry Figure Clock and Data Output Skew Timing. Figure SMPTE Jitter Tolerance Specification Mask Figure SONET Jitter Tolerance Specification Mask Figure SONET/SMPTE Jitter Transfer Specification Mask Figure M2125x Pinout Diagram Top View . Figure Cross-Section of QFN Package Figure Package Drawing 1of 2 Figure Package Drawing 2 of 2 Figure 72-Pin Package Dimensions Figure PCB Footprint for 72-Pin 10 mm QFN Package. Figure PCB Pad Extensions Figure Recommended Via Array for Thermal Pad Figure Trace-Length Matching Using Serpentine Pattern Figure Loop Length Matching for Differential Traces. Figure Module Application Figure Backplane Application. Figure Recommended Data and Reference Clock Input Coupling Circuitry Figure Serial Word Format. Figure Serial WRITE Mode. Figure Serial READ Mode Figure STS-48 waveform after transmission through 76” of PCB traces input to M21250 Figure STS-48 waveform at M21250 output with input shown in Figure Definition of Pre-Emphasis Levels Figure Block Diagram of Frequency Acquisition Circuits Figure LOA Timing.
2125x-DSH-001-J

Mindspeed

Mindspeed Proprietary and Confidential / Not Recommend for New Designs

List of Tables

Not Recommended for New Designs

BIST_pattern0 Address 1Bh 44 Table Built In Self-Test BIST Transmitter 16/20 bit User Programmable Pattern

BIST_pattern1 Address 1Ch 44
2125x-DSH-001-J

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived M21250G-12 Datasheet file may be downloaded here without warranties.

Datasheet ID: M21250G-12 646844