PCI-EXP2-E5G-U

PCI-EXP2-E5G-U Datasheet

PCI Express x1/x2/x4 Endpoint IP Core

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PCI-EXP2-E5G-U	PCI-EXP2-E5G-U (pdf)

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PCI Express x1/x2/x4 Endpoint IP Core User Guide FPGA-IPUG-02009 Version October 2016 PCI Express x1/x2/x4 Endpoint IP Core User Guide Contents Introduction Quick Facts PHY Data Link Layer Transaction Layer Configuration Space Top Level IP Functional Descriptions Overview Interface Transmit TLP Receive TLP Interface Using the Transmit and Receive Interfaces As a Completer As a Unsupported Request Generation Configuration Space Base Configuration Type0 Registers Power Management Capability Structure MSI Capability How to Enable/Disable MSI How to issue MSI PCI Express Capability Device Serial Number Capability Structure Advanced Error Reporting Capability Structure Handling of Configuration Wishbone Byte/Bit Ordering Error Handling Parameter Settings General Tab PCI Express Link Configuration Spec. Version Endpoint Include Master Loopback Data Include Wishbone Interface Configuration Registers Not PCS Pipe Options Tab Flow Control Tab Update Flow Control Generation Control Number of P TLPs Between UpdateFC Number of PD TLPs Between UpdateFC Number of NP TLPs Between Number of NPD TLPs Between UpdateFC Worst Case Number of 125 MHz Clock Cycles Between UpdateFC Initial Receive Credits Infinite PH Initial PH Credits Infinite PD Initial PD Credits 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009-1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009_1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide Regenerating an IP Core in Clarity Designer Flow for ECP5 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009-1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide Figures Figure PCI Express IP Core Technology and Figure PCI Express Core Implementation in LatticeECP3, ECP5 and EPC5-5G Figure PCI Express Figure Transmit Interface of 2.5G IP core Native x4 or 5G IP core Native x2, 3DW Header, 1 DW Data Figure Transmit Interface 2.5G IP core Native x4 or 5G IP core Native x2, 3DW Header, 2 DW Data Figure Transmit Interface 2.5G IP core Native x4 or 5G IP core Native x2, 4DW Header, 0 DW Figure Transmit Interface 2.5G IP core Native x4 or 5G IP core Native x2, 4DW Header, Odd Number of DWs Figure Transmit Interface 2.5G IP core Native x4 or 5G IP core Native x2, Burst of Two TLPs Figure Transmit Interface IP core Native x4 or 5G IP core Native x2, Nullified Figure Transmit Interface 2.5G IP Core Downgraded x1 or 5G IP core Downgraded x1 at Gen1 speed Figure Transmit Interface 2.5G IP core Downgraded x2, 5G IP core Native x2 at Gen 1 speed or Downgraded x1 at Gen2 Figure Transmit Interface 2.5G IP core Native x4 or 5G IP core Native x2, Posted Request with tx_ca_p-recheck Assertion 25 Figure Transmit Interface Native x1, 3DW Header, 1 DW Figure Transmit Interface Native x1, Burst of Two TLPs Figure Transmit Interface Native x1, Nullified TLP Figure Transmit Interface Native x1 Posted Request with tx_ca_p-recheck Figure Receive Interface, Clean Figure Receive Interface, ECRC Errored TLP Figure Receive Interface, Malformed Figure Receive Interface, Unsupported Request TLP Figure PCI Express IP Core General Figure PCI Express IP Core PCS Pipe Figure PCI Express IP Core Flow Control Options Figure PCI Express IP Core Configuration Space - 1 Figure PCI Express IP Core Configuration Space - 2 Figure IPexpress Tool Dialog Box Figure IPexpress Configuration GUI Figure LatticeECP3 PCI Express Core Directory Figure Clarity Designer GUI pci express endpoint core Figure PCI Express IP GUI Dialog Box Figure PCI Express Endpoint IP Core Configuration GUI Figure PCI Express Endpoint IP Core Clarity Designer Figure Clarity Designer Placed Figure Clarity Designer GUI Figure Clarity Designer Placed Modules pci express endpoint and extref Figure Clarity Designer DCU Figure Generating the IP Core Figure Directory Structure Figure Reset, Delete, Config, Expand and Collapse Placement of the IP Core Figure PCI Express x4 Core Evaluation Testbench Block Diagram Figure PCI Express x4 Core Testbench Using Two Figure PCI Express x4 Core Testbench with Third-Party VIP Figure LatticeECP3 PCI Express Clocking Scheme Figure ECP5 PCI Express Clocking Figure LatticeECP3 Device Arrays with Figure ECP5 Device Arrays with Figure Best Case Timing Diagram, Lattice Device with Respect to PERST# Figure Worst Case Timing Diagram, Lattice Device with Respect to PERST# Figure Example of Board Layout Concern with x4 Figure Implementation of x4 IP Core to Edge Fingers 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009_1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide Figure Implementation of x1 IP Core to Edge Fingers Figure PCI Express Endpoint Add In Tables Table PCI Express 2.5G IP Core Quick Table PCI Express 5G IP Core Quick Facts Table PCI Express IP Core Port Table Unsupported TLPs Which Can be Received by the IP Table Unsupported TLPs Which Can Be Received by the IP Table Wishbone Interface Memory Table Physical Layer Error Table Data Link Layer Error List Table Transaction Layer Error Table IP Core Parameters Table Total EBR Count Based on Max Payload Size 2.5G IP Core Table File List Table File List Table LatticeECP3 Power Up Timing Specifications Table ECP5 Power Up Timing Table LTSSM Counters Table Troubleshooting Table A.1. Resource Utilization Table A.2. Resource Utilization Table A.3. Resource Utilization Table A.4. Resource Utilization Table A.5. Resource Utilization Table B.1. Resource Utilization Table B.2. Resource Utilization 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009-1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide Introduction PCI Express is a high performance, fully scalable, well defined standard for a wide variety of computing and communications platforms. It has been defined to provide software compatibility with existing PCI drivers and operating systems. Being a packet based serial technology, PCI Express greatly reduces the number of required pins and simplifies board routing and manufacturing. PCI Express is a point-to-point technology, as opposed to the multidrop bus in PCI. Each PCI Express device has the advantage of full duplex communication with its link partner to greatly increase overall system bandwidth. The basic data rate for a single lane is double that of the 32 bit/33 MHz PCI bus. A four lane link has eight times the data rate in each direction of a conventional bus. Lattice’s PCI Express core provides a x1, x2 or x4 endpoint solution from the electrical SERDES interface to the transaction layer. This solution supports the LatticeECP3 , ECP5 and ECP5-5G device families. When used with the LatticeECP3, ECP5 and ECP5-5G family of devices, the PCI Express core is implemented using an extremely economical and high value FPGA platform. This users guide covers the following versions of the Lattice PCI Express Endpoint core: PCI Express 2.5G IP Core • The Native x4 Core targets the LatticeECP3 and ECP5 family of devices. • The x4 Downgraded x1 Core also targets the LatticeECP3 and ECP5 family. The x4 Downgraded x1 core is a x4 core that uses one channel of SERDES/PCS and a 64-bit data path for x1 link width. • The x4 Downgraded x2 Core also targets the LatticeECP3 and ECP5 family. The x4 Downgraded x2 core is a x4 core that uses two channels of SERDES/PCS and a 64-bit data path for x2 link width. • The Native x1 Core targets the LatticeECP3 and ECP5 family of devices. This is a reduced LUT count x1 core with a 16-bit data path. PCI Express 5G IP Core • The Native x2 Core targets the Lattice ECP5-5G device. The x2 core uses 2 channels of SERDES/PCS and a 64-bit data path for x2 link width. • The x2 Downgraded x1 Core targets the Lattice ECP5-5G device. The x2 Downgraded x1 core is a x2 core that uses 1 channel of SERDES/PCS and a 64-bit data path for x1 link width. Quick Facts Table provides quick facts about the Lattice PCI Express 2.5G x1/x2/x4 IP Core. Table PCI Express 2.5G IP Core Quick Facts PCI Express IP Configuration Native x4 Native x1 Downgraded x2 FPGA Families Supported LatticeECP3 and ECP5 IP Requirements Minimal Device Needed LFE317E7FN484C Wishbone Byte/Bit Ordering The write byte order for Wishbone is DAT_I = byte of N+2, lower byte of N+2, upper byte of N, lower byte of The read byte order for Wishbone is different depending on the address range. For an address range of 0x0000-0x0FFF accessing the PCI Express configuration space, the read byte ordering is: DAT_O = byte of N, upper byte of N, lower byte of N+2, upper byte of For an address range of 0x1000-101F accessing control and status registers inside the PCI Express IP core, the read byte ordering is DAT_O = byte of N+2, lower byte of N+2, upper byte of N, ,lower byte of The bit ordering within a byte is always The memory map for the Wishbone interface is provided in Table Table Wishbone Interface Memory Map Type Address hex Bits* Status 1008-100B 31:24 23:20 19:16 15:12 11:7 100C-100F 31:22 21:18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 Defaults 0 Description Reserved PHY LSM Status. For X1 Core [23:21] are Reserved. PHY Connection Status / Result of Receiver Detection. For X1 Core [19:17] are Reserved. PHY Receive/Rx Electrical Idle. For x1 Core [15:13] are Reserved. LTSSM State 0 DETECT,1 POLLING, 2 CONFIG, 3 - L0, 4 - L0s, 5 - L1, 6 - L2, 7 RECOVERY, 8 LOOPBACK, 9 HOTRST, 10 - DISABLED* DLL/Link Control SM Status [6] - DL Inactive State [5] - DL Init State [4] - DL Active State [3] - DL Up State Reserved LTSSM goto Loopback For x1 Core [21:19] are Reserved TLP Debug Mode TLP bypasses DLL & TRNC check. PHY/LTSSM Send Beacon Force LSM Status active Force Received Electrical Idle Force PHY Connection Status Force Disable Scrambler to PCS Disable scrambling bit in TS1/TS2 LTSSM go to Disable LTSSM go to Detect LTSSM go to HotReset LTSSM go to L0s LTSSM go to L1 LTSSM go to L2 LTSSM go to L0s and Tx FTS 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009_1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide 1010-101 31:30 29:16 14:10 1014-1017 31:18 Set in IP 17:11 10:0 1018-101B 31:18 Set in IP 17:11 10:0 101C-101F 31:18 Set in IP 17:11 10:0 1020-1023 Enable Relaxed Ordering Yes/No Maximum Link Width 1, 2, 4 Device Capabilities 2 Register [4:0] 00-1f 0000-ffff 00-ff 00-ff 00-ff Yes/No Yes/No Yes/No Yes/No Yes/No Yes/No 0000-ffff 0000-ffff Yes/No Yes/No 0000-ffff 0-3 00-ff 00-ff 00-ff 00-ff 00-ff 00-ff 00-ff 00-ff 00-ff 00-ff Yes/No 1-8 00-ff 1 or 2 128, 256, 512, 1024, 2048, 4096 Yes/No 1, 2, 4 00-1f 0000 00 No 0000 No 0003 Yes 1 00 1 128 Yes 4 11 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009_1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide Device Serial Number Device Serial Number Version Device Serial Number Advanced Error Reporting Use Advanced Error Reporting Advanced Error Reporting Version Include ECRC support Terminate All Config TLPs Terminate All Config TLPs User Extended Capability Structure Yes/No 1 Yes/No Yes/No 000-fff Yes/No 1 Yes/No Yes/No 000-fff No Disabled Yes Disabled The default values shown in the following pages are those used for the PCI Express reference design. IP core options for each tab are discussed in further detail. General Tab Figure 3-1 shows the contents of the General tab. Figure PCI Express IP Core General Options The General tab consists of the following parameters: PCI Express Link Configuration Specifies the link width and type of core to be used. 25G IP core • Native x4 - This is a x4 link width using a 64-bit data path. This configuration can dynamically downgraded to a x2 or x1 link width. • Downgraded x1 - This is a x1 link width using a 64-bit datapath. • Downgraded x2 - This is a x2 link width using a 64-bit datapath. • Native x1 - This is a x1 link width only using a 16-bit datapath. 5G IP core • Native x2 and Downgraded x1 using 64-bit datapath. 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009-1.7 Enable Relaxed Ordering Relaxed ordering is the default setting for PCI Express. If the PCI Express link does not support relaxed ordering then this checkbox should be cleared. This feature does not change the behavior of the core, only the setting of this bit in the PCI Express capability structure. The user will be required to ensure strict ordering is enforced by the transmitter. Maximum Link Width This option sets the maximum link width advertised by the endpoint. This control should match the intended link width of the endpoint. Device Capabilities 2 Register 4:0 This 5-bit field sets the Device Capabilities Register bits MSI Capability Structure Options These controls allow the user to include MSI and request a certain number of interrupts Use Message Signaled Interrupts This option includes MSI support in the IP core. Number of Messages Requested This number specifies how many MSIs will be requested by the endpoint of the system. The system will respond with how many interrupts have been provided. The number of interrupts provided can be found on the mm_enable port of the IP core. Advanced Error Reporting Options These controls allow the user to include AER. 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009_1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide Use Advanced Error Reporting This control will include AER in the IP core. AER is used to provide detailed information on the status of the PCI Express link and error TLPs. Advanced Error Reporting Version Indicates the version of the Advanced Error Reporting Capability. This number must always be set to 1 for v1.1. Device Serial Number Version Indicates the version of the Device Serial Number Capability. This number must always be set to 1 for v1.1. Device Serial Number This 64-bit value is provided in the IP core through the Device Serial Number Capability Structure. Power Management Capability Structure This section includes options for the Power Management Capability Structure. This structure is used to pass power information from the endpoint to the system. If power management is not going to be used by the solution then all fields can remain in the default state. Power Management Cap Reg 31:16 This field sets the Power Management Capabilities PMC register bits Data Scale Multiplier This control sets the Data Scale Multiplier used by system to multiplier the power numbers provided by the end- point. Power Consumed in D0, D1, D2, D3 These controls allow the user to specify the power consumed by the endpoint in each power state D0, D1, D2, and D3. The user specifies Watts as an 8-bit hex number. Power Dissipated in D0, D1, D2, D3 These controls allow the user to specify the power dissipated by the endpoint in each power state D0, D1, D2, and D3. The user specifies Watts as an 8-bit hex number. Terminate All Configuration TLPs If enabled, this control will allow the core to terminate all Configuration requests. The user will not need to handle any configuration requests in the user's design. User Extended Capability Structure This control defines the pointer to additional non-extended capability implemented in the user application design. The default is 0 to indicate there is no user implemented non-extended capability. If the pointer is set to a non-zero value, “Terminate All Config TLPs” must not be selected. 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009-1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide Users simulating a multi-lane core at the serial level should give consideration to lane ordering. Lane ordering is dependent on the layout of the chip on a board. Alternative Testbench Approach In order to create a testbench which meets the user's needs, the data must be sourced across the serial PCI Express lanes. The user must also have the ability to create the source traffic that will be pushed over the PCI Express link. This solution can be created by the user using the Lattice core. 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009-1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide Figure shows a block diagram that illustrates a new testbench orientation which can be created by the user. New Testb ench Lattice Device User Design PCI Express IP Core PCI Express IP Core Tx BFM Rx BFM Figure PCI Express x4 Core Testbench Using Two Cores Use two PCI Express cores. The first PCI Express core is used in the design and the second PCI Express core is used as a driver. The user needs to use the no_pcie_train command to force the L0 state of the LTSSM in both cores. When IP Core does not use the Wishbone bus, the bench must force no_pcie_train port on the IP to “1” to set LTSSM to L0 status. When the Wishbone bus is implemented, there is no no_pcie_train port on the IP Core. Therefore, the bench must set the “LTSSM no training” register to force LTSSM to L0 status. Whether or not the Wishbone bus is implemented, the bench must force LTSSM to L0 after both LTSSM state machines of transmitter and receiver are moved to Configuration status 4’d2 . As a result, the second core can then be used as a traffic separator. The second core is created to be the opposite of the design core. Thus an upstream port will talk with a downstream port and vice versa. The second core is used as a traffic generator. User-written BFMs can be created to source and sink PCI Express TLPs to exercise the design. An issue associated with this test bench solution is that the run time tends to be long since the test bench will now include two PCS/SERDES cores. There is a large number of functions contained in both of the IP blocks which will slow down the simulation. Another issue is that the Lattice PCI Express solution is being used to verify the Lattice PCI Express solution. This risk is mitigated by the fact that Lattice is PCI-SIG compliant see the Integrator's list at and a third party verification IP was used during the development process. It should also be noted that this approach does not allow for PCI Express layer error insertion. Third Party Verification IP The ideal solution for system verification is to use a third party verification IP. These solutions are built specifically for the user’s needs and supply the BFMs and provide easy to use interfaces to create TLP traffic. Also, models are behavioral, gate level, or even RTL to increase the simulation speed. Lattice has chosen the Synopsys PCI Express verification IP for development of the PCI Express core, as shown in Figure There are other third party vendors for PCI Express including and 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009_1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide Third-Party Testbench Lattice Device User Design PCI Express IP Core Third-Pa rt y PCI Express User Commands Figure PCI Express x4 Core Testbench with Third-Party VIP If desired, an independent Bus Functional Model can be modified to emulate a user’s environment. This option is highly recommended. FPGA Design Implementation for LatticeECP3 Devices This section provides information on implementing the PCI Express IP core in a complete FPGA design. Topics covered include how to set up the IP core for various link width combinations, clocking schemes and physically locating the IP core within the FPGA. Setting Up the Core This section describes how to set up the PCI Express core for various link width combinations. The user must pro- vide a different PCS/SERDES autoconfig file based on the link width and the flipping of the lanes. The PCS/SERDES memory map is initially configured during bit stream loading using the autoconfig file generated with the IPexpress tool. Note that transactions shown display data in hexadecimal format with bit 0 as the MSb. Setting Up for Native x4 No Flip This is the default condition that is created from the IPexpress tool. Simply use the autoconfig file to setup the channels. The flip_lanes port should be tied low. Setting Up for Native x4 Flipped No changes required. Simply use the pcs_pcie_8b_x4.txt file generated from the IPexpress tool. Setting Up for Downgraded x1 No Flip If the design will be using only a single channel and it is not flipped then Channels 1, 2, and 3 need to be powered down. Change the following lines from the pcs_pipe_x4.txt file. CH0_MODE "GROP1" CH1_MODE "GROUP1" CH2_MODE "GROUP1" CH3_MODE "GROUP1" CH0_MODE "GROUP1" CH1_MODE "DISABLE" CH2_MODE "DISABLE" 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009-1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide CH3_MODE "DISABLE" Ordering Part Number The Ordering Part Number OPN for the PCI Express x1 Endpoint IP core targeting LatticeECP3 devices is PCI-EXP1-E3U3. LatticeECP3 Utilization Native x4 Table A.2 lists the resource utilization for the PCI Express x4 Endpoint core implemented in a LatticeECP3 FPGA. Table A.2. Resource Utilization* IPexpress Configuration Native x4 Slices 8799 LUTs 12169 Registers 9796 sysMEM EBRs 11 Note Performance and utilization data are generated targeting an LFE3-95E-7FN1156CES using Lattice Diamond software. Performance might vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family. When the x4 core downgrades to x1 mode, utilization and performance results for x1 are identical to x4 mode. Ordering Part Number The Ordering Part Number OPN for the PCI Express x4 Endpoint IP core targeting LatticeECP3 devices is PCI-EXP4-E3U3. ECP5 Utilization Native x1 Table A.3 shows the resource utilization for the PCI Express x1 Endpoint core implemented in a ECP5 FPGA. Table A.3. Resource Utilization Clarity Configuration Native x1 Slices 4270 LUTs 6207 Registers 4188 sysMEM EBRs 4 Note Performance and utilization data are generated targeting LFE5UM-85E-7MG756C using Lattice Diamond software. Performance might vary when using a different software version or targeting a different device density or speed grade within the ECP5 family. Ordering Part Number The Ordering Part Number OPN for the PCI Express x1 Endpoint IP core targeting ECP5 devices is PCI-EXP1-E5-U or PCI-EXP1-E5-UT. 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009_1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide ECP5 Utilization Native x4 Table A.4 shows the resource utilization for the PCI Express x4 Endpoint core implemented in a ECP5 FPGA. Table A.4. Resource Utilization Clarity Configuration Native x4 Slices 9384 LUTs 13906 Registers 9763 sysMEM EBRs 11 Note Performance and utilization data are generated targeting LFE5UM-85E-7MG756C using Lattice Diamond software. Performance might vary when using a different software version or targeting a different device density or speed grade within the ECP5 family. Ordering Part Number The Ordering Part Number OPN for the PCI Express x4 Endpoint IP core targeting ECP5 devices isPCI-EXP4-E5-U or PCI-EXP4-E5-UT. ECP5 Utilization Downgraded x2 Table A.5 shows the resource utilization for the PCI Express x2 Endpoint core implemented in a ECP5 FPGA. Table A.5. Resource Utilization Clarity Configuration x4 Downgraded x2 Slices 8645 LUTs 12911 Registers 8999 sysMEM EBRs 11 Note Performance and utilization data are generated targeting LFE5UM-85E-7MG756C using Lattice Diamond software. Performance might vary when using a different software version or targeting a different device density or speed grade within the ECP5 family. Ordering Part Number The Ordering Part Number OPN for the PCI Express x2 Endpoint IP core targeting ECP5 devices is PCI-EXP4-E5-U or PCI-EXP4-E5-UT. 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009-1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide Appendix B. Resource Utilization of PCI Express 5G IP Core This appendix provides resource utilization information for Lattice FPGAs using the PCI Express 5G IP core. The Clarity Designer for ECP5-5G devices tool is the Lattice IP configuration utility, and is included as a standard feature of the Diamond design tools. Details regarding the usage of the IPexpress and Clarity tool can be found in Diamond help system. For more information on the Diamond design tools, visit the Lattice website at: ECP5-5G Utilization Downgraded x1 Table B.1 shows the resource utilization for the PCI Express x1 5G Endpoint core implemented in a ECP5-5G FPGA. Table B.1. Resource Utilization Clarity Configuration x2 Downgraded x1 Slices 9307 LUTs 13378 Registers 9354 sysMEM EBRs 7 Note Performance and utilization data are generated targeting LFE5UM5G-85F-8BG756C using Lattice Diamond software. Performance might vary when using a different software version or targeting a different device density or speed grade within the ECP5-5G family. Ordering Part Number The Ordering Part Number OPN for the PCI Express x1 5G Endpoint IP core targeting ECP5-5G devices is PCI-EXP2E5G-U or PCI-EXP2-E5G-UT. ECP5-5G Utilization Native x2 Table B.2 shows the resource utilization for the PCI Express x2 5G Endpoint core implemented in a ECP5-5G FPGA. Table B.2. Resource Utilization Clarity Configuration1 Native x2 Slices 10486 LUTs 14909 Registers 10928 sysMEM EBRs 7 *Note Performance and utilization data are generated targeting LFE5UM5G-85F-8BG756C using Lattice Diamond software. Performance might vary when using a different software version or targeting a different device density within the ECP5-5G family. Ordering Part Number The Ordering Part Number OPN for the PCI Express x2 5G Endpoint IP core targeting ECP5-5G devices is PCI-EXP2E5G-U or PCI-EXP2-E5G-UT. 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009_1.7 PCI Express x1/x2/x4 Endpoint IP Core User Guide Date October 2016 May 2016 April 2015 November 2014 April 2014 January 2014 September 2013 Document Version IP Core Version Package Name Change Summary Beta PCI Express 5G Endpoint Beta PCI Express 5G Endpoint PCI Express Endpoint 6.0_asr 6.0_sbp 6.0ea Added support for ECP5-5G. Updated Lattice Technical Support section Added additional fabric pipeline registers to EBR output paths. Added mask logic to ECP5 RxValid signal from pipe wrapper. Added SoftLoL logic to ECP5 PIPE wrapper. Added LSE support for ECP5 devices. Added support for both LatticeECP3 and ECP5 in same package IP core version Updated device name to ECP5. Added support for Clarity Designer flow. Initial EAP release. 2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. FPGA-IPUG-02009-1.7 7th Floor, 111 SW 5th Avenue Portland, OR 97204, USA T

PDF Datasheet Preview

PCI Express x1/x2/x4 Endpoint IP Core

User Guide

FPGA-IPUG-02009 Version

October 2016

PCI Express x1/x2/x4 Endpoint IP Core User Guide

Contents

Introduction Quick Facts PHY Data Link Layer Transaction Layer Configuration Space Top Level IP
Functional Descriptions Overview Interface Transmit TLP Receive TLP Interface Using the Transmit and Receive Interfaces As a Completer As a Unsupported Request Generation Configuration Space Base Configuration Type0 Registers Power Management Capability Structure MSI Capability How to Enable/Disable MSI How to issue MSI PCI Express Capability Device Serial Number Capability Structure Advanced Error Reporting Capability Structure Handling of Configuration Wishbone Byte/Bit Ordering Error Handling

Parameter Settings General Tab PCI Express Link Configuration Spec. Version Endpoint Include Master Loopback Data Include Wishbone Interface Configuration Registers Not PCS Pipe Options Tab Flow Control Tab Update Flow Control Generation Control Number of P TLPs Between UpdateFC Number of PD TLPs Between UpdateFC Number of NP TLPs Between Number of NPD TLPs Between UpdateFC Worst Case Number of 125 MHz Clock Cycles Between UpdateFC Initial Receive Credits Infinite PH Initial PH Credits Infinite PD Initial PD Credits
2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-IPUG-02009-1.7

PCI Express x1/x2/x4 Endpoint IP Core User Guide
2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-IPUG-02009_1.7

PCI Express x1/x2/x4 Endpoint IP Core User Guide

Regenerating an IP Core in Clarity Designer Flow for ECP5
2016 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-IPUG-02009-1.7

PCI Express x1/x2/x4 Endpoint IP Core User Guide

Figures

Figure PCI Express IP Core Technology and Figure PCI Express Core Implementation in LatticeECP3, ECP5 and EPC5-5G Figure PCI Express Figure Transmit Interface of 2.5G IP core Native x4 or 5G IP core Native x2, 3DW Header, 1 DW Data Figure Transmit Interface 2.5G IP core Native x4 or 5G IP core Native x2, 3DW Header, 2 DW Data Figure Transmit Interface 2.5G IP core Native x4 or 5G IP core Native x2, 4DW Header, 0 DW Figure Transmit Interface 2.5G IP core Native x4 or 5G IP core Native x2, 4DW Header, Odd Number of DWs Figure Transmit Interface 2.5G IP core Native x4 or 5G IP core Native x2, Burst of Two TLPs Figure Transmit Interface IP core Native x4 or 5G IP core Native x2, Nullified Figure Transmit Interface 2.5G IP Core Downgraded x1 or 5G IP core Downgraded x1 at Gen1 speed Figure Transmit Interface 2.5G IP core Downgraded x2, 5G IP core Native x2 at Gen 1 speed or Downgraded x1 at Gen2 Figure Transmit Interface 2.5G IP core Native x4 or 5G IP core Native x2, Posted Request with tx_ca_p-recheck Assertion 25 Figure Transmit Interface Native x1, 3DW Header, 1 DW Figure Transmit Interface Native x1, Burst of Two TLPs Figure Transmit Interface Native x1, Nullified TLP Figure Transmit Interface Native x1 Posted Request with tx_ca_p-recheck Figure Receive Interface, Clean Figure Receive Interface, ECRC Errored TLP Figure Receive Interface, Malformed Figure Receive Interface, Unsupported Request TLP Figure PCI Express IP Core General Figure PCI Express IP Core PCS Pipe Figure PCI Express IP Core Flow Control Options Figure PCI Express IP Core Configuration Space - 1 Figure PCI Express IP Core Configuration Space - 2 Figure IPexpress Tool Dialog Box Figure IPexpress Configuration GUI Figure LatticeECP3 PCI Express Core Directory Figure Clarity Designer GUI pci express endpoint core Figure PCI Express IP GUI Dialog Box Figure PCI Express Endpoint IP Core Configuration GUI Figure PCI Express Endpoint IP Core Clarity Designer Figure Clarity Designer Placed Figure Clarity Designer GUI Figure Clarity Designer Placed Modules pci express endpoint and extref Figure Clarity Designer DCU Figure Generating the IP Core Figure Directory Structure Figure Reset, Delete, Config, Expand and Collapse Placement of the IP Core Figure PCI Express x4 Core Evaluation Testbench Block Diagram Figure PCI Express x4 Core Testbench Using Two Figure PCI Express x4 Core Testbench with Third-Party VIP Figure LatticeECP3 PCI Express Clocking Scheme Figure ECP5 PCI Express Clocking Figure LatticeECP3 Device Arrays with Figure ECP5 Device Arrays with Figure Best Case Timing Diagram, Lattice Device with Respect to PERST# Figure Worst Case Timing Diagram, Lattice Device with Respect to PERST# Figure Example of Board Layout Concern with x4 Figure Implementation of x4 IP Core to Edge Fingers
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PCI Express x1/x2/x4 Endpoint IP Core User Guide

Figure Implementation of x1 IP Core to Edge Fingers Figure PCI Express Endpoint Add In

Tables

Table PCI Express 2.5G IP Core Quick Table PCI Express 5G IP Core Quick Facts Table PCI Express IP Core Port Table Unsupported TLPs Which Can be Received by the IP Table Unsupported TLPs Which Can Be Received by the IP Table Wishbone Interface Memory Table Physical Layer Error Table Data Link Layer Error List Table Transaction Layer Error Table IP Core Parameters Table Total EBR Count Based on Max Payload Size 2.5G IP Core Table File List Table File List Table LatticeECP3 Power Up Timing Specifications Table ECP5 Power Up Timing Table LTSSM Counters Table Troubleshooting Table A.1. Resource Utilization Table A.2. Resource Utilization Table A.3. Resource Utilization Table A.4. Resource Utilization Table A.5. Resource Utilization Table B.1. Resource Utilization Table B.2. Resource Utilization
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PCI Express x1/x2/x4 Endpoint IP Core User Guide

Introduction

PCI Express is a high performance, fully scalable, well defined standard for a wide variety of computing and communications platforms. It has been defined to provide software compatibility with existing PCI drivers and operating systems. Being a packet based serial technology, PCI Express greatly reduces the number of required pins and simplifies board routing and manufacturing. PCI Express is a point-to-point technology, as opposed to the multidrop bus in PCI. Each PCI Express device has the advantage of full duplex communication with its link partner to greatly increase overall system bandwidth. The basic data rate for a single lane is double that of the 32 bit/33 MHz PCI bus. A four lane link has eight times the data rate in each direction of a conventional bus.

Lattice’s PCI Express core provides a x1, x2 or x4 endpoint solution from the electrical SERDES interface to the transaction layer. This solution supports the LatticeECP3 , ECP5 and ECP5-5G device families. When used with the LatticeECP3, ECP5 and ECP5-5G family of devices, the PCI Express core is implemented using an extremely economical and high value FPGA platform.

This users guide covers the following versions of the Lattice PCI Express Endpoint core:

PCI Express 2.5G IP Core
• The Native x4 Core targets the LatticeECP3 and ECP5 family of devices.
• The x4 Downgraded x1 Core also targets the LatticeECP3 and ECP5 family. The x4 Downgraded x1 core is a x4 core
that uses one channel of SERDES/PCS and a 64-bit data path for x1 link width.
• The x4 Downgraded x2 Core also targets the LatticeECP3 and ECP5 family. The x4 Downgraded x2 core is a x4 core
that uses two channels of SERDES/PCS and a 64-bit data path for x2 link width.
• The Native x1 Core targets the LatticeECP3 and ECP5 family of devices. This is a reduced LUT count x1 core with a
16-bit data path.

PCI Express 5G IP Core
• The Native x2 Core targets the Lattice ECP5-5G device. The x2 core uses 2 channels of SERDES/PCS and a 64-bit
data path for x2 link width.
• The x2 Downgraded x1 Core targets the Lattice ECP5-5G device. The x2 Downgraded x1 core is a x2 core that uses
1 channel of SERDES/PCS and a 64-bit data path for x1 link width.

Quick Facts

Table provides quick facts about the Lattice PCI Express 2.5G x1/x2/x4 IP Core.

Table PCI Express 2.5G IP Core Quick Facts

PCI Express IP Configuration

Native x4

Native x1

Downgraded x2

FPGA Families Supported

LatticeECP3 and ECP5

IP Requirements

Minimal Device Needed

LFE317E7FN484C
Wishbone Byte/Bit Ordering

The write byte order for Wishbone is DAT_I = byte of N+2, lower byte of N+2, upper byte of N, lower byte of
The read byte order for Wishbone is different depending on the address range. For an address range of 0x0000-0x0FFF accessing the PCI Express configuration space, the read byte ordering is:

DAT_O = byte of N, upper byte of N, lower byte of N+2, upper byte of For an address range of 0x1000-101F accessing control and status registers inside the PCI Express IP core, the read
byte ordering is DAT_O = byte of N+2, lower byte of N+2, upper byte of N, ,lower byte of The bit ordering within a byte is always The memory map for the Wishbone interface is provided in Table

Table Wishbone Interface Memory Map

Type

Address hex

Bits*

Status
1008-100B
31:24
23:20
19:16
15:12
11:7
100C-100F
31:22
21:18
17 16 15 14 13 12 11 10 9 8 7 6 5 4

Defaults 0

Description Reserved PHY LSM Status. For X1 Core [23:21] are Reserved. PHY Connection Status / Result of Receiver Detection. For X1 Core [19:17] are Reserved. PHY Receive/Rx Electrical Idle. For x1 Core [15:13] are Reserved. LTSSM State 0 DETECT,1 POLLING, 2 CONFIG, 3 - L0, 4 - L0s, 5 - L1, 6 - L2, 7 RECOVERY, 8 LOOPBACK, 9 HOTRST, 10 - DISABLED* DLL/Link Control SM Status [6] - DL Inactive State [5] - DL Init State [4] - DL Active State [3] - DL Up State Reserved LTSSM goto Loopback For x1 Core [21:19] are Reserved TLP Debug Mode TLP bypasses DLL & TRNC check. PHY/LTSSM Send Beacon Force LSM Status active Force Received Electrical Idle Force PHY Connection Status Force Disable Scrambler to PCS Disable scrambling bit in TS1/TS2 LTSSM go to Disable LTSSM go to Detect LTSSM go to HotReset LTSSM go to L0s LTSSM go to L1 LTSSM go to L2 LTSSM go to L0s and Tx FTS
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PCI Express x1/x2/x4 Endpoint IP Core User Guide
1010-101
31:30
29:16
14:10
1014-1017
31:18

Set in IP
17:11
10:0
1018-101B
31:18

Set in IP
17:11
10:0
101C-101F
31:18

Set in IP
17:11
10:0
1020-1023
Enable Relaxed Ordering

Yes/No

Maximum Link Width
1, 2, 4

Device Capabilities 2 Register [4:0]
00-1f
0000-ffff
00-ff 00-ff 00-ff Yes/No Yes/No Yes/No Yes/No Yes/No Yes/No 0000-ffff 0000-ffff Yes/No Yes/No
0000-ffff
0-3 00-ff 00-ff 00-ff 00-ff 00-ff 00-ff 00-ff 00-ff 00-ff 00-ff

Yes/No 1-8
00-ff 1 or 2 128, 256, 512, 1024, 2048, 4096 Yes/No 1, 2, 4 00-1f
0000
00 No 0000 No
0003

Yes 1
00 1 128

Yes 4 11
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PCI Express x1/x2/x4 Endpoint IP Core User Guide

Device Serial Number Device Serial Number Version Device Serial Number

Advanced Error Reporting Use Advanced Error Reporting Advanced Error Reporting Version Include ECRC support Terminate All Config TLPs Terminate All Config TLPs User Extended Capability Structure

Yes/No 1

Yes/No

Yes/No 000-fff

Yes/No 1

Yes/No

Yes/No 000-fff

No Disabled

Yes Disabled

The default values shown in the following pages are those used for the PCI Express reference design. IP core options for each tab are discussed in further detail.

General Tab

Figure 3-1 shows the contents of the General tab.

Figure PCI Express IP Core General Options

The General tab consists of the following parameters:

PCI Express Link Configuration

Specifies the link width and type of core to be used. 25G IP core
• Native x4 - This is a x4 link width using a 64-bit data path. This configuration can dynamically downgraded to a x2
or x1 link width.
• Downgraded x1 - This is a x1 link width using a 64-bit datapath.
• Downgraded x2 - This is a x2 link width using a 64-bit datapath.
• Native x1 - This is a x1 link width only using a 16-bit datapath. 5G IP core
• Native x2 and Downgraded x1 using 64-bit datapath.
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Enable Relaxed Ordering
Relaxed ordering is the default setting for PCI Express. If the PCI Express link does not support relaxed ordering then this checkbox should be cleared. This feature does not change the behavior of the core, only the setting of this bit in the PCI Express capability structure. The user will be required to ensure strict ordering is enforced by the transmitter.

Maximum Link Width

This option sets the maximum link width advertised by the endpoint. This control should match the intended link width of the endpoint.

Device Capabilities 2 Register 4:0

This 5-bit field sets the Device Capabilities Register bits

MSI Capability Structure Options

These controls allow the user to include MSI and request a certain number of interrupts

Use Message Signaled Interrupts

This option includes MSI support in the IP core.

Number of Messages Requested

This number specifies how many MSIs will be requested by the endpoint of the system. The system will respond with how many interrupts have been provided. The number of interrupts provided can be found on the mm_enable port of the IP core.

Advanced Error Reporting Options

These controls allow the user to include AER.
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PCI Express x1/x2/x4 Endpoint IP Core User Guide

Use Advanced Error Reporting

This control will include AER in the IP core. AER is used to provide detailed information on the status of the PCI Express link and error TLPs.

Advanced Error Reporting Version

Indicates the version of the Advanced Error Reporting Capability. This number must always be set to 1 for v1.1.

Device Serial Number Version

Indicates the version of the Device Serial Number Capability. This number must always be set to 1 for v1.1.

Device Serial Number

This 64-bit value is provided in the IP core through the Device Serial Number Capability Structure.

Power Management Capability Structure

This section includes options for the Power Management Capability Structure. This structure is used to pass power information from the endpoint to the system. If power management is not going to be used by the solution then all fields can remain in the default state.

Power Management Cap Reg 31:16

This field sets the Power Management Capabilities PMC register bits

Data Scale Multiplier

This control sets the Data Scale Multiplier used by system to multiplier the power numbers provided by the end- point.

Power Consumed in D0, D1, D2, D3

These controls allow the user to specify the power consumed by the endpoint in each power state D0, D1, D2, and D3. The user specifies Watts as an 8-bit hex number.

Power Dissipated in D0, D1, D2, D3

These controls allow the user to specify the power dissipated by the endpoint in each power state D0, D1, D2, and D3. The user specifies Watts as an 8-bit hex number.

Terminate All Configuration TLPs

If enabled, this control will allow the core to terminate all Configuration requests. The user will not need to handle any configuration requests in the user's design.

User Extended Capability Structure

This control defines the pointer to additional non-extended capability implemented in the user application design. The default is 0 to indicate there is no user implemented non-extended capability. If the pointer is set to a non-zero value, “Terminate All Config TLPs” must not be selected.
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PCI Express x1/x2/x4 Endpoint IP Core User Guide
Users simulating a multi-lane core at the serial level should give consideration to lane ordering. Lane ordering is dependent on the layout of the chip on a board.

Alternative Testbench Approach

In order to create a testbench which meets the user's needs, the data must be sourced across the serial PCI Express lanes. The user must also have the ability to create the source traffic that will be pushed over the PCI Express link. This solution can be created by the user using the Lattice core.
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PCI Express x1/x2/x4 Endpoint IP Core User Guide

Figure shows a block diagram that illustrates a new testbench orientation which can be created by the user.

New Testb ench Lattice Device

User Design

PCI Express IP Core

PCI Express IP Core

Tx BFM Rx BFM

Figure PCI Express x4 Core Testbench Using Two Cores

Use two PCI Express cores. The first PCI Express core is used in the design and the second PCI Express core is used as a driver. The user needs to use the no_pcie_train command to force the L0 state of the LTSSM in both cores. When IP Core does not use the Wishbone bus, the bench must force no_pcie_train port on the IP to “1” to set LTSSM to L0 status. When the Wishbone bus is implemented, there is no no_pcie_train port on the IP Core. Therefore, the bench must set the “LTSSM no training” register to force LTSSM to L0 status. Whether or not the Wishbone bus is implemented, the bench must force LTSSM to L0 after both LTSSM state machines of transmitter and receiver are moved to Configuration status 4’d2 . As a result, the second core can then be used as a traffic separator. The second core is created to be the opposite of the design core. Thus an upstream port will talk with a downstream port and vice versa. The second core is used as a traffic generator. User-written BFMs can be created to source and sink PCI Express TLPs to exercise the design. An issue associated with this test bench solution is that the run time tends to be long since the test bench will now include two PCS/SERDES cores. There is a large number of functions contained in both of the IP blocks which will slow down the simulation. Another issue is that the Lattice PCI Express solution is being used to verify the Lattice PCI Express solution. This risk is mitigated by the fact that Lattice is PCI-SIG compliant see the Integrator's list at and a third party verification IP was used during the development process. It should also be noted that this approach does not allow for PCI Express layer error insertion.

Third Party Verification IP

The ideal solution for system verification is to use a third party verification IP. These solutions are built specifically for the user’s needs and supply the BFMs and provide easy to use interfaces to create TLP traffic. Also, models are behavioral, gate level, or even RTL to increase the simulation speed. Lattice has chosen the Synopsys PCI Express verification IP for development of the PCI Express core, as shown in Figure There are other third party vendors for PCI Express including and
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PCI Express x1/x2/x4 Endpoint IP Core User Guide

Third-Party Testbench Lattice Device

User Design

PCI Express IP Core

Third-Pa rt y PCI Express

User Commands

Figure PCI Express x4 Core Testbench with Third-Party VIP

If desired, an independent Bus Functional Model can be modified to emulate a user’s environment. This option is highly recommended.

FPGA Design Implementation for LatticeECP3 Devices

This section provides information on implementing the PCI Express IP core in a complete FPGA design. Topics covered include how to set up the IP core for various link width combinations, clocking schemes and physically locating the IP core within the FPGA.

Setting Up the Core

This section describes how to set up the PCI Express core for various link width combinations. The user must pro- vide a different PCS/SERDES autoconfig file based on the link width and the flipping of the lanes. The PCS/SERDES memory map is initially configured during bit stream loading using the autoconfig file generated with the IPexpress tool. Note that transactions shown display data in hexadecimal format with bit 0 as the MSb.

Setting Up for Native x4 No Flip

This is the default condition that is created from the IPexpress tool. Simply use the autoconfig file to setup the channels. The flip_lanes port should be tied low.

Setting Up for Native x4 Flipped

No changes required. Simply use the pcs_pcie_8b_x4.txt file generated from the IPexpress tool.

Setting Up for Downgraded x1 No Flip

If the design will be using only a single channel and it is not flipped then Channels 1, 2, and 3 need to be powered down. Change the following lines from the pcs_pipe_x4.txt file. CH0_MODE "GROP1" CH1_MODE "GROUP1" CH2_MODE "GROUP1" CH3_MODE "GROUP1"

CH0_MODE "GROUP1" CH1_MODE "DISABLE" CH2_MODE "DISABLE"
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PCI Express x1/x2/x4 Endpoint IP Core User Guide

CH3_MODE "DISABLE"
Ordering Part Number
The Ordering Part Number OPN for the PCI Express x1 Endpoint IP core targeting LatticeECP3 devices is PCI-EXP1-E3U3.

LatticeECP3 Utilization Native x4

Table A.2 lists the resource utilization for the PCI Express x4 Endpoint core implemented in a LatticeECP3 FPGA.

Table A.2. Resource Utilization*

IPexpress Configuration Native x4

Slices 8799

LUTs 12169

Registers 9796
sysMEM EBRs 11
*Note Performance and utilization data are generated targeting an LFE3-95E-7FN1156CES using Lattice Diamond software. Performance might vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family. When the x4 core downgrades to x1 mode, utilization and performance results for x1 are identical to x4 mode.
Ordering Part Number
The Ordering Part Number OPN for the PCI Express x4 Endpoint IP core targeting LatticeECP3 devices is PCI-EXP4-E3U3.

ECP5 Utilization Native x1

Table A.3 shows the resource utilization for the PCI Express x1 Endpoint core implemented in a ECP5 FPGA.

Table A.3. Resource Utilization*

Clarity Configuration Native x1

Slices 4270

LUTs 6207

Registers 4188
sysMEM EBRs 4
*Note Performance and utilization data are generated targeting LFE5UM-85E-7MG756C using Lattice Diamond software. Performance might vary when using a different software version or targeting a different device density or speed grade within the ECP5 family.
Ordering Part Number
The Ordering Part Number OPN for the PCI Express x1 Endpoint IP core targeting ECP5 devices is PCI-EXP1-E5-U or PCI-EXP1-E5-UT.
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PCI Express x1/x2/x4 Endpoint IP Core User Guide

ECP5 Utilization Native x4

Table A.4 shows the resource utilization for the PCI Express x4 Endpoint core implemented in a ECP5 FPGA.

Table A.4. Resource Utilization*

Clarity Configuration Native x4

Slices 9384

LUTs 13906

Registers 9763
sysMEM EBRs 11
*Note Performance and utilization data are generated targeting LFE5UM-85E-7MG756C using Lattice Diamond software. Performance might vary when using a different software version or targeting a different device density or speed grade within the ECP5 family.
Ordering Part Number
The Ordering Part Number OPN for the PCI Express x4 Endpoint IP core targeting ECP5 devices isPCI-EXP4-E5-U or PCI-EXP4-E5-UT.

ECP5 Utilization Downgraded x2

Table A.5 shows the resource utilization for the PCI Express x2 Endpoint core implemented in a ECP5 FPGA.

Table A.5. Resource Utilization*

Clarity Configuration x4 Downgraded x2

Slices 8645

LUTs 12911

Registers 8999
sysMEM EBRs 11
*Note Performance and utilization data are generated targeting LFE5UM-85E-7MG756C using Lattice Diamond software. Performance might vary when using a different software version or targeting a different device density or speed grade within the ECP5 family.
Ordering Part Number
The Ordering Part Number OPN for the PCI Express x2 Endpoint IP core targeting ECP5 devices is PCI-EXP4-E5-U or PCI-EXP4-E5-UT.
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PCI Express x1/x2/x4 Endpoint IP Core User Guide

Appendix B. Resource Utilization of PCI Express 5G IP Core

This appendix provides resource utilization information for Lattice FPGAs using the PCI Express 5G IP core.

The Clarity Designer for ECP5-5G devices tool is the Lattice IP configuration utility, and is included as a standard feature of the Diamond design tools. Details regarding the usage of the IPexpress and Clarity tool can be found in Diamond help system. For more information on the Diamond design tools, visit the Lattice website at:

ECP5-5G Utilization Downgraded x1

Table B.1 shows the resource utilization for the PCI Express x1 5G Endpoint core implemented in a ECP5-5G FPGA.

Table B.1. Resource Utilization*

Clarity Configuration x2 Downgraded x1

Slices 9307

LUTs 13378

Registers 9354
sysMEM EBRs 7
*Note Performance and utilization data are generated targeting LFE5UM5G-85F-8BG756C using Lattice Diamond software. Performance might vary when using a different software version or targeting a different device density or speed grade within the ECP5-5G family.
Ordering Part Number
The Ordering Part Number OPN for the PCI Express x1 5G Endpoint IP core targeting ECP5-5G devices is PCI-EXP2E5G-U or PCI-EXP2-E5G-UT.

ECP5-5G Utilization Native x2

Table B.2 shows the resource utilization for the PCI Express x2 5G Endpoint core implemented in a ECP5-5G FPGA.

Table B.2. Resource Utilization*

Clarity Configuration1 Native x2

Slices 10486

LUTs 14909

Registers 10928
sysMEM EBRs 7
*Note Performance and utilization data are generated targeting LFE5UM5G-85F-8BG756C using Lattice Diamond software. Performance might vary when using a different software version or targeting a different device density within the ECP5-5G family.
Ordering Part Number
The Ordering Part Number OPN for the PCI Express x2 5G Endpoint IP core targeting ECP5-5G devices is PCI-EXP2E5G-U or PCI-EXP2-E5G-UT.
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PCI Express x1/x2/x4 Endpoint IP Core User Guide

Date October 2016

May 2016

April 2015 November 2014

April 2014 January 2014 September 2013

Document Version

IP Core Version Package Name

Change Summary

Beta

PCI Express 5G

Endpoint

Beta

PCI Express 5G

Endpoint

PCI Express

Endpoint
6.0_asr 6.0_sbp 6.0ea

Added support for ECP5-5G.

Updated Lattice Technical Support section Added additional fabric pipeline registers to EBR output paths. Added mask logic to ECP5 RxValid signal from pipe wrapper. Added SoftLoL logic to ECP5 PIPE wrapper. Added LSE support for ECP5 devices. Added support for both LatticeECP3 and ECP5 in same package IP core version Updated device name to ECP5. Added support for Clarity Designer flow. Initial EAP release.
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Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived PCI-EXP2-E5G-U Datasheet file may be downloaded here without warranties.

Datasheet ID: PCI-EXP2-E5G-U 645499