ORSO42G5-EV

ORSO42G5-EV Datasheet

ORT/ORSO42G5 High-Speed SERDES Board

Part	Datasheet
ORSO42G5-EV	ORSO42G5-EV (pdf)

Related Parts	Information
ORT42G5-EV	ORT42G5-EV

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ORT/ORSO42G5 High-Speed SERDES Board User’s Guide May 2004 ebug05_01 Lattice Semiconductor ORCA ORT/ORSO42G5 High-Speed SERDES Board User’s Guide Introduction This user’s guide describes the Lattice High-Speed SERDES Board for the ORCA ORT/ORSO42G5 device, a stand-alone evaluation PCB that provides a functional platform for device feature demonstrations. The board includes the following features: • Power connections • programming support • On-board and external reference clock sources • Discrete high-speed interface SMA test points and clock connections • ORCAstra Demonstration Software interface • Varied high-speed layout structures The contents of this user’s guide include top level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics for version of the board. Figure 1 shows the functional partitioning of the board. Figure ORT/ORSO42G5 High-Speed SERDES Board Benchtop Power Supply Jacks ORCAstra Interface Benchtop Power Supply Jacks HDIN/HDOUT Test SMAs Reference Clocks Generic FPGA I/O Switches & LEDs ispVM Programming Lattice Semiconductor ORCA ORT/ORSO42G5 High-Speed SERDES Board User’s Guide An 8-pin connector that provides the interface to the cable. Pin Number Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8 Signal VDD TDO TDI N/C N/C TMS GND TCK A 7-pin serial connector used for serial Pin Number Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Signal GND NC PROGRMN DONE D0 CCLK VDD Header Connections Standard headers are provided for interconnecting points on the board. This can be accomplished with IDC connectors and ribbon cable for bus connections or pin socket patch cords such as Pomona Electronics #5948 jumpers shunts are also used for board selections such as Sullins Electronics P/N SPC02SYAN D1, D2 These LEDs indicate the status of to the FPGA DONE/INITN status pins. When D2 is illuminated this indicates the successful completion of When D1illuminates, this indicates that programming was aborted or reinitialized. Lattice Semiconductor ORCA ORT/ORSO42G5 High-Speed SERDES Board User’s Guide J23, 25 These standard 3x1 headers provide connections of the PROGRAMN and RESETN control pins. For standard evaluation board use, a 2-pin shunt should be placed across pins 2 and This will connect the pins to on-board push-button switches. Pin Number Pin 1 Pin 2 Pin 3 Pin 1 Pin 2 Pin 3 Signal Global PROGRMN Local Global RESETN Local

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ORT/ORSO42G5 High-Speed SERDES Board

User’s Guide

May 2004 ebug05_01

Lattice Semiconductor

ORCA ORT/ORSO42G5 High-Speed SERDES Board User’s Guide

Introduction

This user’s guide describes the Lattice High-Speed SERDES Board for the ORCA ORT/ORSO42G5 device, a stand-alone evaluation PCB that provides a functional platform for device feature demonstrations. The board includes the following features:
• Power connections
• programming support
• On-board and external reference clock sources
• Discrete high-speed interface SMA test points and clock connections
• ORCAstra Demonstration Software interface
• Varied high-speed layout structures

The contents of this user’s guide include top level functional descriptions of the various portions of the evaluation board, descriptions of the on-board connectors, diodes and switches and a complete set of schematics for version of the board. Figure 1 shows the functional partitioning of the board.

Figure ORT/ORSO42G5 High-Speed SERDES Board

Benchtop Power Supply Jacks

ORCAstra Interface

Benchtop Power Supply Jacks

HDIN/HDOUT Test SMAs

Reference Clocks

Generic FPGA I/O Switches & LEDs
ispVM Programming

Lattice Semiconductor

ORCA ORT/ORSO42G5 High-Speed SERDES Board User’s Guide

An 8-pin connector that provides the interface to the cable.

Pin Number Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7 Pin 8

Signal VDD TDO TDI N/C N/C TMS GND TCK

A 7-pin serial connector used for serial

Pin Number Pin 1 Pin 2 Pin 3 Pin 4 Pin 5 Pin 6 Pin 7

Signal GND NC PROGRMN DONE D0 CCLK VDD

Header Connections

Standard headers are provided for interconnecting points on the board. This can be accomplished with IDC connectors and ribbon cable for bus connections or pin socket patch cords such as Pomona Electronics #5948 jumpers shunts are also used for board selections such as Sullins Electronics P/N SPC02SYAN

D1, D2

These LEDs indicate the status of to the FPGA DONE/INITN status pins. When D2 is illuminated this indicates the successful completion of When D1illuminates, this indicates that programming was aborted or reinitialized.

Lattice Semiconductor

ORCA ORT/ORSO42G5 High-Speed SERDES Board User’s Guide

J23, 25

These standard 3x1 headers provide connections of the PROGRAMN and RESETN control pins. For standard evaluation board use, a 2-pin shunt should be placed across pins 2 and This will connect the pins to on-board push-button switches.

Pin Number

Pin 1

Pin 2

Pin 3

Pin 1

Pin 2

Pin 3

Signal Global PROGRMN Local Global RESETN Local

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ORSO42G5-EV Datasheet file may be downloaded here without warranties.

Datasheet ID: ORSO42G5-EV 645495