ICE65P04F-TCB196C

ICE65P04F-TCB196C Datasheet

iCE65 P-Series Ultra Low-Power mobileFPGA Family

Part	Datasheet
ICE65P04F-TCB196C	ICE65P04F-TCB196C (pdf)

Related Parts	Information
ICE65P04F-TCB121C	ICE65P04F-TCB121C
ICE65P04F-TCB284I	ICE65P04F-TCB284I
ICE65P04F-TCB196I	ICE65P04F-TCB196I
ICE65P04F-TCB121I	ICE65P04F-TCB121I
ICE65P04F-TCB284C	ICE65P04F-TCB284C

PDF Datasheet Preview
iCE65 P-Series Ultra Low-Power mobileFPGA Family April 22, 2011 SiliconBlue Data Sheet High-density, ultra low-power single-chip, SRAM mobileFPGA family specifically designed for hand-held applications and long battery life Integrated Phase-Locked Loop PLL Clock multiplication/division for display, serializer/deserializer SerDes , and memory interface applications Up to 533 MHz PLL Output Reprogrammable from a variety of methods and sources Self configuration from external, commodity SPI serial Flash PROM Slave configuration by a processor using SPI-like serial interface in as little as 20 us. Self configuration from embedded, secure Nonvolatile Configuration Memory NVCM ideal for volume production superior design security no exposed data Proven, high-volume 65 nm, low-power CMOS technology Figure 1 iCE65P P-Series Family Architectural Features 9+45µuAA aatt ff 302k.7H6z8 kTHypzi cTayl pical Programmable Logic Block PLB I/O Bank 0 Programmable Interconnect 8 Logic Cells = Programmable Logic Block I/O Bank 1 Programmable Interconnect 4Kbit RAM 4Kbit RAM Programmable Interconnect I/O Bank 3 JTAG NVCM PLL I/O Bank 2 SPI Config Phase-Locked Loop Nonvolatile Configuration Memory NVCM Carry logic Four-input Look-Up Table LUT4 Flip-flop with enable and reset controls Flexible programmable logic and programmable interconnect fabric Over 12K look-up tables LUT4 and flip-flops Low-power logic and interconnect Flexible I/O pins to simplify system interfaces Ordering Information Figure 2 describes the iCE65P ordering codes for all packaged components. See the separate DiePlus data sheets when ordering die-based products. Figure 2 iCE65P Ordering Codes packaged, non-die components iCE65P 04 F -T CB 284 C Logic Cells x1,000 044,, 0088, 12 Configuration Memory F = NVCM + reprogrammable Power Consumption/ Speed -T = High speed Temperature Range C = Commercial I = ITnAJd=us0t°ritaol 70° Celsius TJA= to 85° Celsius Package Leads Package Style CB = chip-scale ball grid CS = wafer level chip-scale package mm pitch VQ = very-thin quad flat pack package iCE65P devices come standard in the higher speed “-T” version. iCE65P devices are available in two operating temperature ranges, one for typical commercial applications, the other with an extended temperature range for industrial and telecommunications applications. The ordering code also specifies the device package option, as described further in Table Programmable Logic Block PLB Generally, a logic design for an iCE65P component is created using a high-level hardware description language such as Verilog or VHDL. The SiliconBlue Technologies development software then synthesizes the high-level description into equivalent functions built using the programmable logic resources within each iCE65P device. Both sequential and combinational functions are constructed from an array of Programmable Logic Blocks PLBs . Each PLB contains eight Logic Cells LCs , as pictured in Figure 3, and share common control inputs, such as clocks, reset, and enable controls. PLBs are connected to one another and other logic functions using the rich Programmable Interconnect resources. SiliconBlue Technologies Corporation 22-APR-2011 3 iCE65 P-Series Ultra-Low Power mobileFPGA Family Logic Cell LC Each iCE65P device contains thousands of Logic Cells LCs , as listed in Table Each Logic Cell includes three primary logic elements, shown in Figure A four-input Look-Up Table LUT4 builds any combinational logic function, of any complexity, of up to four inputs. Similarly, the LUT4 element behaves as a 16x1 Read-Only Memory ROM . Combine and cascade multiple LUT4s to create wider logic functions. A „D‟-style Flip-Flop DFF , with an optional clock-enable and reset control input, builds sequential logic functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following device configuration. Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters, comparators, binary counters and some wide, cascaded logic functions. The output from a Logic Cell is available to all inputs to all eight Logic Cells within the Programmable Logic Block. Similarly, the Logic Cell output feeds into the Error! Reference source not found. fabric to connect to other eatures on the iCE65P device. Look-Up Table LUT4 The four-input Look-Up Table LUT4 function implements any and all combinational logic functions, regardless of complexity, of between zero and four inputs. Zero-input functions include “High” 1 and “Low” The LUT4 function has four inputs, labeled I0, I1, I2, and I3. Three of the four inputs are shared with the Carry Logic function, as shown in Figure The bottom-most LUT4 input connects either to the I3 input or to the Carry Logic output from the previous Logic Cell. The output from the LUT4 function connects to the flip-flop within the same Logic Cell. The LUT4 output or the flip-flop output then connects to the programmable interconnect. For detailed LUT4 internal timing, see Table ‘D’-style Flip-Flop DFF The „D‟-style flip-flop DFF optionally stores state information for the application. Figure 3 Programmable Logic Block and Logic Cell Shared Block-Level Controls Programmable Logic Block PLB Clock Enable Set/Reset Carry Logic Logic Cell I1 I2 LUT4 8 Logic Cells LCs 22-APR-2011 4 Four-input Look-Up Table LUT4 Flip-flop with optional enable and set or reset controls = Statically defined by configuration program SiliconBlue Technologies Corporation SiliconBlue The flip-flop has a data input, „D‟, and a data output, „Q‟. Additionally, each flip-flop has up to three control signals that are shared among all flip-flops in all Logic Cells within the PLB, as shown in Figure Table 3 describes the behavior of the flip-flop based on inputs and upon the specific DFF design primitive used or synthesized. Table 3 ‘D’-Style Flip-Flop Behavior Flip-Flop Inputs Primitive Check if the iCE65P is enabled to configure from the Nonvolatile Configuration Memory NVCM . If the iCE65P device has NVCM memory „F‟ ordering code but the NVCM is yet unprogrammed, then the iCE65P device is not enabled to configure from NVCM. Conversely, if the NVCM is programmed, the iCE65P device will configure from NVCM. If enabled to configure from NVCM, the iCE65P device configures itself using the Nonvolatile Configuration Memory NVCM . If not enabled to configure from NVCM, then the iCE65P FPGA configures using the SPI Master Configuration Interface. If the SPI_SS_B pin is sampled as a logic „0‟ Low , then the iCE65P device waits to be configured from an external controller or from another iCE65P device in SPI Master Configuration Mode using an SPI-like interface. 22-APR-2011 30 SiliconBlue Technologies Corporation Figure 23 Device Configuration Control Flow Power-Up SiliconBlue CDONE = 0 Is Power-On Reset POR Released? iCE65 checks that all required supply voltages are within acceptable range CRESET_B = High? Holding CRESET_B Low delays the start of configuration State of SPI_SS_B pin sampled SPI_SS_B = High? No CCoonnfifgiguurreeafsroSmPI PNerVipChMal A device with an unprogrammed NVCM is not enabled for configuration. NVCM Enabled for Configuration? Yes Configure from NVCM Configure from SPI Flash PROM CDONE = 1 CRESET_B = Low? After configuration ends, pulse the CRESET_B pin Low for 250 ns or longer to restart configuration process or cycle the power Configuration Image Size Table 28 shows the number of memory bits required to configure an iCE65P device. Two values are provided for each device. The “Logic Only” value indicates the minimum configuration size, the number of bits required to configure only the logic fabric, leaving the RAM4K blocks uninitialized. The “Logic + RAM4K” column indicates the maximum configuration size, the number of bits to configure the logic fabric and to pre-initialize all the RAM4K blocks. Device iCE65P04 Table 28 iCE65P Configuration Image Size Kbits MINIMUM MAXIUM Logic Only Logic + RAM4K RAM4K not initialized RAM4K pre-initialized 453 Kbits 533 Kbits SiliconBlue Technologies Corporation

PDF Datasheet Preview

iCE65 P-Series Ultra Low-Power mobileFPGA Family

April 22, 2011

SiliconBlue

Data Sheet

High-density, ultra low-power single-chip,

SRAM mobileFPGA family specifically designed for hand-held applications and long battery life

Integrated Phase-Locked Loop PLL

Clock multiplication/division for display, serializer/deserializer SerDes , and memory interface applications

Up to 533 MHz PLL Output

Reprogrammable from a variety of
methods and sources

Self configuration from external, commodity SPI serial Flash PROM

Slave configuration by a processor using SPI-like serial interface in as little as 20 us.

Self configuration from embedded, secure Nonvolatile Configuration Memory NVCM
ideal for volume production
superior design security no exposed data

Proven, high-volume 65 nm, low-power

CMOS technology

Figure 1 iCE65P P-Series Family Architectural Features
9+45µuAA aatt ff 302k.7H6z8 kTHypzi cTayl pical

Programmable Logic Block PLB

I/O Bank 0

Programmable Interconnect
8 Logic Cells = Programmable Logic Block

I/O Bank 1

Programmable Interconnect
4Kbit RAM 4Kbit RAM

Programmable Interconnect

I/O Bank 3

JTAG

NVCM

PLL I/O Bank 2

SPI Config

Phase-Locked Loop

Nonvolatile Configuration Memory NVCM

Carry logic Four-input

Look-Up Table LUT4

Flip-flop with enable and reset controls

Flexible programmable logic and programmable
interconnect fabric Over 12K look-up tables LUT4 and flip-flops Low-power logic and interconnect

Flexible I/O pins to simplify system interfaces
Ordering Information
Figure 2 describes the iCE65P ordering codes for all packaged components. See the separate DiePlus data sheets when ordering die-based products.
Figure 2 iCE65P Ordering Codes packaged, non-die components
iCE65P 04 F -T CB 284 C

Logic Cells x1,000
044,, 0088, 12

Configuration Memory F = NVCM + reprogrammable

Power Consumption/ Speed
-T = High speed

Temperature Range C = Commercial I = ITnAJd=us0t°ritaol 70° Celsius

TJA= to 85° Celsius

Package Leads

Package Style

CB = chip-scale ball grid CS = wafer level chip-scale package mm pitch VQ = very-thin quad flat pack package
iCE65P devices come standard in the higher speed “-T” version.
iCE65P devices are available in two operating temperature ranges, one for typical commercial applications, the other with an extended temperature range for industrial and telecommunications applications. The ordering code also specifies the device package option, as described further in Table

Programmable Logic Block PLB

Generally, a logic design for an iCE65P component is created using a high-level hardware description language such as Verilog or VHDL. The SiliconBlue Technologies development software then synthesizes the high-level description into equivalent functions built using the programmable logic resources within each iCE65P device. Both sequential and combinational functions are constructed from an array of Programmable Logic Blocks PLBs . Each PLB contains eight Logic Cells LCs , as pictured in Figure 3, and share common control inputs, such as clocks, reset, and enable controls.

PLBs are connected to one another and other logic functions using the rich Programmable Interconnect resources.

SiliconBlue Technologies Corporation
22-APR-2011 3
iCE65 P-Series Ultra-Low Power mobileFPGA Family

Logic Cell LC

Each iCE65P device contains thousands of Logic Cells LCs , as listed in Table Each Logic Cell includes three primary logic elements, shown in Figure

A four-input Look-Up Table LUT4 builds any combinational logic function, of any complexity, of up to four inputs. Similarly, the LUT4 element behaves as a 16x1 Read-Only Memory ROM . Combine and cascade multiple LUT4s to create wider logic functions.

A „D‟-style Flip-Flop DFF , with an optional clock-enable and reset control input, builds sequential logic functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following device configuration.

Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters, comparators, binary counters and some wide, cascaded logic functions.

The output from a Logic Cell is available to all inputs to all eight Logic Cells within the Programmable Logic Block. Similarly, the Logic Cell output feeds into the Error! Reference source not found. fabric to connect to other eatures on the iCE65P device.

Look-Up Table LUT4

The four-input Look-Up Table LUT4 function implements any and all combinational logic functions, regardless of complexity, of between zero and four inputs. Zero-input functions include “High” 1 and “Low” The LUT4 function has four inputs, labeled I0, I1, I2, and I3. Three of the four inputs are shared with the Carry Logic function, as shown in Figure The bottom-most LUT4 input connects either to the I3 input or to the Carry Logic output from the previous Logic Cell.

The output from the LUT4 function connects to the flip-flop within the same Logic Cell. The LUT4 output or the flip-flop output then connects to the programmable interconnect.

For detailed LUT4 internal timing, see Table
‘D’-style Flip-Flop DFF

The „D‟-style flip-flop DFF optionally stores state information for the application.

Figure 3 Programmable Logic Block and Logic Cell

Shared Block-Level Controls

Programmable Logic Block PLB

Clock

Enable

Set/Reset

Carry Logic

Logic Cell

I1 I2

LUT4
8 Logic Cells LCs
22-APR-2011 4

Four-input Look-Up Table LUT4

Flip-flop with optional enable and set or reset controls
= Statically defined by configuration program

SiliconBlue Technologies Corporation

SiliconBlue

The flip-flop has a data input, „D‟, and a data output, „Q‟. Additionally, each flip-flop has up to three control signals that are shared among all flip-flops in all Logic Cells within the PLB, as shown in Figure Table 3 describes the behavior of the flip-flop based on inputs and upon the specific DFF design primitive used or synthesized.

Table 3 ‘D’-Style Flip-Flop Behavior

Flip-Flop

Inputs

Primitive
Check if the iCE65P is enabled to configure from the Nonvolatile Configuration Memory NVCM . If the iCE65P device has NVCM memory „F‟ ordering code but the NVCM is yet unprogrammed, then the iCE65P device is not enabled to configure from NVCM. Conversely, if the NVCM is programmed, the iCE65P device will configure from NVCM.

If enabled to configure from NVCM, the iCE65P device configures itself using the Nonvolatile Configuration Memory NVCM .

If not enabled to configure from NVCM, then the iCE65P FPGA configures using the SPI Master Configuration Interface.

If the SPI_SS_B pin is sampled as a logic „0‟ Low , then the iCE65P device waits to be configured from an external controller or from another iCE65P device in SPI Master Configuration Mode using an SPI-like interface.
22-APR-2011 30

SiliconBlue Technologies Corporation

Figure 23 Device Configuration Control Flow

Power-Up

SiliconBlue

CDONE = 0

Is Power-On Reset POR

Released?
iCE65 checks that all required supply voltages are within acceptable range

CRESET_B = High?

Holding CRESET_B Low delays the start of configuration

State of SPI_SS_B pin sampled

SPI_SS_B = High?

No CCoonnfifgiguurreeafsroSmPI

PNerVipChMal

A device with an unprogrammed NVCM is not enabled for configuration.

NVCM Enabled for Configuration?

Yes Configure from

NVCM

Configure from SPI Flash PROM

CDONE = 1

CRESET_B = Low?

After configuration ends, pulse the CRESET_B pin Low for 250 ns or longer to restart configuration process or cycle the power

Configuration Image Size

Table 28 shows the number of memory bits required to configure an iCE65P device. Two values are provided for each device. The “Logic Only” value indicates the minimum configuration size, the number of bits required to configure only the logic fabric, leaving the RAM4K blocks uninitialized. The “Logic + RAM4K” column indicates the maximum configuration size, the number of bits to configure the logic fabric and to pre-initialize all the RAM4K blocks.

Device
iCE65P04

Table 28 iCE65P Configuration Image Size Kbits

MINIMUM

MAXIUM

Logic Only

Logic + RAM4K

RAM4K not initialized

RAM4K pre-initialized
453 Kbits
533 Kbits

SiliconBlue Technologies Corporation

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ICE65P04F-TCB196C Datasheet file may be downloaded here without warranties.

Datasheet ID: ICE65P04F-TCB196C 645477