ICE65L04F-TCS63I

ICE65L04F-TCS63I Datasheet

iCE65 Ultra Low-Power mobileFPGA Family

Part	Datasheet
ICE65L04F-TCS63I	ICE65L04F-TCS63I (pdf)

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PDF Datasheet Preview
iCE65 Ultra Low-Power mobileFPGA Family March 30, 2012 Data Sheet First high-density, ultra low-power single-chip, SRAM mobileFPGA family specifically designed for hand-held applications and long battery life Figure 1 iCE65 Family Architectural Features 12 µA at f =0 kHz Typical Programmable Logic Block PLB 12 µA in static mode Two power/speed options Low Power High speed I/O Bank 0 Programmable Interconnect 8 Logic Cells = Programmable Logic Block I/O Bank 1 Programmable Interconnect 4Kbit RAM 4Kbit RAM Programmable Interconnect Up to 256 MHz internal performance I/O Bank 3 Reprogrammable from a variety of sources and methods Processor-like mode self-configures from external, commodity SPI serial Flash PROM Downloaded by processor using SPI-like serial interface in as little as 20 µs JTAG In-system programmable, ASIC-like mode loads from secure, internal Nonvolatile Configuration Memory NVCM NVCM Programmable Interconnect Ideal for volume production Superior design and intellectual property protection no exposed data Proven, high-volume 65 nm, low-power CMOS technology Low leakage, µW static power I/O Bank 2 Nonvolatile Configuration Memory NVCM SPI Config Carry logic Four-input Look-Up Table LUT4 Flip-flop with enable and reset controls Lower core voltage, lowest dynamic power Flexible programmable logic and programmable interconnect fabric Over 7,600 look-up tables LUT4 and flip-flops Low-power logic and interconnect Flexible I/O pins to simplify system interfaces Up to 222 programmable I/O pins Four independently-powered I/O banks support for 3.3V, Ordering Information Figure 2 describes the iCE65 ordering codes for all packaged, non-NVCM Programed components. See the separate DiePlus data sheets when ordering die-based products. Figure 2 iCE65 Ordering Codes Standard Device iCE65L 04 F -L CB 132 C Logic Cells x1,000 010,4,040, 808 Configuration Memory F = NVCM + reprogrammable Power Consumption/ Speed -L = Low power -T = High speed Temperature Range C = Commercial TAJ = 0° to Industrial 70° Celsius TAJ = to 85° Celsius Package Leads Package Style CB = chip-scale ball grid CS = wafer level chip-scale package mm pitch VQ = very-thin quad flat pack package QN = quad flat no-lead package iCE65 devices offer two power consumption, speed options. Standard products “-L” ordering code have low standby and dynamic power consumption. The “-T” provides higher-speed logic. Similarly, iCE65 devices are available in two operating temperature ranges, one for typical commercial applications, the other with an extended temperature range for industrial and telecommunications applications. The ordering code also specifies the device package option, as described further in Table Figure 3 describes the iCE65 ordering codes for all packaged, NVCM Programmed components. Figure 3 iCE65 Ordering Codes NVCM Programmed Device iCE65L 01 F ZZZ ZZZZ Logic Cells x1000 01, 04, 08 Configuration Memory F = NVCM + reprogrammable 30-MAR-2012 4 Lattice Semiconductor Corporation Programmable Logic Block PLB Generally, a logic design for an iCE65 component is created using a high-level hardware description language such as Verilog or VHDL. The Lattice Semiconductor development software then synthesizes the high-level description into equivalent functions built using the programmable logic resources within each iCE65 device. Both sequential and combinational functions are constructed from an array of Programmable Logic Blocks PLBs . Each PLB contains eight Logic Cells LCs , as pictured in Figure 4, and share common control inputs, such as clocks, reset, and enable controls. PLBs are connected to one another and other logic functions using the rich Programmable Interconnect resources. Logic Cell LC Each iCE65 device contains thousands of Logic Cells LCs , as listed in Table Each Logic Cell includes three primary logic elements, shown in Figure A four-input Look-Up Table LUT4 builds any combinational logic function, of any complexity, of up to four inputs. Similarly, the LUT4 element behaves as a 16x1 Read-Only Memory ROM . Combine and cascade multiple LUT4s to create wider logic functions. Figure 4 Programmable Logic Block and Logic Cell A ‘D’-style Flip-Flop DFF , with an optional clock-enable and reset control input, builds sequential logic functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following device configuration. Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders, subtracters, comparators, binary counters and some wide, cascaded logic functions. The output from a Logic Cell is available to all inputs to all eight Logic Cells within the Programmable Logic Block. Similarly, the Logic Cell output feeds into fabric to connect to other features on the iCE65 device. Programmable Logic Block PLB I0 I1 I2 I3 Shared Block-Level Controls Clock Enable Set/Reset Carry Logic Logic Cell LUT4 8 Logic Cells LCs Four-input Look-Up Table LUT4 Flip-flop with optional enable and set or reset controls = Statically defined by configuration program Lattice Semiconductor Corporation 30-MAR-2011 5 iCE65 Ultra Low-Power mobileFPGA Family Look-Up Table LUT4 The four-input Look-Up Table LUT4 function implements any and all combinational logic functions, regardless of complexity, of between zero and four inputs. Zero-input functions include “High” 1 and “Low” The LUT4 function has four inputs, labeled I0, I1, I2, and I3. Three of the four inputs are shared with the Carry Logic function, as shown in Figure The bottom-most LUT4 input connects either to the I3 input or to the Carry Logic output from the previous Logic Cell. The output from the LUT4 function connects to the flip-flop within the same Logic Cell. The LUT4 output or the flip-flop output then connects to the programmable interconnect. For detailed LUT4 internal timing, see Table ‘D’-style Flip-Flop DFF The ‘D’-style flip-flop DFF optionally stores state information for the application. Check if the iCE65 is enabled to configure from the Nonvolatile Configuration Memory NVCM . If the iCE65 device has NVCM memory ‘F’ ordering code but the NVCM is yet unprogrammed, then the iCE65 device is not enabled to configure from NVCM. Conversely, if the NVCM is programmed, the iCE65 device will configure from NVCM. If enabled to configure from NVCM, the iCE65 device configures itself using NVCM. If not enabled to configure from NVCM, then the iCE65 FPGA configures using the SPI Master Configuration Interface. If the SPI_SS_B pin is sampled as a logic ‘0’ Low , then the iCE65 device waits to be configured from an external controller or from another iCE65 device in SPI Master Configuration Mode using an SPI-like interface. Lattice Semiconductor Corporation 30-MAR-2011 25 iCE65 Ultra Low-Power mobileFPGA Family Figure 20 Device Configuration Control Flow Power-Up CDONE = 0 Is Power-On Reset POR Released? iCE65 checks that all required supply voltages are within acceptable range CRESET_B = High? Holding CRESET_B Low delays the start of configuration State of SPI_SS_B pin sampled SPI_SS_B = High? No CCoonnfifgiguurreeafsroSmPI PNerVipChMal A device with an unprogrammed NVCM is not enabled for configuration. NVCM Enabled for Configuration? Yes Configure from NVCM Configure from SPI Flash PROM CDONE = 1 CRESET_B = Low? After configuration ends, pulse the CRESET_B pin Low for 250 ns or longer to restart configuration process or cycle the power Configuration Image Size Table 23 shows the number of memory bits required to configure an iCE65 device. Two values are provided for each device. The “Logic Only” value indicates the minimum configuration size, the number of bits required to configure only the logic fabric, leaving the RAM4K blocks uninitialized. The “Logic + RAM4K” column indicates the maximum configuration size, the number of bits to configure the logic fabric and to pre-initialize all the RAM4K blocks. 30-MAR-2012 26 Lattice Semiconductor Corporation Device iCE65L01 iCE65L04 iCE65L08 Table 21 iCE65 Configuration Image Size Kbits MINIMUM MAXIUM Logic Only Logic + RAM4K RAM4K not initialized RAM4K pre-initialized 181 Kbits 4-SEPT-2008 Updated package roadmap Table 2 and updated ordering codes Figure Updated Figure Updated Figure Added CS63 package footprint Figure 36 , pinout Table 39 and Package. 31-MAY-2008 Initial public release. Lattice Semiconductor Corporation 30-MAR-2011 109 iCE65 Ultra Low-Power mobileFPGA Family 2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. cumentation services by Prevailing Technology, Inc. 30-MAR-2012 110 Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon 97124-6421 United States of America Tel +1 503 268 8000 Fax +1 503 268 8347 Lattice Semiconductor Corporation

PDF Datasheet Preview

iCE65 Ultra Low-Power mobileFPGA Family

March 30, 2012

Data Sheet

First high-density, ultra low-power
single-chip, SRAM mobileFPGA family specifically designed for hand-held applications and long battery life

Figure 1 iCE65 Family Architectural Features
12 µA at f =0 kHz Typical

Programmable Logic Block PLB
12 µA in static mode

Two power/speed options Low Power High speed

I/O Bank 0

Programmable Interconnect
8 Logic Cells = Programmable Logic Block

I/O Bank 1

Programmable Interconnect
4Kbit RAM 4Kbit RAM

Programmable Interconnect

Up to 256 MHz internal performance

I/O Bank 3

Reprogrammable from a variety of
sources and methods

Processor-like mode self-configures from external, commodity SPI serial Flash PROM

Downloaded by processor using SPI-like serial interface in as little as 20 µs

JTAG

In-system programmable, ASIC-like mode loads from secure, internal Nonvolatile Configuration Memory NVCM

NVCM Programmable Interconnect

Ideal for volume production

Superior design and intellectual property protection no exposed data

Proven, high-volume 65 nm, low-power

CMOS technology

Low leakage, µW static power

I/O Bank 2 Nonvolatile Configuration Memory NVCM

SPI Config

Carry logic Four-input

Look-Up Table LUT4

Flip-flop with enable and reset controls

Lower core voltage, lowest dynamic power

Flexible programmable logic and programmable
interconnect fabric Over 7,600 look-up tables LUT4 and flip-flops Low-power logic and interconnect

Flexible I/O pins to simplify system interfaces

Up to 222 programmable I/O pins Four independently-powered I/O banks support for 3.3V,
Ordering Information
Figure 2 describes the iCE65 ordering codes for all packaged, non-NVCM Programed components. See the separate DiePlus data sheets when ordering die-based products.
Figure 2 iCE65 Ordering Codes Standard Device
iCE65L 04 F -L CB 132 C

Logic Cells x1,000
010,4,040, 808

Configuration Memory F = NVCM + reprogrammable

Power Consumption/ Speed
-L = Low power -T = High speed

Temperature Range

C = Commercial

TAJ = 0° to Industrial
70°

Celsius

TAJ = to 85° Celsius

Package Leads

Package Style

CB = chip-scale ball grid CS = wafer level chip-scale package mm pitch VQ = very-thin quad flat pack package QN = quad flat no-lead package
iCE65 devices offer two power consumption, speed options. Standard products “-L” ordering code have low standby and dynamic power consumption. The “-T” provides higher-speed logic.
Similarly, iCE65 devices are available in two operating temperature ranges, one for typical commercial applications, the other with an extended temperature range for industrial and telecommunications applications. The ordering code also specifies the device package option, as described further in Table
Figure 3 describes the iCE65 ordering codes for all packaged, NVCM Programmed components. Figure 3 iCE65 Ordering Codes NVCM Programmed Device
iCE65L 01 F ZZZ ZZZZ

Logic Cells x1000 01, 04, 08

Configuration Memory F = NVCM + reprogrammable
30-MAR-2012 4

Lattice Semiconductor Corporation

Programmable Logic Block PLB

Generally, a logic design for an iCE65 component is created using a high-level hardware description language such as Verilog or VHDL. The Lattice Semiconductor development software then synthesizes the high-level description into equivalent functions built using the programmable logic resources within each iCE65 device. Both sequential and combinational functions are constructed from an array of Programmable Logic Blocks PLBs . Each PLB contains eight Logic Cells LCs , as pictured in Figure 4, and share common control inputs, such as clocks, reset, and enable controls.

PLBs are connected to one another and other logic functions using the rich Programmable Interconnect resources.

Logic Cell LC

Each iCE65 device contains thousands of Logic Cells LCs , as listed in Table Each Logic Cell includes three primary logic elements, shown in Figure

A four-input Look-Up Table LUT4 builds any combinational logic function, of any complexity, of up to
four inputs. Similarly, the LUT4 element behaves as a 16x1 Read-Only Memory ROM . Combine and cascade multiple LUT4s to create wider logic functions.

Figure 4 Programmable Logic Block and Logic Cell

A ‘D’-style Flip-Flop DFF , with an optional clock-enable and reset control input, builds sequential logic
functions. Each DFF also connects to a global reset signal that is automatically asserted immediately following device configuration.

Carry Logic boosts the logic efficiency and performance of arithmetic functions, including adders,
subtracters, comparators, binary counters and some wide, cascaded logic functions.

The output from a Logic Cell is available to all inputs to all eight Logic Cells within the Programmable Logic Block. Similarly, the Logic Cell output feeds into fabric to connect to other features on the iCE65 device.

Programmable Logic Block PLB

I0 I1 I2 I3

Shared Block-Level Controls

Clock

Enable

Set/Reset

Carry Logic

Logic Cell

LUT4
8 Logic Cells LCs

Four-input Look-Up Table LUT4

Flip-flop with optional enable and set or reset controls
= Statically defined by configuration program

Lattice Semiconductor Corporation
30-MAR-2011 5
iCE65 Ultra Low-Power mobileFPGA Family

Look-Up Table LUT4

The four-input Look-Up Table LUT4 function implements any and all combinational logic functions, regardless of complexity, of between zero and four inputs. Zero-input functions include “High” 1 and “Low” The LUT4 function has four inputs, labeled I0, I1, I2, and I3. Three of the four inputs are shared with the Carry Logic function, as shown in Figure The bottom-most LUT4 input connects either to the I3 input or to the Carry Logic output from the previous Logic Cell.

The output from the LUT4 function connects to the flip-flop within the same Logic Cell. The LUT4 output or the flip-flop output then connects to the programmable interconnect.

For detailed LUT4 internal timing, see Table
‘D’-style Flip-Flop DFF

The ‘D’-style flip-flop DFF optionally stores state information for the application.
Check if the iCE65 is enabled to configure from the Nonvolatile Configuration Memory NVCM . If the iCE65 device has NVCM memory ‘F’ ordering code but the NVCM is yet unprogrammed, then the iCE65 device is not enabled to configure from NVCM. Conversely, if the NVCM is programmed, the iCE65 device will configure from NVCM.

If enabled to configure from NVCM, the iCE65 device configures itself using NVCM.

If not enabled to configure from NVCM, then the iCE65 FPGA configures using the SPI Master Configuration Interface.

If the SPI_SS_B pin is sampled as a logic ‘0’ Low , then the iCE65 device waits to be configured from an
external controller or from another iCE65 device in SPI Master Configuration Mode using an SPI-like interface.

Lattice Semiconductor Corporation
30-MAR-2011 25
iCE65 Ultra Low-Power mobileFPGA Family

Figure 20 Device Configuration Control Flow

Power-Up

CDONE = 0

Is Power-On Reset POR

Released?
iCE65 checks that all required supply voltages are within acceptable range

CRESET_B = High?

Holding CRESET_B Low delays the start of configuration

State of SPI_SS_B pin sampled

SPI_SS_B = High?

No CCoonnfifgiguurreeafsroSmPI

PNerVipChMal

A device with an unprogrammed NVCM is not enabled for configuration.

NVCM Enabled for Configuration?

Yes Configure from

NVCM

Configure from SPI Flash PROM

CDONE = 1

CRESET_B = Low?

After configuration ends, pulse the CRESET_B pin Low for 250 ns or longer to restart configuration process or cycle the power

Configuration Image Size

Table 23 shows the number of memory bits required to configure an iCE65 device. Two values are provided for each device. The “Logic Only” value indicates the minimum configuration size, the number of bits required to configure only the logic fabric, leaving the RAM4K blocks uninitialized. The “Logic + RAM4K” column indicates the maximum configuration size, the number of bits to configure the logic fabric and to pre-initialize all the RAM4K blocks.
30-MAR-2012 26

Lattice Semiconductor Corporation

Device iCE65L01 iCE65L04 iCE65L08

Table 21 iCE65 Configuration Image Size Kbits

MINIMUM

MAXIUM

Logic Only

Logic + RAM4K

RAM4K not initialized

RAM4K pre-initialized
181 Kbits
4-SEPT-2008 Updated package roadmap Table 2 and updated ordering codes Figure Updated Figure Updated Figure

Added CS63 package footprint Figure 36 , pinout Table 39 and Package.
31-MAY-2008 Initial public release.

Lattice Semiconductor Corporation
30-MAR-2011 109
iCE65 Ultra Low-Power mobileFPGA Family
2012 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
cumentation services by Prevailing Technology, Inc.
30-MAR-2012 110

Lattice Semiconductor Corporation 5555 N.E. Moore Court Hillsboro, Oregon 97124-6421 United States of America

Tel +1 503 268 8000 Fax +1 503 268 8347

Lattice Semiconductor Corporation

Notice: we do not provide any warranties that information, datasheets, application notes, circuit diagrams, or software stored on this website are up-to-date or error free. The archived ICE65L04F-TCS63I Datasheet file may be downloaded here without warranties.

Datasheet ID: ICE65L04F-TCS63I 645476