ETHER-1GIG-E2-N3

ETHER-1GIG-E2-N3 Datasheet


Ethernet MAC Cores

Part Datasheet
ETHER-1GIG-E2-N3 ETHER-1GIG-E2-N3 ETHER-1GIG-E2-N3 (pdf)
Related Parts Information
ETHER-1GIG-XP-N3 ETHER-1GIG-XP-N3 ETHER-1GIG-XP-N3
ETHER-FAST-O4-N3 ETHER-FAST-O4-N3 ETHER-FAST-O4-N3
ETHER-1GIG-O4-N3 ETHER-1GIG-O4-N3 ETHER-1GIG-O4-N3
ETHER-1GIG-XM-N3 ETHER-1GIG-XM-N3 ETHER-1GIG-XM-N3
ETHER-1GIG-SC-N3 ETHER-1GIG-SC-N3 ETHER-1GIG-SC-N3
ETHER-FAST-XP-N3 ETHER-FAST-XP-N3 ETHER-FAST-XP-N3
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Ethernet MAC Cores

Home > Products > Intellectual Property > Lattice IP Cores > Ethernet MAC Cores

Ethernet MAC Cores

Overview

The Ethernet Media Access Controller MAC core can be configured to operate in either the Gigabit mode 1000 Mbits/sec data rate or the Fast Ethernet mode 10/100 Mbits/sec data rate . Netlist configurations of this core operate only in either the Gigabit mode or Fast Ethernet mode. The netlist cannot auto-negotiate between the two different modes.

The Ethernet MAC transmits and receives data between a host processor and an Ethernet network. The main function of the Ethernet MAC is to ensure that the Media Access rules specified in the IEEE standard are met while transmitting a frame of data over Ethernet. Figure 2 shows the transmission of data on the Ethernet network using the frame format. On the receiving side, the Ethernet MAC extracts the different components of a frame and transfers them to higher applications through the FIFO interface.

Compliant to IEEE 802.3z Standard Generic Host Interface Configurable 8-bit or 16-bit and Greater Data Bus 16-bit Wide Internal Data Path Full-duplex Operation in Gigabit Mode Full and Half Duplex in 10/100 Mode Transmit and Receive Statistics Vector Programmable Inter Packet Gap IPG Multicast Address Filtering Supports:

Full-duplex Control Using PAUSE Frames VLAN Tagged Frames Automatic Re-transmission on Collision
10/11/2011

Ethernet MAC Cores

Automatic Padding of Short Frames Optional FCS Transmission and Reception Optional MII Management Interface Module

Supports Jumbo Frames up to 8192 kbytes Reference Design for GMII to RGMII Bridge

Reduced pincount Gigabit Media Independent Interface

Evaluation Configurations

Evaluation Configurations Available for Series 4 ORCA FPGAs and FPSCs1 Name of Parameter File ether_fast_o4_3_002.lpc ether_1gig_o4_3_001.lpc

Mode Mbps
10/100
1000

CPU Data Width

MIIM Module

LUTs
2581
1747

ORCA 4 PFUs

Registers
1850
1313

External Pins

System EBRs RAM512
fMAX MHz

MHz sys_clk, 25MHz MII host clks

PHY side
125MHz GMII
1 Performance and utilization characteristics using ispLEVERTM software and targeting the ORCA4E04-2BA352C. When using this IP Core in a different density, package, speed or grade within the ORCA 4 family, performance may vary.

Evaluation Configurations Available for ispXPGA1 Name of Parameter File ether_1gig_xp_1_001.lpc ether_fast_xp_1_002.lpc

Mode Mbps
1000
10/100

CPU Data Width

MIIM Module

LUTs
Ordering Information

Part Numbers:

For ORCA 4 Fast Ethernet ETHER-FAST-O4-N3 For ORCA 4 Gigabit ETHER-1GIG-O4-N3 For ispXPGA Fast Ethernet ETHER-FAST-XP-N3 For ispXPGA Gigabit ETHER-1GIG-XP-N3 For LatticeECP/EC Fast Ethernet ETHER-FAST-E2-N3 For LatticeECP/EC Gigabit ETHER-1GIG-E2-N3 For LatticeXP Fast Ethernet ETHER-FAST-XM-N3 For LatticeXP Gigabit ETHER-1GIG-XM-N3 For LatticeSC Fast Ethernet ETHER-FAST-SC-N3 For LatticeSC Gigabit ETHER-1GIG-SC-N3

To find out how to purchase the Ethernet MAC IP Cores, please contact your local Lattice Sales Office.
10/11/2011
More datasheets: DDMMZ24H7SNA197 | NDB603AL | NDP603AL | FZ1200R17KE3B2NOSA1 | ETHER-1GIG-XP-N3 | ETHER-FAST-O4-N3 | ETHER-1GIG-O4-N3 | ETHER-1GIG-XM-N3 | ETHER-1GIG-SC-N3 | ETHER-FAST-XP-N3


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Datasheet ID: ETHER-1GIG-E2-N3 645464